Datenblatt für SN75161B-62B von Texas Instruments

SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Meets IEEE Standard 488-1978 (GPIB)
8-Channel Bidirectional Transceivers
Power-Up/Power-Down Protection
(Glitch Free)
Designed to Implement Control Bus
Interface
SN75161B Designed for Single Controller
SN75162B Designed for Multiple
Controllers
High-Speed, Low-Power Schottky Circuitry
Low Power Dissipation...72 mW Max Per
Channel
Fast Propagation Times . . . 22 ns Max
High-Impedance pnp Inputs
Receiver Hysteresis...650 mV Typ
Bus-Terminating Resistors Provided on
Driver Outputs
No Loading of Bus When Device Is
Powered Down (VCC = 0)
description
The SN75161B and SN75162B eight-channel,
general-purpose interface bus transceivers are
monolithic, high-speed, low-power Schottky
devices designed to meet the requirements of
IEEE Standard 488-1978. Each transceiver is
designed to provide the bus-management and
data-transfer signals between operating units of
a single- or multiple-controller instrumentation
system. When combined with the SN75160B octal
bus transceiver, the SN75161B or SN75162B
provides the complete 16-wire interface for the
IEEE-488 bus.
The SN75161B and SN75162B feature eight
driver-receiver pairs connected in a front-to-back
configuration to form input/output (I/O) ports at
both the bus and terminal sides. A power-
up/-down disable circuit is included on all bus and
receiver outputs. This provides glitch-free opera-
tion during VCC power up and power down.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
NC
GND
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
VCC
NC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
NC
DC
(TOP VIEW)
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
GND
VCC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
DC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GPIB
I/O Ports Terminal
I/O Ports
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
GND
VCC
NC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
DC
(TOP VIEW)
NC–No internal connection
SN75161B . . . DW OR N PACKAGE
SN75162B . . . DW PACKAGE
SN75162B ...N PACKAGE
GPIB
I/O Ports
Terminal
I/O Ports
GPIB
I/O Ports
Terminal
I/O Ports
*9 TEXAS INSTRUMENTS
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The direction of data through these driver-receiver pairs is determined by the DC, TE, and SC (on SN75162B)
enable signals. The SC input on the SN75162B allows the REN and IFC transceivers to be controlled
independently.
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high
impedance to the bus when supply voltage VCC is 0. The drivers are designed to handle loads up to 48 mA of
sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV
for increased noise immunity. All receivers have 3-state outputs to present a high impedance to the terminal
when disabled.
The SN75161B and SN75162B are characterized for operation from 0°C to 70°C.
Function Tables
SN75161B RECEIVE/TRANSMIT
CONTROLS BUS-MANAGEMENT CHANNELS DATA-TRANSFER CHANNELS
DC TE ATN†ATN†SRQ REN IFC EOI DAV NDAC NRFD
(Controlled by DC) (Controlled by TE)
H H H
R
T
R
R
T
T
R
R
H H L
R
T
R
R
R
T
R
R
L L H
T
R
T
T
R
R
T
T
L L L
T
R
T
T
T
R
T
T
H L X R T R R R R T T
L H X T R T T T T R R
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
†ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE
inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
SN75162B RECEIVE/TRANSMIT
CONTROLS BUS-MANAGEMENT CHANNELS DATA-TRANSFER CHANNELS
SC DC TE ATN†ATN†SRQ REN IFC EOI DAV NDAC NRFD
(Controlled by DC) (Controlled by SC) (Controlled by TE)
H H H
R
T
T
T
R
R
H H L
R
T
R
T
R
R
L L H
T
R
R
R
T
T
L L L
T
R
T
R
T
T
H L X R T R R T T
L H X T R T T R R
H T T
L R R
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
†ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE
inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
A1" a ATN 1a 7 EOI EOI sac 9 sac 2 REM REN a IFC 1 9 'FC J 6 DAV 2Q DAV J 4 NDAC E Q NDAC JI 5 NHFD 59 NHFD v2 JI TTms symbo‘ \s In accardance w11h IEEE Sm 9171984 and \EC Pubhcamn 617712. v Desugnates Esme oulpms Q Desugnates passwerpulmp oulpms *9 TEXAS INSTRUMENTS 9057 omca aox $55303 - DALLAS IEXAS 752s5 #574k’57éefi7éefi74rx éxévékvégw
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CHANNEL-IDENTIFICATION TABLE
NAME IDENTITY CLASS
DC Direction Control
TE Talk Enable Control
SC System Control (SN75162B only)
ATN Attention
SRQ Service Request
REN Remote Enable Bus
IFC Interface Clear Management
EOI End of Identity
DAV Data Valid
NDAC Not Data Accepted Data
NRFD Not Ready for Data Transfer
SN75161B logic symbol†
EN3
1
ATN
8
1
ATN 13
1
1
EOI
7
3
EOI 14
1
3
SRQ
1
SRQ 12
1
1
REN
2
1
REN 19
1
1
IFC
3
1
IFC 18
1
1
DAV
6
2
DAV 15
1
2
NDAC
4
2
NDAC 17
1
2
2
1
16
NRFD
2
EN1/G4
EN2/G5
5
4
5NRFD
TE 1
DC 11
This symbol is in accordance with IEEE Std 91-1984 and
IEC Publication 617-12.
Designates 3-state outputs
Designates passive-pullup outputs
9
SN75161B logic diagram (positive logic)
NRFD
5
NRFD 16
NDAC
4
NDAC 17
DAV
6
DAV 15
IFC
3
IFC 18
REN
2
REN 19
SRQ
9
SRQ 12
EOI
7
EOI 14
11
DC
1
TE
13
ATN 8ATN
TE EN2/Gs sc ATN ATN l5 EOI EOI l3 SRO SRO REN 20 HEN IFC '9 IFC DAV '6 DAV NDAC '8 59 NDAC E 6 NRFD '7 29 NRFD V2 JI TTms symnm \s m accordance wnh \EEE sm 9171954 and \EC Pubhcahon 517712 v Deswgnales same Du‘puts e Deswgnales passwerpmlup outpms Pm numbers shown are car «he N package. 97W 4 9057 omca aox $55303 - DALLAS IEXAS 752s5 %&7%&7%&7%~R7M7éfi [$472947
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75162B logic symbol†
EN3
≥1
ATN
1
ATN 14
1
1
EOI
6
EOI
1
6
SRQ
1
SRQ
1
1
REN
REN
1
3
IFC
IFC
1
DAV
2
DAV
1
2
NDAC
2
NDAC
1
2
2
1
NRFD
2
EN1/G4
EN2/G5
5
4
NRFD
TE
DC
This symbol is in accordance with IEEE Std 91-1984 and
IEC Publication 617-12.
Designates 3-state outputs
Designates passive-pullup outputs
EN3
12
2
1
15
SC
13
20
19
16
18
17
9
8
10
3
4
7
5
6
3
3
3
Pin numbers shown are for the N package.
SN75162B logic diagram (positive logic)
NRFDNRFD
NDACNDAC
DAVDAV
IFCIFC
RENREN
SRQSRQ
EOIEOI
DC
TE
ATN ATN
12
2
1
14
15
13
20
19
16
18
17
9
8
10
3
4
7
5
6
SC
M E IKE : 11a ..1 at” 1* *9 TEXAS INSTRUMENTS
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
NOM
4 kΩ
R(eq) 1.7 kΩ
NOM 10 kΩ
NOM
VCC
GND
Input/Output Port
Input/Output Port
GND
VCC
NOM
10 kΩ
NOM
4 kΩ
NOM
1.7 kΩ
NOM
9 kΩ
GND
Input
VCC
NOM
4 kΩ
EQUIVALENT OF ALL CONTROL INPUTS TYPICAL OF SRQ, NDAC, AND NRFD GPIB I/O PORT
Circuit inside dashed lines is on the driver outputs only.
TYPICAL OF ALL I/O PORTS EXCEPT SRQ, NDAC,
AND NRFD GPIB I/O PORTS
Driver output R(eq) = 30 Ω NOM
Receiver output R(eq) = 110 Ω NOM
Circuit inside dashed lines is on the driver outputs only.
R(eq) = equivalent resistor
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-level driver output current, IOL 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16) inch from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
VIH V‘L ngh \e-el min-101mm 1w Lo-wlevrew Du1p‘10'rrem I~ *9 TEXAS INSTRUMENTS
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING
DW (20 pin) 1125 mW 9.0 mW/°C 720 mW
DW (24 pin) 1350 mW 10.8 mW/°C 864 mW
N (20 pin) 1150 mW 9.2 mW/°C 736 mW
N (22 pin) 1700 mW 13.6 mW/°C 1088 mW
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
High-level input voltage, VIH 2 V
Low-level input voltage, VIL 0.8 V
High level out
p
ut current IOH
Bus ports with 3-state outputs –5.2 mA
High
-
le
v
el
o
u
tp
u
t
c
u
rrent
,
I
OH Terminal ports –800 µA
Low level out
p
ut current IOL
Bus ports 48
Lo
w-
le
v
el
o
u
tp
u
t
c
u
rrent
,
I
OL Terminal ports 16
Operating free-air temperature, TA0 70 °C
Hrgh \e‘ e? output vanage Lam ?e~'et n‘ 'tpul vnflage Termma‘ Voflage at US port Dwer dlsab1ed Power Dn Dn“erdlsab1ed > , 2 5 V to 3 7 V Shun mrcum amp-I current Bus pancapacmance *9 TEXAS INSTRUMENTS
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK Input clamp voltage II = –18 mA –0.8 –1.5 V
Vhys Hysteresis voltage
(VIT+ – VIT–)Bus See Figure 7 0.4 0.65 V
VOH‡
High level out
p
ut voltage
Terminal IOH = –800 µA2.7 3.5
V
V
OH
‡
High
-
le
v
el
o
u
tp
u
t
v
oltage
Bus IOH = –5.2 mA 2.5 3.3
V
VOL
Low level out
p
ut voltage
Terminal IOL = 16 mA 0.3 0.5
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
Bus IOL = 48 mA 0.35 0.5
V
II
Input current at maximum
Terminal
VI=55V
02
100
µA
I
Iinput voltage
Terminal
V
I =
5
.
5
V
0
.
2
100
µ
A
IIH High-level input current Terminal and VI = 2.7 V 0.1 20 µA
IIL Low-level input current control inputs VI = 0.5 V –10 –100 µA
VI/O(b )
Voltage at bus
p
ort
Driver disabled
II(bus) = 0 2.5 3.0 3.7
V
V
I/O(bus)
Voltage
at
b
u
s
port
Dri
v
er
disabled
II(bus) = –12 mA –1.5
V
VI(bus) = –1.5 V to 0.4 V –1.3
VI(bus) = 0.4 V to 2.5 V 0 –3.2
Power on
Driver disabled
VI(b ) =25Vto37V
2.5
mA
II/O(bus) Current into bus port
Po
w
er
on
Dri
v
er
disabled
V
I(bus) =
2
.
5
V
to
3
.
7
V
–3.2
mA
()
VI(bus) = 3.7 V to 5 V 0 2.5
VI(bus) = 5 V to 5.5 V 0.7 2.5
Power off VCC = 0, VI(bus) = 0 V to 2.5 V –40 µA
IOS
Short circuit out
p
ut current
Terminal –15 –35 –75
mA
I
OS
Short
-
circ
u
it
o
u
tp
u
t
c
u
rrent
Bus –25 –50 –125
mA
ICC Supply current No load, TE, DE, and SC low 110 mA
CI/O(b )
Bus
p
ort ca
p
acitance
VCC = 5 V to 0,
16
p
F
C
I/O(bus)
B
u
s
-
port
capacitance
CC
VI/O = 0 to 2 V, f = 1 MHz
16
pF
†All typical values are at VCC = 5 V, TA = 25°C.
‡VOH applies for 3-state outputs only.
tPLZ Termma‘ Bus L ns Bus Terrmnab L ns ‘PZH Bus (ATN ‘PHZ .. ~ » See Flg“re 3 ns ‘PZL 5: . (PZH (PHZ or Termma? See Flg‘we 4 ns ‘PZL sc
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C (unless otherwise noted)
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST
CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time,
low- to high-level output
Terminal
Bus
CL = 30 pF, 14 20
tPHL Propagation delay time,
high- to low-level output
Terminal
Bus
L
See Figure 1 14 20
tPLH Propagation delay time,
low- to high-level output Terminal Bus
(SRQ,NDAC,
NRFD)
CL = 30 pF,
See Figure 1 29 35 ns
tPLH Propagation delay time,
low- to high-level output
Bus
Terminal
CL = 30 pF, 10 20
tPHL Propagation delay time,
high- to low-level output
Bus
Terminal
L
See Figure 2 15 22
tPZH Output enable time to high level
Bus (ATN
60
tPHZ Output disable time from high level TE,DC,
or
Bus
(ATN
,
EOI, REN,
See Figure 3
45
tPZL Output enable time to low level or
SC
,,
IFC, and
DAV)
See
Fig
u
re
3
60
tPLZ Output disable time from low level
SC
DAV) 55
tPZH Output enable time to high level 55
tPHZ Output disable time from high level TE,DC,
or
Terminal
See Figure 4
50
tPZL Output enable time to low level
or
SC
Terminal
See
Fig
u
re
4
45
tPLZ Output disable time from low level
SC
55
I LOAD CIRCUIT Terminal | 5 v I c ' "p” \ See Male 3 \ ‘PLH At—H‘ |PHL+H 7 }7 7 7 Bus 2.2 v \ Output 1 VOLTAGE WAVEFO ompm Under Test “3?: 1.5 v 1 p \ See Note B \ ‘PLH J W Hunk—>4 \ + 7 7 1.5 v Output fl VOLTAGE WAVEFOR *9 TEXAS INSTRUMENTS p057 omca aox $55303 - DALLA
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
LOAD CIRCUIT
480 Ω
200 Ω
(see Note A)
CL = 30 pF
Test Point
5 V
Output
Bus
Input
Terminal
See Note B
VOH
VOH
0 V
3 V
tPHL
2.2 V
1.0 V
1.5 V
tPLH
1.5 V
From (Bus)
Output Under
Test
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
Figure 1. Terminal-to-Bus Load Circuit and Voltage Waveforms
See Note B
1.5 V
tPLH
1.5 V
1.5 V
1.5 V
tPHL
3 V
0 V
VOH
VOL
Bus
Input
Output
From (Terminal)
Output Under
Test
4.3 V
Test Point
CL = 30 pF
(see Note A)
240 Ω
3 kΩ
LOAD CIRCUIT
VOLTAGE WAVEFORMS
Terminal
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
Figure 2. Bus-to-Terminal Load Circuit and Voltage Waveforms
Test LOAD CIRCUIT Conlrol —\/— {.— '"_P“_‘ TCV SeeNoleB Bus ‘ Output 51 Open \ VOLTAG E WAVEFOHMS NOTES A. CL Indudes probe and pg capacnance. a. The mpm pulse ‘5 supphed by a generamr havmg me laHowmg char 1. 56 ns‘ 20 : so 9. *9 TEXAS INSTRUMENTS 9057 omca aox $55303 - DALLAS IE
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
S1 Open
tPHZ
1.5 V
3 V
0 V
S1 Closed 1 V
3.5 V
VOL
Input
Control See Note B
1.5 V
tPZH
S1
VOLTAGE WAVEFORMS
2 V
tPZL
90%
0.5 V
tPLZ
VOH
0 V
Bus
Output
Bus
Output
5 V
Test Point
CL = 15 pF
(see Note A)
200 Ω
480 Ω
LOAD CIRCUIT
From (Bus)
Output Under
Test
Figure 3. Bus Enable and Disable Times Load Circuit and Voltage Waveforms
Tesl Input ' -- \ |P2H41 ‘W 'PHZ 4‘ W Output ‘ 790%” Terminal 51 Open \ . \ Termlnal 51 Closed VOLTAGE WAVEFORM *9 TEXAS INSTRUMENTS p057 OFFICE aox $553133 - DALLAS IE
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
90%
Output
Terminal
S1 Open
S1 Closed
Terminal
tPHZ
VOLTAGE WAVEFORMS
Output
0 V
VOH
tPLZ
0.7 V
tPZL
1.5 V
tPZH
1.5 V See Note B
Control
Input
VOL
4 V
1 V
0 V
3 V
1.5 V
LOAD CIRCUIT
3 kΩ
240 Ω
Test Point
4.3 V
S1
CL = 15 pF
(see Note A)
From (Terminal)
Output Under
Test
NOTES: A. CL includes probe and jig capacitance.
B. The Input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 4. Terminal Enable and Disable Times Load Circuit and Voltage Waveforms
vOH — High-Level Oulpul Vollage — Lu P uI = 0 it > 0 -I‘ s a .I I —5 —10 —15 —20 —25 —30 —35 —40 no" — High-Level ompuI Current — mA 'OL ‘ L°W Figure 5 7TA = 25“C > I 0 Is. 3 B > '3 5 'VIT— A O I r *9 TEXAS INSTRUMENTS p057 OFFICE aox $55303 - DALLAS IEXAS 752s5
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
VOH – High-Level Output Voltage – V
TERMINAL I/O PORTS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
3
2.5
2
1.5
1
0.5
–35–30–25–20–15–10–5
0–40
4
0
T
A = 25°C
VCC = 5 V
IOH – High-Level Output Current – mA
VOH
Figure 5
IOL – Low-Level Output Current – mA
VOL – Low-Level Output Voltage – V
TERMINAL I/O PORTS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TA = 25°C
VCC = 5 V
0.5
0.4
0.3
0.2
0.1
5040302010
060
0.6
0
VOL
Figure 6
2
VO – Output Voltage – V
TERMINAL I/O PORTS
OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
VIT–
TA = 25°C
No Load
VCC = 5 V
3.5
3
2.5
2
1.5
1
0.5
1.81.61.41.210.80.60.40.2
0
4
VI – Bus Input Voltage – V
0
VO
VIT+
Figure 7
v0" 4 High—Level Oulpul Valiage 4 v E > 4? / s a .a I 0 —1o —20 —40 —3o —5o —60 IOH — High-Level Oulpul Cum-ml — mA IOL — Low Figure 5 ‘K E 1 E 2 ‘5 U \ 1 1.2 I3 1.4 1.5 1.6 L7 v. — Input Voltage — v Figure 10 *9 TEXAS INSTRUMENTS 9057 omca aox $55303 - DALLAS IEXAS 752s5
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
IOH – High-Level Output Current – mA
– High-Level Output Voltage – V
GPIB I/O PORTS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
TA = 25°C
VCC = 5 V
3
2
1
–50–30–40–20–10
0–60
0
0
V
OH
Figure 8
IOL – Low-Level Output Current – mA
– Low-Level Output Voltage – V
GPIB I/O PORTS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TA = 25°C
VCC = 5 V
0.5
0.4
0.3
0.2
0.1
908070605040302010
0100
0.6
0
VOL
Figure 9
Figure 10
VI – Input Voltage – V
VO – Output Voltage – V
GPIB I/O PORTS
OUTPUT VOLTAGE
vs
THERMAL INPUT VOLTAGE
TA = 25°C
No Load
VCC = 5 V
3
2
1
1.61.51.41.31.21.11
0
4
0.9 1.7
VO
– Current – mA
GPIB I/O PORTS
CURRENT
vs
VOLTAGE
2
1
0
–1
–2
–3
–6
543210–1
–7 6
VI/O – Voltage – V
–2
T
A = 25°C
VCC = 5 V
The Unshaded
Area Conforms to
Paragraph 3.5.3 of
IEEE Standard 488-1978
II/O
–5
–4
Figure 11
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN75161BDW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75161B Samples
SN75161BDWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75161B Samples
SN75161BDWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75161B Samples
SN75161BDWRE4 ACTIVE SOIC DW 20 2000 TBD Call TI Call TI 0 to 70 Samples
SN75161BDWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75161B Samples
SN75161BN ACTIVE PDIP N 20 20 RoHS &
Non-Green NIPDAU N / A for Pkg Type 0 to 70 SN75161BN Samples
SN75161BNE4 ACTIVE PDIP N 20 20 RoHS &
Non-Green NIPDAU N / A for Pkg Type 0 to 70 SN75161BN Samples
SN75162BDW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75162B Samples
SN75162BDWE4 ACTIVE SOIC DW 24 25 TBD Call TI Call TI 0 to 70 Samples
SN75162BDWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75162B Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension deSIgned Io eecommodaIe me componenI Iengm KO Dlmenslun desIgned to accommodate me componem Ihlckness 7 w OvereII wmm OHhe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN75161BDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN75162BDWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75161BDWR SOIC DW 20 2000 367.0 367.0 45.0
SN75162BDWR SOIC DW 24 2000 350.0 350.0 43.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width $ — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN75161BDW DW SOIC 20 25 507 12.83 5080 6.6
SN75161BDW DW SOIC 20 25 506.98 12.7 4826 6.6
SN75161BDWG4 DW SOIC 20 25 506.98 12.7 4826 6.6
SN75161BDWG4 DW SOIC 20 25 507 12.83 5080 6.6
SN75161BN N PDIP 20 20 506 13.97 11230 4.32
SN75161BNE4 N PDIP 20 20 506 13.97 11230 4.32
SN75162BDW DW SOIC 24 25 506.98 12.7 4826 6.6
SN75162BDWE4 DW SOIC 24 25 506.98 12.7 4826 6.6
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 3
MECHANICAL DATA DW «#:5075220 JLASW‘ SMALL 0U J\L HHHHHHHHHHHH’fi N A AH Hnec' d'vnensm m ‘mmes (mammaers) D'ws'nmng md tu‘ermc'mq per ASME w 5M 1994, B TH: drawmq ‘5 Sn :0 change wan: nohce. a Body dimensmns ca nut inc‘ude mom flcsh ur mum" rut m exceed 0035 (055) D FONS WMHH JEDEC MSiOH vermin" ADV NOTES: {if TEXAS INSTRUMENTS wwvmi .com
MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
DW0020A I
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
18X 1.27
20X 0.51
0.31
2X
11.43
TYP
0.33
0.10
0 - 8
0.3
0.1
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
13.0
12.6
B7.6
7.4
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
120
0.25 C A B
11
10
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.200
DW0020A
www.ti.com
EXAMPLE BOARD LAYOUT
(9.3)
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
20X (2)
20X (0.6)
18X (1.27)
(R )
TYP
0.05
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
10 11
20
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
DW0020A $$$$$fififiifi%
www.ti.com
EXAMPLE STENCIL DESIGN
(9.3)
18X (1.27)
20X (0.6)
20X (2)
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
10 11
20
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
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