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Datenblatt für LP886x-Q1 von Texas Instruments
V'.‘
I TEXAS
INSTRUMENTS
vw
ma
1
HM w
LP8867-Q1
FB
PWM
OUT1
OUT2
OUT3
OUT4
L1 D1 Up to 45 V
VIN
4.5...40 V
COUT
CIN BOOST
SD
VSENSE_N
RISET
Up to 120 mA/string
SW
LDO
FSET
VDDIO/EN
SYNC
PGND GND PAD
VIN
TSENSE
ISETFAULT
EN
BRIGHTNESS
RFSET
R1R2
TSET
CLDO
CFB
Q1
FAULT
RISENSE
RGS
CIN
R8
VDDIO
VLDO
R7
R6
R5
R4
R3
RTº
NTC
VLDO
Output Current (mA)
System Efficiency (%)
80 160 240 320 400 480
68
72
76
80
84
88
92
96
100
D000
VIN = 16V
VIN = 12V
VIN = 8V
VIN = 6V
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Folder
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP8867-Q1
,
LP8869-Q1
SNVSB83B –JUNE 2019–REVISED JANUARY 2020
LP8867-Q1, LP8869-Q1 Low EMI Automotive LED Driver with 4-, 3- Channels
1
1 Features
1• AEC-Q100 Qualified for automotive applications:
– Device temperature grade 1:
–40°C to +125°C, TA
•Functional safety capable
– Documentation available to aid functional
safety system design
• 3-, 4-Channel 120-mA current sinks
– High dimming ratio of 10 000:1 at 100 Hz
– Current matching 1% (typical)
– LED String current up to 120 mA per channel
– Outputs can be combined externally for higher
current per string
• Integrated boost and SEPIC converter for LED
string power
– Input voltage operating range 4.5 V to 40 V
– Output voltage up to 45 V
– Integrated 3.3-A Switch FET
– Switching frequency 300 kHz to 2.2 MHz
– Switching synchronization input
– Spread spectrum for lower EMI
• Fault detection and protection
– Fault output
– Input voltage OVP, UVLO and OCP
– Boost block SW OVP and output OVP
– LED open and short fault detection
– Power-Line FET control for battery bus
protection
– Automatic LED current reduction with external
temperature sensor
– Thermal shutdown
2 Applications
• Backlight for:
– Automotive infotainment
– Automotive instrument clusters
– Smart mirrors
– Heads-up displays (HUD)
3 Description
The LP8867-Q1, LP8869-Q1 is an automotive highly-
integrated, low-EMI, easy-to-use LED driver with DC-
DC converter. The DC-DC converter supports both
boost and SEPIC mode operation. The device has
four or three high-precision current sinks that can be
combined for higher current capability.
The DC-DC converter has adaptive output voltage
control based on the LED forward voltages. This
feature minimizes the power consumption by
adjusting the voltage to the lowest sufficient level in
all conditions. For EMI reduction DC-DC supports
spread spectrum for switching frequency and an
external synchronization with dedicated pin. A wide-
range adjustable frequency allows the LP886x-Q1 to
avoid disturbance for sensitive frequency band.
The input voltage range for the LP886x-Q1 is from
4.5 V to 40 V to support automotive start-stop and
load dump condition. The LP886x-Q1 integrates
extensive fault detection features.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LP8867-Q1 HTSSOP (20) 6.50 mm × 4.40 mm
LP8869-Q1
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic LED Backlight Efficiency
l TEXAS
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LP8867-Q1
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SNVSB83B –JUNE 2019–REVISED JANUARY 2020
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions......................... 3
7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 6
7.6 Internal LDO Electrical Characteristics ..................... 6
7.7 Protection Electrical Characteristics ......................... 6
7.8 Current Sinks Electrical Characteristics.................... 7
7.9 PWM Brightness Control Electrical Characteristics .. 7
7.10 Boost and SEPIC Converter Characteristics .......... 7
7.11 Logic Interface Characteristics................................ 7
7.12 Typical Characteristics............................................ 9
8 Detailed Description............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram....................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 25
9 Application and Implementation ........................ 27
9.1 Application Information............................................ 27
9.2 Typical Applications ................................................ 27
10 Power Supply Recommendations ..................... 32
11 Layout................................................................... 32
11.1 Layout Guidelines ................................................. 32
11.2 Layout Example .................................................... 33
12 Device and Documentation Support ................. 34
12.1 Device Support...................................................... 34
12.2 Documentation Support ........................................ 34
12.3 Receiving Notification of Documentation Updates 34
12.4 Community Resources.......................................... 34
12.5 Trademarks........................................................... 34
12.6 Electrostatic Discharge Caution............................ 34
12.7 Glossary................................................................ 34
13 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
Changes from Revision A (July 2019) to Revision B Page
• Added the functional safety link to the Features section........................................................................................................ 1
Changes from Original (June 2019) to Revision A Page
• Changed from Advance Information to Production Data ....................................................................................................... 1
‘5‘ TEXAS
INSTRUMENTS
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““““““““““““““““““ L
3333333333
::::::::::
““““““““““““““““““ L
::::::::::
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
EP*
*EXP OSED PAD
OUT2
GND
OUT3
GND
TSENSE
LDO
VDDIO/EN
FSET
VIN VSENSE_N
SD
FB
PGND
SW
OUT1
TSET
PWM
FAULT
ISET
SYNC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
EP*
*EXPOSED PAD
OUT2
GND
OUT3
OUT4
TSENSE
LDO
VDDIO/EN
FSET
VIN VSENSE_N
SD
FB
PGND
SW
OUT1
TSET
PWM
FAULT
ISET
SYNC
3
LP8867-Q1
,
LP8869-Q1
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SNVSB83B –JUNE 2019–REVISED JANUARY 2020
Product Folder Links: LP8867-Q1 LP8869-Q1
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5 Device Comparison Table
LP8869-Q1 LP8869C-Q1 LP8867-Q1 LP8867C-Q1
Number of LED channels 3 3 4 4
LED current / channel 120 mA 120 mA 120 mA 120 mA
Power Line FET Control and
Automatic Current De-rating Support Yes No Yes No
6 Pin Configuration and Functions
LP8867-Q1 PWP Package
20-Pin HTSSOP With Exposed Thermal Pad
Top View
LP8869-Q1 PWP Package
20-Pin HTSSOP With Exposed Thermal Pad
Top View
l TEXAS
INSTRUMENTS
4
LP8867-Q1
,
LP8869-Q1
SNVSB83B –JUNE 2019–REVISED JANUARY 2020
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Product Folder Links: LP8867-Q1 LP8869-Q1
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(1) A: Analog pin, G: Ground pin, P: Power pin, I: Input pin, I/O: Input/Output pin, O: Output pin, OD: Open Drain pin
Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 VIN A Input power pin; input voltage OVP detection pin; input current sense positive input pin.
2 LDO A Output of internal LDO; connect a 1-μF decoupling capacitor between this pin and noise-free ground.
Put the capacitor as close to the chip as possible.
3 FSET A DC-DC (boost or SEPIC) switching frequency setting resistor; for normal operation, resistor value
from 24 kΩto 219 kΩmust be connected between this pin and ground.
4 VDDIO/EN I Enable input for the device as well as supply input (VDDIO) for digital pins.
5 FAULT OD Fault signal output. If unused, the pin may be left floating.
6 SYNC I Input for synchronizing DC-DC converter. If synchronization is not used, connect this pin to ground to
disable spread spectrum or to VDDIO/EN to enable spread spectrum.
7 PWM I PWM dimming input.
8 TSENSE A Input for NTC resistor divider. Refer to LED Current Dimming With External Temperature Sensor for
proper connection. If unused, the pin must be left floating.
9 TSET A Input for NTC resistor divider. Refer to LED Current Dimming With External Temperature Sensor for
proper connection. If unused, the pin must be connected to GND.
10 ISET A LED current setting resistor; for normal operation, resistor value from 20 kΩto 129 kΩmust be
connected between this pin and ground.
11 GND G Ground.
12 OUT4/GND A Current sink output for LP8867-Q1
This pin must be connected to ground if not used.
GND pin for LP8869-Q1
13 OUT3 A Current sink output.
This pin must be connected to ground if not used.
14 OUT2 A Current sink output.
This pin must be connected to ground if not used.
15 OUT1 A Current sink output.
This pin must be connected to ground if not used.
16 FB A DC-DC (boost or SEPIC) feedback input; for normal operation this pin must be connected to the
middle of a resistor divider between VOUT and ground using feedback resistor values greater than
5kΩ.
17 PGND G DC-DC (boost or SEPIC) power ground.
18 SW A DC-DC (boost or SEPIC) switch pin.
19 SD A Power-line FET control. Open Drain (current sink type) Output. If unused, the pin may be left floating.
20 VSENSE_N A Input current sense negative input. Connect to VIN pin when input current sense resistor is not used.
l TEXAS
INSTRUMENTS
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LP8867-Q1
,
LP8869-Q1
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SNVSB83B –JUNE 2019–REVISED JANUARY 2020
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pins.
(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 165°C (typical) and
disengages at TJ= 145°C (typical).
(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
150°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Voltage on pins
VIN, VSENSE_N, SD, SW, FB –0.3 50
VOUT1, OUT2, OUT3, OUT4 –0.3 45
LDO, SYNC, FSET, ISET, TSENSE, TSET, PWM, VDDIO/EN, FAULT –0.3 5.5
Continuous power dissipation(3) Internally Limited
Ambient temperature, TA(4) –40 125 °C
Junction temperature, TJ(4) –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human-body model (HBM), per AEC Q100-002, all pins (1) ±2000
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins (1, 10, 11 and 20) ±750
All pins ±500
(1) All voltages are with respect to the potential at the GND pins.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
Voltage on
pins
VIN 4.5 12 45
V
SW, VSENSE_N, SD 0 45
OUT1, OUT2, OUT3, OUT4 0 40
FB, FSET, LDO, ISET, TSENSE, TSET, VDDIO/EN, FAULT 0 5.25
SYNC, PWM 0 VDDIO/EN
l TEXAS
INSTRUMENTS
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LP8867-Q1
,
LP8869-Q1
SNVSB83B –JUNE 2019–REVISED JANUARY 2020
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Product Folder Links: LP8867-Q1 LP8869-Q1
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(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
7.4 Thermal Information
THERMAL METRIC(1)
LP886x-Q1
UNITPWP (HTSSOP)
20 PINS
RθJA Junction-to-ambient thermal resistance(2) 44.2 °C/W
RθJCtop Junction-to-case (top) thermal resistance 26.5 °C/W
RθJB Junction-to-board thermal resistance 22.4 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 22.2 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 2.5 °C/W
7.5 Electrical Characteristics
Limits apply over the full operation temperature range −40°C ≤TA≤+125°C , unless otherwise speicified, VIN = 12V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IQ
Standby supply current Device disabled, VVDDIO/EN = 0 V, VIN = 12 V 4.5 20 μA
Active supply current VIN = 12 V, VOUT = 26 V, output current 80
mA/channel, converter ƒSW = 300 kHz 5 12 mA
7.6 Internal LDO Electrical Characteristics
Limits apply over the full operation temperature range −40°C ≤TA≤+125°C , unless otherwise speicified, VIN = 12V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VLDO Output voltage VIN = 12 V 4.15 4.3 4.55 V
VDR Dropout voltage 120 300 430 mV
ISHORT Short circuit current 50 mA
IEXT Current for external load 5 mA
7.7 Protection Electrical Characteristics
Limits apply over the full operation temperature range −40°C ≤TA≤+125°C , unless otherwise speicified, VIN = 12V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOVP VIN OVP threshold voltage 41 42 44 V
VOCP VIN OCP threshold voltage, VIN -
VSENSEN 135 160 186 mV
VUVLO VIN UVLO Falling threshold 3.7 3.85 4 V
VUVLO_HYST VIN UVLO Rising threshold - VIN UVLO
Fallling threshold 150 mV
ISENSE_N VSENSE_N pin leakage VSENSE_N = 45V, EN = L 0.1 3 µA
ISD_LEAK SD pin leakage VSD = 45V, EN = L 0.1 3 µA
ISD SD pull down current 185 230 283 µA
VFB_OVP FB threshold for BST_OVP fault 2.3 V
TTSD Thermal shutdown Rising threshold 150 165 175 ℃
TTSD_HYS Thermal shutdown Rising threshold -
Thermal shutdown Falling threshold 20 ℃
l TEXAS
INSTRUMENTS
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LP8867-Q1
,
LP8869-Q1
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SNVSB83B –JUNE 2019–REVISED JANUARY 2020
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(1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.
Matching is the maximum difference from the average. For the constant current sinks on the part (OUTx), the following are determined:
the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Matching
number is calculated: (MAX-MIN)/AVG. The typical specification provided is the most likely norm of the matching figure for all parts. LED
current sinks were characterized with 1-V headroom voltage. Note that some manufacturers have different definitions in use.
7.8 Current Sinks Electrical Characteristics
Limits apply over the full operation temperature range −40°C ≤TA≤+125°C , unless otherwise speicified, VIN = 12V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ILEAKAGE Leakage current Outputs OUT1 to OUT4 , VOUTx = 45 V, EN = L 0.1 5 µA
IMAX Maximum current OUT1, OUT2, OUT3, OUT4, RISET = 20 kΩ120 mA
IOUT Output current accuracy IOUT = 100 mA −5% 5%
IMATCH Output current matching(1) IOUT = 100 mA, PWM duty =100% 1% 5%
VLOW_COMP Low comparator threshold 0.9 V
VMID_COMP Mid comparator threshold 1.9 V
VHIGH_COMP High comparator threshold 5.6 6 7 V
(1) This specification is not ensured by ATE.
7.9 PWM Brightness Control Electrical Characteristics
Limits apply over the full operation temperature range −40°C ≤TA≤+125°C , unless otherwise speicified, VIN = 12V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ƒPWM PWM input frequency 100 20 000 Hz
tON/OFF Minimum on/off time(1) 0.5 µs
(1) This specification is not ensured by ATE.
7.10 Boost and SEPIC Converter Characteristics
Limits apply over the full operation temperature range −40°C ≤TA≤+125°C , unless otherwise speicified, VIN = 12V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage 4.5 40 V
VOUT Output voltage 6 45
ƒSW_MIN Minimum switching frequency Defined by RFSET resistor 300 kHz
ƒSW_MAX Maximum switching frequency Defined by RFSET resistor 2 200 kHz
tOFF Minimum switch OFF time(1) ƒSW ≥1.15 MHz 55 ns
ISW_MAX SW current limit first triggerred 3.3 3.7 4.1 A
tSW_MAX SW current limit first triggerred period 1.6 s
ISW_LIM SW current limit 3 3.35 3.7 A
RDSON FET RDSON 240 400 mΩ
fSYNC External SYNC frequency 300 2 200 kHz
tSYNC_ON External SYNC on time(1) 150 ns
tSYNC_OFF External SYNC off time(1) 150 ns
7.11 Logic Interface Characteristics
Limits apply over the full operation temperature range −40°C ≤TA≤+125°C , unless otherwise speicified, VIN = 12V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC INPUT VDDIO/EN
VIL Input low level 0.4 V
VIH Input high level 1.65
IEN
Input DC current −1 5 30 µA
Input transient current during VDDIO/EN
powering up 1.2 mA
LOGIC INPUT SYNC, PWM
l TEXAS
INSTRUMENTS
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LP8867-Q1
,
LP8869-Q1
SNVSB83B –JUNE 2019–REVISED JANUARY 2020
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Product Folder Links: LP8867-Q1 LP8869-Q1
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Logic Interface Characteristics (continued)
Limits apply over the full operation temperature range −40°C ≤TA≤+125°C , unless otherwise speicified, VIN = 12V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIL Input low level 0.2 ×
VDDIO/E
NV
VIH Input high level 0.8 ×
VDDIO/E
N
IIInput current −1 1 μA
LOGIC OUTPUT FAULT
VOL Output low level Pullup current 3 mA 0.3 0.5 V
ILEAKAGE Output leakage current V = 5.5 V 1 μA
l TEXAS
INSTRUMENTS
Mu
Mu
AKU
mu
mu
Output Current (mA)
Boost Efficiency (%)
80 160 240 320 400 480
68
72
76
80
84
88
92
96
100
D001
VIN = 16V
VIN = 12V
VIN = 8V
VIN = 6V
Output Current (mA)
Boost Efficiency (%)
80 160 240 320 400 480
68
72
76
80
84
88
92
96
100
D002
VIN = 16V
VIN = 12V
VIN = 8V
VIN = 6V
Input Voltage (V)
Boost Output Current (mA)
4.5 5.5 6.5 7.5 8.5 9.5
80
160
240
320
400
480
D007
VBoost = 18V
VBoost = 26V
VBoost = 37V
Output Current (mA)
Output current mismatch (%)
30 40 50 60 70 80 90 100 110 120
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
D008
Input Voltage (V)
Boost Output Current (mA)
4.5 5.5 6.5 7.5 8.5 9
80
160
240
320
400
480
D005
VBoost = 18V
VBoost = 26V
VBoost = 37V
Input Voltage (V)
Boost Output Current (mA)
4.5 5.5 6.5 7.5 8.5 9.5 10
80
160
240
320
400
480
D006
VBoost = 18V
VBoost = 26V
VBoost = 37V
9
LP8867-Q1
,
LP8869-Q1
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7.12 Typical Characteristics
Unless otherwise specified: D = NRVB460MFS, TA= 25°C
ƒSW = 400 kHz L = 33 μH DC Load (PWM = 100%)
CIN and COUT = 33 µF (electrolytic) + 2 × 10 µF (ceramic)
Figure 1. Maximum Boost Current
ƒSW = 1.1 MHz L = 15 μH DC Load (PWM = 100%)
CIN and COUT = 33 µF (electrolytic) + 10 µF (ceramic)
Figure 2. Maximum Boost Current
ƒSW = 2.2 MHz L = 10 μH DC Load (PWM = 100%)
CIN and COUT = 3× 10 µF (ceramic)
Figure 3. Maximum Boost Current
Figure 4. LED Current Sink Matching
ƒSW = 400 kHz L = 22 μH DC Load (PWM = 100%)
CIN and COUT = 33 µF (electrolytic)
+ 2 × 10 µF (ceramic) VBOOST = 18 V
Figure 5. Boost Efficiency
ƒSW = 400 kHz L = 22 μH DC Load (PWM = 100%)
CIN and COUT = 33 µF (electrolytic)
+ 2 × 10 µF (ceramic) VBOOST = 30 V
Figure 6. Boost Efficiency
l TEXAS
INSTRUMENTS
mu
vuu
Output Current (mA)
Boost Efficiency (%)
80 160 240 320 400 480
68
72
76
80
84
88
92
96
100
D003
VIN = 16V
VIN = 12V
VIN = 8V
VIN = 6V
Output Current (mA)
Boost Efficiency (%)
80 160 240 320 400 480
68
72
76
80
84
88
92
96
100
D004
VIN = 16V
VIN = 12V
VIN = 8V
VIN = 6V
10
LP8867-Q1
,
LP8869-Q1
SNVSB83B –JUNE 2019–REVISED JANUARY 2020
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Typical Characteristics (continued)
Unless otherwise specified: D = NRVB460MFS, TA= 25°C
ƒSW = 2.2 MHz L = 4.7 μH DC Load (PWM = 100%)
CIN and COUT = 3 × 10 µF (ceramic) VBOOST = 18 V
Figure 7. Boost Efficiency
ƒSW = 2.2 MHz L = 4.7 μH DC Load (PWM = 100%)
CIN and COUT = 3 × 10 µF (ceramic) VBOOST = 30 V
Figure 8. Boost Efficiency
l TEXAS
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LP8867-Q1
,
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8 Detailed Description
8.1 Overview
The LP8867-Q1, LP8869-Q1 is a highly integrated LED driver for automotive infotainment , cluster and HUD
medium-size LCD backlight applications. It includes a DC-DC with an integrated FET, supporting both boost and
SEPIC modes, an internal LDO enabling direct connection to battery without need for a pre-regulated supply and
3 or 4 LED current sinks. The VDDIO/EN pin provides the supply voltage for digital IOs (PWM and SYNC inputs)
and at the same time enables the device.
The switching frequency on the DC-DC converter is set by a resistor connected to the FSET pin. The maximum
voltage of the DC-DC is set by a resistive divider connected to the FB pin. For the best efficiency, the output
voltage is adapted automatically to the minimum necessary level needed to drive the LED strings. This is done
by monitoring LEDs' cathode voltage in real time. For EMI reduction, two optional features are available:
• Spread spectrum, which reduces EMI noise around the switching frequency and its harmonic frequencies
• DC-DC can be synchronized to an external frequency connected to SYNC pin
The 3 or 4 constant current outputs OUT1, OUT2, OUT3, and OUT4 provide LED current up to 120 mA. Value
for the current per OUT pin is set with a resistor connected to ISET pin. Current sinks that are not used must be
connected to ground. Grounded current sink is disabled and excluded from boost adaptive voltage detection
loop.
Brightness is controlled with the PWM input. Frequency range for the input PWM is from 100 Hz to 20 kHz. LED
output PWM behavior follows the input PWM so the output frequency is equal to the input frequency.
LP886x-Q1 has extensive fault detection features:
• LED open and short detection
• VIN input overvoltage protection
• VIN input undervoltage protection
• VIN input overcurrent protection
• VBoost output overvoltage protection
• SW overvoltage protection
• Thermal shutdown in case of chip overheated
Fault condition is indicated through the FAULT output pin.
l TEXAS
INSTRUMENTS
COUT
D
POWER-LINE FET CONTROL
RISENSE
SDVSENSE_NVIN
LDO
CLDO SW
FB
BOOST
CONTROLLER
VIN
SYNC
Q
PGND
OUT1
OUT2
OUT3
OUT4
GND
4 x LED
CURRENT
SINK
ANALOG BLOCKS
(CLOCK GENERATOR, VREF,
TSD etc.)
DIGITAL BLOCKS
(FSM, ADAPTIVE VOLTAGE
CONTROL, SAFETY LOGIC
etc.)
VDDIO/EN
FAULT
RISET
NTC
tº
EXPOSED PAD
LDO
ISET
CURRENT
SETTING
FSET
TSET
TSENSE
RFSET
PWM
VDDIO
RGS
CIN CIN BOOST
L
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8.2 Functional Block Diagram
RC
filter
BOOST
OSCILLATOR
SYNC
FB
OFF/BLANK
TIME
PULSE
GENERATOR
CURRENT
RAMP
GENERATOR
BLANK
TIME
SW
OVP
S
OCP
LIGHT
LOAD
R
RRR
-
+
FSET FSET
CTRL
GM
GM
RFSET
ADAPTIVE
VOLTAGE
CONTROL
CIN
D
COUT
VIN
CURRENT
SENSE
PGND
VOUT
R1
R2
13
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8.3 Feature Description
8.3.1 Integrated DC-DC Converter
The LP886x-Q1 DC-DC converter generates supply voltage for the LEDs and can operate in boost mode or in
SEPIC mode. The output voltage, switching frequency are all configured by external resistors.
For detailed boost application, refer to Typical Application for 4 LED Strings
For detailed SEPIC application, refer to SEPIC Mode Application
8.3.1.1 DC-DC Converter Parameter Configuration
The LP886x-Q1 converter is a current-peak mode DC-DC converter, where the switch FET's current and the
output voltage feedback are measured and controlled. The block diagram is shown in Figure 9.
Figure 9. DC-DC converter in Boost Application
8.3.1.1.1 Switching Frequency
Switching frequency is adjustable between 300 kHz and 2.2 MHz with RFSET resistor as Equation 1:
ƒSW = 67600 / (RFSET + 6.4)
where
• ƒSW is switching frequency, kHz
• RFSET is frequency setting resistor, kΩ(1)
For example, if RFSET is set to 163 kΩ, fSW will be 400 kHz.
In most cases, lower switching frequency has higher system efficiency and lower internal temperature increase.
8.3.1.1.2 Spread Spectrum and External SYNC
LP886x-Q1 has an optional spread spectrum feature (±3% from central frequency, 1-kHz modulation frequency)
which reduces EMI noise at the switching frequency and its harmonic frequencies. If SYNC pin level is low,
spread spectrum function is disabled. If SYNC pin level is high, spread spectrum function is enabled.
LP886x-Q1 DC-DC converter can be driven by an external SYNC signal between 300 kHz and 2.2 MHz. When
external synchronization is used, spread spectrum is not available. If the external synchronization input
disappears, DC-DC continues operation at the frequency defined by RFSET resistor and spread spectrum function
will be enabled/disabled depending on the final SYNC pin level.
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Feature Description (continued)
External SYNC frequency must be 1.2 to 1.5 times higher than the frequency defined by RFSET resistor. In
external SYNC configuration, minimum frequency setting with RFSET could go as low as 250 kHz to support 300-
kHz switching with external clock.
Table 1. DC-DC Synchronization Mode
SYNC PIN INPUT MODE
Low Spread spectrum disabled
High Spread spectrum enabled
300 to 2200 kHz frequency Spread spectrum disabled, external synchronization mode
(1) Parameters are for reference only
(2) Due to current sensing comparator delay the actual minimum off time is 6 ns (typical) longer than in the table.
8.3.1.1.3 Recommended Component Value and Internal Parameters
The LP886x-Q1 DC-DC converter has an internal compensation network to ensure the stability. There's no
external component needed for compensation. It's strongly recommended that the inductance value and the
boost input and output capacitors value follow the requirement of Table 2. Also, the DC-DC internal parameters
are chosen automatically according to the selected switching frequency (see Table 2) to ensure stability.
Table 2. Boost Converter Parameters(1)
RANGE FREQUENCY (kHz) TYPICAL
INDUCTANCE (µH) TYPICAL BOOST INPUT
AND OUTPUT CAPACITORS (µF) MINIMUM SWITCH
OFF TIME (ns)(2) BLANK
TIME (ns)
1 300 to 480 22 or 33 2 ×10 (cer.) + 33 (electr.) 150 95
2 480 to 1150 15 10 (cer.) + 33 (electr.) 60 95
3 1150 to 1650 10 3 × 10 (cer.) 40 95
4 1650 to 2200 4.7 or 10 3 × 10 (cer.) 40 70
8.3.1.1.4 DC-DC Converter Switching Current Limit
The LP886x-Q1 DC-DC converter has an internal SW FET inside chip's SW pin. The internal FET current is
limited to 3.35 A (typical). The DC-DC converter will sense the internal FET current, and turn off the internal FET
cycle-by-cycle when the internal FET current reaches the limit.
To support start transient condition, the current limit could be automatically increased to 3.7 A for a short period
of 1.6 seconds when a 3.35-A limit is reached.
NOTE
Application condition where the 3.35-A limit is exceeded continuously is not allowed. In
this case the current limit would be 3.35 A for 1.6 seconds followed by 3.7-A limit for 1.6
seconds, and this 3.2-second period repeats.
8.3.1.1.5 DC-DC Converter Light Load Mode
LP886x-Q1 DC-DC converter will enter into light load mode in below condition:
• VIN voltage is very close to VOUT
• Loading current is very low
• PWM pulse width is very short
When DC-DC converter enters into light load mode, DC-DC converter stops switching occasionally to make sure
boost output voltage won't rise up too much. It could also be called as PFM mode, since the DC-DC converter
switching frequency will change in this mode.
‘.
INSTRUMENTS
EG
BG
BOOST BG
V
V K 0.0387 R1 V
R2
·
§
u u
¨ ¸
©¹
OUT1
OUT2
OUT3
OUT4
No actions Boost
decreases voltage
Boost
Increases voltage
No output is close to
VLOW_COMP threshold
One output is lower than
VLOW_COMP threshold
Normal
Conditions
Dynamic
Conditions
OUT 1-4
VOLTAGE
VLOW_COMP
The lowest channel
voltage touches
VLOW_COMP threshold
OUT1
OUT2
OUT3
OUT4
OUT1
OUT2
OUT3
OUT4
15
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8.3.1.2 Adaptive Voltage Control
The LP886x-Q1 DC/DC converter generates the supply voltage for the LEDs. During normal operation, boost
output voltage is adjusted automatically based on the LED cathode (OUTx pin) voltages. This is called adaptive
boost control. Only the active LED outputs are monitored to control the adaptive boost voltage. Any LED strings
with open or short faults are removed from the adaptive voltage control loop. The OUTx pin voltages are
periodically monitored by the control loop. The boost voltage is raised if any of the OUTx voltage falls below the
VLOW_COMP threshold. The boost voltage is also lowered if all OUTx voltages are higher than VLOW_COMP
threshold. The boost voltage keeps unchanged when one of OUTx voltage touches the VLOW_COMP threshold. In
normal operation, the lowest voltage among the OUTx pins is around VLOW_COMP, and boost voltage stays
constant. VLOW_COMP level is the minimum voltage which could guarantee proper LED current sink operation. See
Figure 10 for how the boost voltage automatically scales based on the OUT1-4 pin voltage.
Figure 10. Adaptive Boost Voltage Control Loop Function
8.3.1.2.1 Using Two-Divider
VBOOST_MAX voltage should be chosen based on the maximum voltage required for LED strings. Recommended
maximum voltage is about 3 to 5-V higher than maximum LED string voltage. DC-DC output voltage is adjusted
automatically based on LED cathode voltage. The maximum, minimum and initial boost voltages can be
calculated with Equation 2:
where
• VBG = 1.2 V
• R2 recommended value is 10 kΩto 200 kΩ
• R1/R2 recommended value is 5 to 10
• K = 1 for maximum adaptive boost voltage (typical)
• K = 0 for minimum adaptive boost voltage (typical)
• K = 0.88 for initial boost voltage (typical) (2)
For example, if R1 is set to 750 kΩand R2 is set to 130 kΩ, VBOOST will be in the range of 8.1 V to 37.1 V.
l TEXAS
INSTRUMENTS
r7
LJ
u
§ · § ·
u u
¨ ¸ ¨ ¸
© ¹ © ¹
BOOST BG
R1 R3 R1
V = +R1+R3 K 0.0387 + +1 V
R2 R2
+
±
VBG
R2
GM
R1
COUT
FB
VOUT
+
±
VOVP
BSTOVP
Curren t DAC
(38.7uA Full-Scale)
16
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Figure 11. FB External Two-Divider Resistors
8.3.1.2.2 Using T-Divider
Alternatively, a T-divider can be used if resistance less than 100 kΩis required for the external resistive divider.
Then the maximum, minimum and initial boost voltages can be calculated with
where
• VBG = 1.2 V
• R2 recommended value is 10 kΩto 200 kΩ
• R1/R2 recommended value is 5 to 10
• K = 1 for maximum adaptive boost voltage (typical)
• K = 0 for minimum adaptive boost voltage (typical)
• K = 0.88 for initial boost voltage (typical) (3)
For example, if R1 is set to 100 kΩ, R2 is set to 10 kΩand R3 is set to 60 kΩ, VBOOST will be in the range of 13.2
V to 42.6 V.
E
37;»
+
±
VBG
R2
GM
R1
COUT
FB
VOUT
+
±
VOVP
BSTOV P
Current DAC
(38.7uA Full-Scale)
Optional
R3
CFB
S
FB
z
1
C =
2 f
R1
+
±
VBG
R2
GM
R1
COUT
FB
VOUT
+
±
VOVP
BSTOV P
Current DAC
(38.7uA Full-Scale)
R3
17
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Figure 12. FB External T-divider Resistors
8.3.1.2.3 Feedback Capacitor
When operating with no electrolytic capacitor in boost output, which is a typical case when boost frequency is in
the 1.15-MHz to 2.2-MHz range, a feedback capacitor needs to be put in parallel with R1 to ensure the loop
stability. The value of the capacitor is recommended to be:
where
• fz= 20 kHz (4)
For example, if R1is set to 750 kΩ, CFB needs to be around 11 pF.
Figure 13. FB External Resistors With Capacitor When Operating With No Electrolytic Capacitor In Boost
Output
l TEXAS
INSTRUMENTS
iii
“H }—4
‘U—H
L1
VIN
CIN BOOST
SD
VSENSE_N
SW
VIN
Q1RISENSE
RGS
CIN
BG
LED
ISET
V
I = 2000
R
u
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8.3.2 Internal LDO
The internal LDO regulator converts the input voltage at VIN to a 4.3-V output voltage for internal use. Connect a
minimum of 1-µF ceramic capacitor from LDO pin to ground, as close to the LDO pin as possible.
8.3.3 LED Current Sinks
8.3.3.1 LED Output Configuration
LP886x-Q1 detects LED output configuration during start-up. Any current sink output connected to ground is
disabled and excluded from the adaptive voltage control of the DC-DC converter and fault detections.
If more current is needed, LP886x-Q1's output could also be connected together to support the high current LED.
8.3.3.2 LED Current Setting
The output current of the LED outputs is controlled with external RISET resistor. RISET value for the target LED
current per channel can be calculated using Equation 5:
where
• VBG = 1.2 V
• RISET is current setting resistor, kΩ
• ILED is output current per OUTx pin, mA (5)
For example, if RISET is set to 20 kΩ, ILED will be 120 mA per channel.
8.3.3.3 Brightness Control
LP886x-Q1 controls the brightness of the display with conventional PWM. Output PWM directly follows the input
PWM. Input PWM frequency can be in the range of 100 Hz to 20 kHz.
8.3.4 Power-Line FET Control
The LP886x-Q1 has a power-line FET control feature. It has a control pin (SD) for driving the gate of an external
power-line P-Channel MOSFET. This feature grants LP886x-Q1 the ability to immediately cut-off the power part
of backlight system when failure occurs, protecting other parallel power systems from being impacted. In
addition, the feature could smooth the inrush current during powering-up by turning on the power-line FET
gradually. In SOFT START state, the SD pin slowly increases the sink current until it reaches 230 μA. An
example schematic is shown in Figure 14.
The value of RGS should follow the rules below
• ISD_MAX × RGS should be less than the power-line FET's maximum acceptable Source-Gate voltage
• ISD_MIN × RGS should be greater than the minimum power-line FET's Source-Gate voltage which could ensure
a low On-State Resistance.
A 20-kΩRGS is chosen in typical application which generates a 4.6 V difference on power-line FET's Source-
Gate voltage.
Figure 14. Power-Line FET Control Schematics
““““““ milimm
‘5‘ TEXAS
INSTRUMENTS
\ng
BG
LED
ISET
V
I = 2000
R
u
R3
R5
RT
NTC
R4
VDD
R6
R7
TSET
TSENSE
VBG
ISET
RISET
1:2000
LED DRIVER
LED OUT
ISET_SCALED
ITSENSE
ILED
+
-
ITSENSE
NTC TEMPERATURE
T1T2
LED CURRENT
100%
17.5%
19
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The LP886x-Q1 turns off the power-line FET and prevents the possible boost and LEDs leakage when the device
is disabled or in FAULT RECOVERY state.
Power-line FET control is an optional feature. Leave SD pin NC and don't use power-line FET when this feature
is not needed.
8.3.5 LED Current Dimming With External Temperature Sensor
The LP886x-Q1 has an optional feature to decrease automatically LED current when LED overheating is
detected with an external NTC sensor. An example of the behavior is shown in Figure 15. When the NTC
temperature reaches T1, the LP886x-Q1 starts to decrease the LED current. When the LED current has reduced
to 17.5% of the nominal value, current turns off until temperature returns to the operation range.
Figure 15. Temperature-Based LED Current Dimming Functionality
Figure 16. Temperature-Based LED Current Dimming Implementation
When TSET pin is grounded and TSENSE is floated, this feature is disabled. LED current is set by RISET resistor:
where
• VBG = 1.2 V
• RISET is current setting resistor, kΩ
• ILED is output current per OUTx pin, mA (6)
l TEXAS
INSTRUMENTS
R5
\SET
BG
SET _ SCALED
ISET
V
IR
u
II
TSET DD
II
TSENSE 2
II
II
II
R
V V
R R3
I
R
R R7
R R3
u
TSET DD
R5
V V
R4 R5
u
T
II
T
R R6
R
R R6
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When external NTC is connected, the TSENSE pin current decreases LED output current. Temperature T1 and
de-rate slope are defined by external resistors as explained below.
Parallel resistance of the NTC sensor RT and resistor R4 is calculated by formula:
(7)
TSET voltage can be calculated with Equation 8:
(8)
TSENSE pin current is calculated by Equation 9:
where
• VDD is the bias voltage of the resistor group. It's recommended to connect with chip's internal LDO output (pin
2) (9)
ISET pin current defined by RISET is:
(10)
For Equation 11, ITSENSE current must be limited between 0 and ISET_SCALED. If ITSENSE > ISET_SCALED then set
ITSENSE = ISET_SCALED. If ITSENSE < 0 then set ITSENSE = 0.
LED driver output current is:
ILED = (ISET_SCALED – ITSENSE ) x 2 000 (11)
When current is lower than 17.5% of the nominal value, the current is set to 0 (the cut-off point).
An Excel®calculator is available for calculating the component values for a specific NTC and target thermal
profile (contact TI E2E™ support forums ). Figure 17 shows an example thermal profile implementation.
l TEXAS
INSTRUMENTS
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0
20
40
60
80
100
120
60 70 80 90 100 110 120
TSENSE Current (mA)
LED Current (mA)
Temperature (ž&
LED current
TSENSE current
C006
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NTC – 10 kΩat 25ºC RISET = 24 kΩR2 = 10 kΩR4 = 100 kΩ
VDD = 4.3 V R1 = 10 kΩR3=2kΩR5 = 7.5 kΩ
Figure 17. Calculation Example
8.3.6 Fault Detections and Protection
The LP886x-Q1 has fault detection for LED open and short, VIN input overvoltage protection (VIN_OVP) , VIN
undervoltage protection (VIN_UVLO), VIN overcurrent protection (VIN_OCP) , Boost output overvoltage
protection (BST_OVP), SW overvoltage protection (SW_OVP) and thermal shutdown (TSD).
8.3.6.1 Supply Fault and Protection
8.3.6.1.1 VIN Undervoltage Fault (VIN_UVLO)
The LP886x-Q1 device supports VIN undervoltage protection. The VIN undervoltage falling threshold is 3.85-V
typical and rising threshold is 4-V typical. If during operation of the LP886x-Q1 device, the VIN pin voltage falls
below the VIN undervoltage falling threshold, the boost, LED outputs, and power-line FET will be turned off, and
the device will enter FAULT RECOVERY mode. The FAULT pin will be pulled low. The LP886x-Q1 will exit
FAULT RECOVERY mode after 100 ms and try the start-up sequence again. VIN_UVLO fault detection is
available in SOFT START, BOOST START, and NORMAL state.
8.3.6.1.2 VIN Overvoltage Fault (VIN_OVP)
The LP886x-Q1 device supports VIN overvoltage protection. The VIN overvoltage threshold is 43-V typical. If
during LP886x-Q1 operation, VIN pin voltage rises above the VIN overvoltage threshold, the boost, LED outputs
and the power-line FET will be turned off, and the device will enter FAULT RECOVERY mode. The FAULT pin
will be pulled low. The LP886x-Q1 will exit FAULT RECOVERY mode after 100 ms and try the start-up sequence
again. VIN_OVP fault detection is available in SOFT START, BOOST START and NORMAL state.
8.3.6.1.3 VIN Overcurrent Fault (VIN_OCP)
The LP886x-Q1 device supports VIN overcurrent protection. If during LP886x-Q1 operation, voltage drop
between VIN pin and VSENSE_N pin rises above 160-mV typical, the boost, LED outputs and the power-line
FET will be turned off, and the device will enter FAULT RECOVERY mode. The FAULT pin will be pulled low.
The LP886x-Q1 will exit FAULT RECOVERY mode after 100 ms and try the start-up sequence again. VIN_OCP
fault detection is available in SOFT START, BOOST START, and NORMAL state.
A 30-mΩresistor is recommended to put between VIN pin and VSENSE_N pin, which will set the VIN
overcurrent threshold to 5.3 A.
l TEXAS
INSTRUMENTS
HIG H_COMP
MID_COMP
LOW_COMP
OUT#
CURRENT/PWM
CONTROL
VLOW_COMP
VHIGH_COMP
VMID_COMP
)(
§ ·u
¨ ¸
© ¹
BOOST_OVP BOOST FB_OVP BG
R1
V = V + +1 V V
R2
22
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8.3.6.2 Boost Fault and Protection
8.3.6.2.1 Boost Overvoltage Fault (BST_OVP)
The LP886x-Q1 device supports boost overvoltage protection. If during LP886x-Q1 operation, the FB pin voltage
exceeds the VFB_OVP threshold, which is 2.3-V typical, the boost, LED outputs and the power-line FET will be
turned off, and the device will enter FAULT RECOVERY mode. The FAULT pin will be pulled low. The LP886x-
Q1 will exit FAULT RECOVERY mode after 100 ms and try the start-up sequence again. BST_OVP fault
detection is available in NORMAL state.
Calculating back from FB pin voltage threshold to boost output OVP voltage threshold, the value is not a static
threshold, but a dynamic threshold changing with the current target boost adaptive voltage:
where
• VBOOST is the current target boost adaptive voltage, which in most time is the current largest LED string forward
voltage among multiple strings + 0.9 V in steady state
• VFB_OVP = 2.3 V
• VBG = 1.2 V
• R1and R2is the resistor value of FB external network in Using Two-Divider and Using T-Divider (12)
For example, if R1is set to 750 kΩand R2is set to 130 kΩ, VBOOST will report OVP when the boost voltage is 7.4
V above target boost voltage.
This equation holds true in both two-divider FB external network and T-divider FB external network.
8.3.6.2.2 SW Overvoltage Fault (SW_OVP)
Besides boost overvoltage protection, the LP886x-Q1 supports SW pin overvoltage protection to further protect
the boost system from overvoltage scenario. If during LP886x-Q1 operation, the SW pin voltage exceeds the
VSW_OVP threshold, which is 49-V typical, the boost, LED outputs and the power-line FET are turned off, and the
device will enter FAULT RECOVERY mode. The FAULT pin will be pulled low. The LP886x-Q1 will exit FAULT
RECOVERY mode after 100 ms and try the start-up sequence again. SW_OVP fault detection is available in
SOFT START, BOOST START and NORMAL state.
8.3.6.3 LED Fault and Protection (LED_OPEN and LED_SHORT)
Every LED current sink has 3 comparators for LED fault detections.
Figure 18. Comparators for LED Fault Detection
Figure 19 shows cases which generates LED faults. Any LED faults will pull the Fault pin low.
During normal operation, boost voltage is raised if any of the used LED outputs falls below the VLOW_COMP
threshold. Open LED fault is detected if boost output voltage has reached the maximum and at least one LED
output is still below the threshold. The open string is then disconnected from the boost adaptive control loop and
its output is disabled.
INSTRUMENTS
OUT1
OUT2
OUT3
OUT4
No actions
Open LED fault
when
VBOOST = MAX
Short LED fault
(at least one channel between
LOW_COMP and MID COMP)
Open LED Fault Short LED Fault
Normal Condition Fault Condition
OUT1~4 PIN
VOLTAGE
VHI GH_COMP
VMID_COMP
VLOW_COMP
OUT1
OUT2
OUT3
OUT4
OUT1
OUT2
OUT3
OUT4
23
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Shorted LED fault is detected if one or more LED outputs are above the VHIGH_COMP threshold (typical 6 V) and at
least one LED output is inside the normal operation window (between VLOW_COMP and VMID_COMP, typical 0.9 V
and 1.9 V). The shorted string is disconnected from the boost adaptive control loop and its output is disabled.
LED Open fault detection and LED Short fault detection are available only in NORMAL state.
Figure 19. Protection and DC-DC Voltage Adaptation Algorithms
If LED fault is detected, the device continues normal operation and only the faulty string is disabled. The fault is
indicated via the FAULT pin which can be released by toggling VDDIO/EN pin low for a short period of 2 µs to 20
µs. LEDs are turned off for this period but the device stays in NORMAL state. If VDDIO/EN is low longer, the
device goes to STANDBY and restarts when EN goes high again.
This means if the system doesn't want to simply disable the device because of LED faults. It could clear the LED
faults by toggling VDDIO/EN pin low for a short period of 2 µs to 20 µs.
8.3.6.4 Thermal Fault and Protection (TSD)
If the die temperature of LP886x-Q1 reaches the thermal shutdown threshold TTSD, which is 165°C typical, the
boost, power-line FET and LED outputs are turned off to protect the device from damage. The FAULT pin will be
pulled low. The LP886x-Q1 will exit FAULT RECOVERY mode after 100 ms and try the start-up sequence again.
Only if the die temperature drops lower than TTSD - TTSD_HYS, which is 145°C typical, the device could start-up
normally. TSD fault detection is available in SOFT START, BOOST START and NORMAL state.
l TEXAS
INSTRUMENTS
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8.3.6.5 Overview of the Fault and Protection Schemes
A summary of the LP886x-Q1 fault detection behavior is shown in Table 3. Detected faults (excluding LED open or short) cause device to enter FAULT
RECOVERY state. In FAULT_RECOVERY the DC-DC and LED current sinks of the device are disabled, and the FAULT pin is pulled low. The device will
exit FAULT RECOVERY mode after 100 ms and try the start-up sequence again. When recovery is successful and device enters into NORMAL state, the
FAULT pin is released high.
Table 3. Fault Detections
FAULT/
PROTECTION FAULT NAME CONDITION FAULT
PIN
Enter FAULT_
RECOVERY
STATE ACTIVE STATE ACTION
VIN overvoltage
protection VIN_OVP VIN > 43 V Yes Yes SOFT START, BOOST
START, NORMAL Device enters into FAULT RECOVERY state, and restarts after
100 ms
VIN undervoltage
protection VIN_UVLO
Effective when VIN <
3.85 V
Released when VIN >4
V
Yes Yes SOFT START, BOOST
START, NORMAL Device enters into FAULT RECOVERY state, and restarts after
100 ms
VIN overcurrent
protection VIN_OCP VIN-VSENSE_N >
160mV Yes Yes SOFT START, BOOST
START, NORMAL Device enters into FAULT RECOVERY state, and restarts after
100 ms
Open LED fault LED _OPEN
Adaptive Voltage is
max. and
any OUTx voltage <
0.9 V
Yes No NORMAL
Open string is removed from the DC-DC voltage control loop
and output is disabled.
Fault pin low could be released by toggling VDDIO/EN pin, If
VDDIO/EN is low for a period of 2 µs to 20 µs, LEDs are turned
off for this period but device stays in NORMAL.
Shorted LED fault LED_SHORT
One of OUTx voltage
is [0.9 V, 1.9 V] and
any OUTx voltage > 6
V
Yes No NORMAL
Short string is removed from the DC-DC voltage control loop
and output is disabled.
Fault pin low could be released by toggling VDDIO/EN pin, If
VDDIO/EN is low for a period of 2 µs to 20 µs, LEDs are turned
off for this period but device stays NORMAL.
Boost overvoltage
protection BST_OVP VFB > 2.3 V Yes Yes NORMAL
Fault is detected if boost overvoltage condition duration is more
than 560 ms
Device enters into FAULT RECOVERY state, and restarts after
100 ms
SW overvoltage
protection SW_OVP VSW > 49 V Yes Yes SOFT START, BOOST
START, NORMAL Device enters into FAULT RECOVERY state, and restarts after
100 ms
Thermal protection TSD
Effective when Tj >
165 ºC
Released when Tj <
145 ºC
Yes Yes SOFT START, BOOST
START, NORMAL Device enters into FAULT RECOVERY state, and restarts until
TSD fault is released
l TEXAS
INSTRUMENTS
vw>v
STANDBY
VIN > VUVLO
VDDIO / EN = 1
BOOST START
SOFT START
NORMAL
65 ms
50 ms
FAULT RECOVERY
100 ms
FAULT
VDDIO / EN = 0
VDDIO / EN = 0
LED OUTPUT
CONFIGURATION
DETECTION
(1st time power-up only)
FAULT
FAULT
25
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8.4 Device Functional Modes
8.4.1 STANDBY State
The LP886x-Q1 enters STANDBY state when the VIN voltage powers on and voltage is higher than VINUVLO
rising threshold, which is 4-V typical. In STANDBY state, the device is able to detect VDDIO/EN signal. When
VDDIO/EN is pulled high, the internal LDO wakes up and the device enters into SOFT START state. The device
will re-enter the STANDBY state when VDDIO/EN is pulled low for more than 50 µs.
8.4.2 SOFT START State
In SOFT START state, Power-line FET is enabled, and boost input and output capacitors are charged to VIN
level. VIN_OCP, VIN_OVP, VIN_UVLO, SW_OVP and TSD fault are active. After 65 ms, the device enters into
BOOST START state.
8.4.3 BOOST START State
In BOOST START state, DC-DC controller is turned on and boost voltage is ramped to initial boost voltage level
with reduced current limit. VIN_OCP, VIN_OVP, VIN_UVLO, SW_OVP and TSD fault are active in this state.
After 50 ms, LED outputs do a one-time detection on grounded outputs. Grounded outputs are disabled and
excluded from the adaptive voltage control loop. Then the device enters into NORMAL state.
8.4.4 NORMAL State
In NORMAL state, LED drivers are enabled when PWM signal is high. All faults are active in this state. Fault pin
will be released high in the start of NORMAL state if recovering from FAULT RECOVERY state and no fault is
available.
8.4.5 FAULT RECOVERY State
Non-LED faults can trigger fault recovery state. LED drivers, boost converter and power-line FET are all disabled.
After 100 ms, the device attempts to restart from SOFT START state if VDDIO/EN is still high.
8.4.6 State Diagram and Timing Diagram for Start-up and Shutdown
Figure 20. State Diagram
l TEXAS
INSTRUMENTS
«"o'o'o'o'o'owwWWW”
x ‘ ‘
H—N“—"
VIN
LDO
VOUT
PWM OUT
IQ
Headroom adaptation
Active mode
VDDIO/EN
VOUT=VIN level ± diode drop
SOFT
START
BOOST
START
t>500s
SYNC
T=50s
26
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Device Functional Modes (continued)
Figure 21. Timing Diagram for the Typical Start-Up and Shutdown
l TEXAS
INSTRUMENTS
Vm
LP8867-Q1
FB
PWM
OUT1
OUT2
OUT3
OUT4
L1 D1 Up to 34V
VIN
5...28 V
COUT
CIN BOOST
RISET
SW
LDO
FSET
VDDIO/EN
SYNC
PGND GND PAD
VSENSE_N
ISETFAULT
VDDIO/EN
BRIGHTNESS
RFSET
R1R2
CLDO
FAULT
CIN
R8
VDDIO/EN
Q1RISENSE
RGS SD
VIN
TSENSE
TSET
VLDO
R3R4
R5R6
R7
NTC
RTf
27
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LP886x-Q1 is designed for automotive applications. The input voltage (VIN) is intended to be connected to
the automotive battery, which supports voltage range from 4.5 V to 40 V. Device internal circuitry is powered
from the integrated LDO.
The LP886x-Q1 uses a simple four-wire control:
• VDDIO/EN for enable
• PWM input for brightness control
• SYNC pin for boost synchronisation (optional)
• FAULT output to indicate fault condition (optional)
9.2 Typical Applications
9.2.1 Typical Application for 4 LED Strings
Figure 22 shows the typical application for LP886x-Q1 which supports 4 LED strings, 100 mA per string with a
boost switching frequency of 400 kHz.
Figure 22. Four Strings 100 mA per String Configuration
l TEXAS
INSTRUMENTS
om
ISAT >
x
(VOUT - VIN)
VOUT
VIN
Where D =
Where IRIPPLE = (2 x L x f)
DQG'¶= (1 - D)
(VOUT ± VIN)
(VOUT)
+ IRIPPLE
IOUTMAX
'¶ For Boost
28
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Typical Applications (continued)
9.2.2 Design Requirements
Table 4. Design Requirements Table
DESIGN PARAMETER VALUE
VIN voltage range 5 V – 28 V
LED string 4P8S LEDs (30 V max)
LED string current 100 mA
Maximum boost voltage 34 V
Boost switching frequency 400 kHz
External boost sync not used
Boost spread spectrum enabled
L1 33 μH
CIN 100 µF, 50 V
CIN BOOST 2 × (10 µF, 50-V ceramic) + 33 µF, 50-V electrolytic
COUT 2 × (10 µF, 50-V ceramic) + 33 µF, 50-V electrolytic
CLDO 1 µF, 10 V
RISET 24 kΩ
RFSET 160 kΩ
R1 685 kΩ
R2 130 kΩ
R8 10 kΩ
9.2.3 Detailed Design Procedure
9.2.3.1 Inductor Selection
There are two main considerations when choosing an inductor; the inductor must not saturate, and the inductor
current ripple must be small enough to achieve the desired output voltage ripple. Different saturation current
rating specifications are followed by different manufacturers so attention must be given to details. Saturation
current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of
application should be requested from the manufacturer. Shielded inductors radiate less noise and are preferred.
The saturation current must be greater than the sum of the maximum load current, and the worst case average-
to-peak inductor current. Equation 13 shows the worst case conditions
• IRIPPLE - peak inductor current
• IOUTMAX - maximum load current
• VIN - minimum input voltage in application
• L - min inductor value including worst case tolerances
• f - minimum switching frequency
• VOUT - output voltage
• D - Duty Cycle for CCM Operation (13)
As a result, the inductor should be selected according to the ISAT. A more conservative and recommended
approach is to choose an inductor that has a saturation current rating greater than the maximum current limit. A
saturation current rating of at least 4.1 A is recommended for most applications. See Table 2 for recommended
inductance value for the different switching frequency ranges. The inductor’s resistance should be less than
300 mΩfor good efficiency.
l TEXAS
INSTRUMENTS
mu
Output Current (mA)
System Efficiency (%)
80 160 240 320 400 480
68
72
76
80
84
88
92
96
100
D011
VIN = 16V
VIN = 12V
VIN = 8V
VIN = 6V
29
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See detailed information in Understanding Boost Power Stages in Switch Mode Power Supplies.
Power Stage Desinger Tool can be used for the boost calculation.
9.2.3.2 Output Capacitor Selection
A ceramic capacitor with 2 × VMAX BOOST or more voltage rating is recommended for the output capacitor. The
DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance
value selection. If the selected ceramic capacitors' voltage rating is less than 2 × VMAX BOOST, an alternative way
is to increase the number of ceramic capacitors. Capacitance recommendations for different switching
frequencies are shown in Table 2. To minimize audible noise of ceramic capacitors their physical size should
typically be minimized.
9.2.3.3 Input Capacitor Selection
A ceramic capacitor with 2 × VIN MAX or more voltage rating is recommended for the input capacitor. The DC-bias
effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance value
selection. If the selected ceramic capacitors' voltage rating is less than 2 × VMAX BOOST, an alternative way is to
increase the number of ceramic capacitors. Capacitance recommendations for different boost switching
frequencies are shown in Table 2.
9.2.3.4 LDO Output Capacitor
A ceramic capacitor with at least 10-V voltage rating is recommended for the output capacitor of the LDO. The
DC-bias effect can reduce the effective capacitance by up to 80%, which needs to be considered in capacitance
value selection. Typically a 1-µF capacitor is sufficient.
9.2.3.5 Diode
A Schottky diode should be used for the boost output diode. Do not use ordinary rectifier diodes, because slow
switching speeds and long recovery times degrade the efficiency and the load regulation. Diode rating for peak
repetitive current should be greater than inductor peak current (up to 4.1 A) to ensure reliable operation in boost
mode. Average current rating should be greater than the maximum output current. Schottky diodes with a low
forward drop and fast switching speeds are ideal for increasing efficiency. Choose a reverse breakdown voltage
of the Schottky diode significantly larger than the output voltage. The junction capacitance of Schottky diodes are
also very important. Big junction capacitance leads to huge reverse current and big noise when boost is
switching. A <500-pF junction capacitance at VR= 0.1 V Schottky diode is recommended.
9.2.4 Application Curves
Load 4 strings, VBoost = 30 V ƒsw=400 kHz, 22 μH
Figure 23. LED Backlight Efficiency Figure 24. Typical Start-Up
l TEXAS
INSTRUMENTS
“W
i . H >117
1 I
W
L P
if «x xx «x v
7 “H ’i xx 'K‘K «I: «x
“—in « 'K ‘K x V
W7
K‘K 'K‘K ‘K‘K ‘K‘K
W
4%
LP8867-Q1
FB
PWM
OUT1
OUT2
OUT3
OUT4
D1 Up to 20V
VIN
4.5...30 V
COUT
CIN BOOST
RISET
SW
LDO
FSET
VDDIO/EN
SYNC
PGND GND PAD
VSENSE_N
ISETFAULT
VDDIO/EN
BRIGHTNESS
RFSET
R1R2
CLDO
FAULT
CIN
R3
VDDIO/EN
L1 C1
TSENSE
TSET
VIN
SD
C2
30
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9.2.5 SEPIC Mode Application
When LED string voltage can be above or below VIN voltage, SEPIC configuration can be used. In this example,
two separate coils or coupled coil could both be used for SEPIC. Separate coils can enable lower height external
components to be used, compared to a coupled coil solution. On the other hand, coupled coil typically maximizes
the efficiency. Also, in this example, an external clock is used to synchronize SEPIC switching frequency.
External clock input can be modulated to spread switching frequency spectrum.
Figure 25. SEPIC Mode, 4 Strings 100-mA per String Configuration
l TEXAS
INSTRUMENTS
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9.2.5.1 Design Requirements
Table 5. Design Requirements Table
DESIGN PARAMETER VALUE
VIN voltage range 4.5 V – 30 V
LED string 4P4S LEDs (15 V max)
LED string current 100 mA
Maxmum output voltage 20 V
SEPIC switching frequency 2.2 MHz
External sync for SEPIC used
Spread spectrum Internal spread spectrum disabled (external sync used)
L1, L2 4.7 μH
CIN 10 µF 50 V
CIN SEPIC 2 × 10 µF, 50-V ceramic + 33 µF, 50-V electrolytic
C1 10-µF 50-V ceramic
C2 30 pF
COUT 2 × 10 µF, 50-V ceramic + 33 µF, 50-V electrolytic
CLDO 1 µF, 10 V
RISET 24 kΩ
RFSET 24 kΩ
R1 265 kΩ
R2 37 kΩ
R3 10 kΩ
9.2.5.2 Detailed Design Procedure
In SEPIC mode the maximum voltage at the SW pin is equal to the sum of the input voltage and the output
voltage. Because of this, the maximum sum of input and output voltage must be limited below 49 V. See the
Detailed Design Procedure section for general external component guidelines. Main differences of SEPIC
compared to boost are described below.
Power Stage Designer™ Tool can be used for modeling SEPIC behavior. For detailed explanation on SEPIC see
Texas Instruments Analog Applications Journal Designing DC/DC Converters Based on SEPIC Topology.
9.2.5.2.1 Inductor
In SEPIC mode, currents flowing through the coupled inductors or the two separate inductors L1 and L2 are the
input current and output current, respectively. Values can be calculated using Power Stage Designer™ Tool or
using equations in Designing DC/DC Converters Based on SEPIC Topology.
9.2.5.2.2 Diode
In SEPIC mode diode peak current is equal to the sum of input and output currents. Diode rating for peak
repetitive current should be greater than SW pin current limit (up to 4.1 A for transients) to ensure reliable
operation in boost mode. Average current rating should be greater than the maximum output current. Diode
voltage rating must be higher than sum of input and output voltages.
9.2.5.2.3 Capacitor C1
TI recommends a ceramic capacitor with low ESR. Capacitor voltage rating must be higher than maximum input
voltage.
l TEXAS
INSTRUMENTS
Output Current (mA)
SEPIC Efficiency (%)
80 160 240 320 400 480
70
72
74
76
78
80
82
84
86
88
90
D012
VIN = 16V
VIN = 12V
VIN = 8V
VIN = 6V
Output Current (mA)
System Efficiency (%)
80 160 240 320 400 480
64
66
68
70
72
74
76
78
80
82
84
D013
VIN = 16V
VIN = 12V
VIN = 8V
VIN = 6V
32
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9.2.5.3 Application Curves
4 strings, 4 LEDs per string
fsw = 2.2 MHz
IHCL-4040DZ-5A 4.7 μH
Figure 26. SEPIC Efficiency
4 strings, 4LEDs per string
fsw = 2.2 MHz
IHCL-4040DZ-5A 4.7 μH
Figure 27. LED Backlight Efficiency
10 Power Supply Recommendations
The device is designed to operate from an automotive battery. Device should be protected from reversal voltage
and voltage dump over 50 V. The resistance of the input supply rail must be low enough so that the input current
transient does not cause a high drop at LP886x-Q1 VIN pin. If the input supply is connected by using long wires,
additional bulk capacitance may be required in addition to the ceramic bypass capacitors in the VIN line.
11 Layout
11.1 Layout Guidelines
Figure 28 is a layout recommendation for LP886x-Q1 used to demonstrate the principles of a good layout. This
layout can be adapted to the actual application layout if or where possible. It is important that all boost
components are close to the chip, and the high current traces must be wide enough. By placing boost
components on one side of the chip it is easy to keep the ground plane intact below the high current paths. This
way other chip pins can be routed more easily without splitting the ground plane. Bypass LDO capacitor must be
placed as close as possible to the device.
Here are some main points to help the PCB layout work:
• Current loops need to be minimized:
– For low frequency the minimal current loop can be achieved by placing the boost components as close as
possible to the SW and PGND pins. Input and output capacitor grounds must be close to each other to
minimize current loop size.
– Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact
under the current traces. High-frequency return currents find a route with minimum impedance, which is
the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when
return current flows just under the positive current route in the ground plane, if the ground plane is intact
under the route. To minimize the current loop for high frequencies:
– Inductor's pin in SW node needs to be as near as possible to chip's SW pin
– Put a small capacitor as near as possible to the diode's pin in boost output node and arrange vias to
PGND plane close to the capacitor's GND pin.
• Use separate power and noise-free grounds. PGND is used for boost converter return current and noise-free
ground is used for more sensitive signals, such as LDO bypass capacitor grounding as well as grounding the
GND pin of the device.
• Boost output feedback voltage to LEDs must be taken out after the output capacitors, not straight from the
diode cathode.
• Place LDO 1-µF bypass capacitor as close as possible to the LDO pin.
INSTRUMENTS
1
2
3
4
5
6
7
20
19
18
17
16
15
14
13
12
11
OUT3
GND
OUT2
OUT4
TSENSE
LDO
VDDIO/EN
FSET
VIN VSENSE_N
SD
FB
PGND
SW
OUT1
TSET
PWM
FAULT
ISET
SYNC
RISET
RFSE T
VBOOST
10
8
9
LED STRINGS
RISEN S E
VIN
GND
PGND
PGND
Vias to PGND Plane
The only Connection points
between GND & PGND
PGND
GND
GND
RGS
33
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Layout Guidelines (continued)
• Input and output capacitors require strong grounding (wide traces, many vias to GND plane).
11.2 Layout Example
Figure 28. LP886x-Q1 Boost Layout
l TEXAS
INSTRUMENTS
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
Power Stage Designer™ Tool can be used for both boost and SEPIC: Power Stage Designer™ Tool
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•PowerPAD™ Thermally Enhanced Package
•Understanding Boost Power Stages in Switch Mode Power Supplies
•Designing DC-DC Converters Based on SEPIC Topology
•TI E2E™ support forums
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
Power Stage Designer, E2E are trademarks of Texas Instruments.
Excel is a registered trademark of Microsoft Corporation.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I
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Sample:
Sample:
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LP8867QPWPRQ1 ACTIVE HTSSOP PWP 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 8867Q
LP8869QPWPRQ1 ACTIVE HTSSOP PWP 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 8869Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 2
I TEXAS
INSTRUMENTS
REEL DIMENSIONS TAPE DIMENSIONS
7 “K0 '«m»
Reel
Diame|er
AD Dimension deswgned to accommodate the componem wwdlh
E0 Dimension desxgned to accommodate the componenl \ength
KO Dimenslun deswgned to accommodate the componem thickness
7 w OveraH wwdm loe earner cape
i p1 Pitch between successwe cavuy cemers
f
T Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
O O O D O O D O Sprockemoles
,,,,,,,,,,, ‘
User Direcllon 0' Feed
Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LP8867QPWPRQ1 HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
LP8869QPWPRQ1 HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jan-2020
Pack Materials-Page 1
I TEXAS
INSTRUMENTS
TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP8867QPWPRQ1 HTSSOP PWP 20 2000 350.0 350.0 43.0
LP8869QPWPRQ1 HTSSOP PWP 20 2000 350.0 350.0 43.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jan-2020
Pack Materials-Page 2
THERMAL PAD MECHANICAL DATA
PWP (RmPDSOmGZO) F’owerPADTM SMALL PLASTIC OUTLiNE
THERMAL iNFORMATiON
This PowerPAD‘“ package incorporates an exposed thermal pad that is designed to be attached to a printed
circuit board (PCB). The thermal pad must he soldered directly to the Peer After soldering. the PCB can
be used as a heatsink. in addition, through the use of thermal vias. the thermal pad can be attached
directly to the appropriate copper plane shown in the electrical schematic for the device. or alternatively,
can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat
transfer from the integrated circuit (IC).
For additional information on the PowerPAD package and how to take advantage of its heat dissipating
abilities. refer to Technical Brief, PowerPAD Thermally Enhanced Package. Texas instruments Literature
Not SLMAOUZ and Application Brief PowerPAD Made Easy, Texas instruments Literature Na, SLMAOUIL
Both documents are avaiinbie at www.ti.corn.
The expased thermal pad dimensions for this package are shown in the following illustration
iiiiiiiiii
1.15 MAX
W
p;
a
a
FE
LBJ—L
HHiHHHHiHIHU
7 Exposed Thermal Pad
Top View
Exposed Thermui Pod Dimensions
4206332715/1‘0 01/15
NOTE: A. Ali iineur dimensions are in miliimeters
A Exposed tie strap features may not be present.
inIrPAD is a tndomark olT-xas instrumlnts
{5i TEXAS
INSTRUMENTS
com
LAND PATTERN DATA
PWP (R—PDSO—GZO) PowerPADW PLASTlC SMALL OUTLINE
Example Board Layout Stencil Openln s_
Via pattern and copper pad size Based on a slencl‘t Ickness
may vary dependlng on layout constraints 0' -tZ7mm (-005Inch)-
Reference table below tor other
l“”“5'“ae‘°we’ W“ W'” solder stencil thicknesses
enhance t rmal performance
(See Note D)
,3 4>T l—il8x0,65 20x0.25—— ‘—
-—HHTHHHHTH
5.6 2,4 3.4 (See Note E) Y 2.4
_l x l
3.7
Solder: Mask Example Solder Mask _—|:| H :| H H H H [ H H
as upper -
<52:"l2tepé‘,dal l8x0.65»l="" l6="" 1/="" example="" i="" non="" saldermask="" defined="" pad="" '="" ‘/="" \‘\.="" example="" solder="" mask="" opening="" (see="" nme="" f)="" center="" power="" pud="" solder="" stencil="" opening="" stencil="" thickness="" x="" y="" 0.1mm="" 3.9="" 2.7="" 0.127rnrn="" 3.7="" 2.4="" pad="" geometry="" 0.152mm="" 3.5="" 2.2="" o="" 07="" 0.178mm="" 3.3="" 2.1="" 4207609s8/w="" 09/15="" notes:="" all="" llnear="" dimensions="" are="" ln="" millimeters="" thls="" drawing="" is="" subject="" to="" change="" without="" notice.="" customers="" should="" place="" a="" note="" on="" the="" circuit="" board="" raan'calian="" drawing="" not="" ta="" alter="" the="" center="" solder="" musk="" defined="" pad.="" this="" package="" is="" deslgned="" to="" be="" soldered="" to="" a="" lnennal="" pad="" on="" the="" baard,="" reler="" to="" technical="" brier,="" powerpod="" thermally="" enhanced="" package.="" texas="" instruments="" literature="" no.="" slmaooz,="" slmaom,="" and="" also="" the="" product="" data="" sheets="" (or="" specific="" thermal="" information.="" via="" requirements.="" and="" recommended="" board="" layout.="" these="" documents="" are="" available="" at="" wwwtieam="">
THERMAL PAD MECHANICAL DATA
PWP (RmPDSOmGZO) PowerPADTM SMALL PLASTIC OUTLiNE
THERMAL iNFORMATiON
This PowerPAD‘“ package incorporates an exposed thermal pad that is designed to be attached to a printed
circuit board (PCB). The thermal pad must he soldered directly to the PCB After soldering. the PCB can
be used as a heatsink. in addition, through the use of thermal vi'os. the thermal pad can be attached
directly to the appropriate copper plane shown in the electrical schematic for the device. or alternatively,
can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat
transfer from the integrated circuit (IC).
For additional information on the PowerPAD package and how to take advantage of its heat dissipating
abilities. refer to Technical Brief, PowerPAD Thermally Enhanced Package. Texas instruments Literature
Nou SLMAOUZ and Application Brief PowerPAD Made Easy, Texas instruments Literature Na, SLMAOUIL
Both documents are available at www.ti.com.
The expased thermal pad dimensions for this package are shown in the following illustration
fiiiiiiiiifi
“i 4UMAX&
firmimiL
a”, J: :
J—_L___+_——J Exposed Thermal Pad
1 3,20 In
2.45
Top View
Exposed Thermal Pod Dimensions
4206332718/A0 01/15
NOTE: A. All linear dimensions are in millimeters
@ Exposed tie strap features may not be present.
inIrPAD is a tmdomark ol'i-xas instrumlnts
{5i TEXAS
INSTRUMENTS
com
LAND PATTERN DATA
PWP (R—PDSO—GZO) PowerPADW PLASTlC SMALL OUTLINE
Example Board Layout Stencil Openin s_
Via pattern and copper pad size Based on a slencll‘t Ickness
may vary dependlng on layout constraints 0' 125mm (-005Inch)-
Reference table below tor other
l“”“5'“ae‘°we’ W“ W'” solder stencil thicknesses
enhanee t rmal performance
12X 1 3 (See Note D)
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