Datenblatt für L6229Q von STMicroelectronics

August 2010 Doc ID 15209 Rev 3 1/28
28
L6229Q
DMOS driver for three-phase brushless DC motor
Features
■Operating supply voltage from 8 to 52 V
■2.8 A output peak current (1.4 A RMS)
■RDS(on) 0.73 Ω typ. value @ TJ = 25 °C
■Operating frequency up to 100 kHz
■Non dissipative overcurrent detection and
protection
■Diagnostic output
■Constant tOFF PWM current controller
■Slow decay synchronous rectification
■60° and 120° hall effect decoding logic
■Brake function
■Cross conduction protection
■Thermal shutdown
■Under voltage lockout
■Integrated fast free wheeling diodes
Description
The L6229Q is a DMOS fully integrated three-
phase motor driver with overcurrent protection.
Realized in BCDmultipower technology, the
device combines isolated DMOS power
transistors with CMOS and bipolar circuits on the
same chip.
The device includes all the circuitry needed to
drive a three-phase BLDC motor including: a
three-phase DMOS bridge, a constant off time
PWM current controller and the decoding logic for
single ended hall sensors that generates the
required sequence for the power stage.
Available in VFQFPN-32 5 x 5 package, the
L6229Q features a non-dissipative overcurrent
protection on the high side power MOSFETs and
thermal shutdown.
VFQFPN32 5 mm x 5 mm
Table 1. Device summary
Order codes Package Packaging
L6229Q VFQFPN32 5x5x1.0 mm Tube
L6229QTR Tape and reel
www.st.com
Contents L6229Q
2/28 Doc ID 15209 Rev 3
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4 Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5 Decoding logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6 Tacho . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 20
6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1 Output current capability and ic power dissipation . . . . . . . . . . . . . . . . . . 23
6.2 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
HALL mm smsms DEcoDwe LOG‘C f f vomeg nzeuwon Doc ID 152
L6229Q Block diagram
Doc ID 15209 Rev 3 3/28
1 Block diagram
Figure 1. Block diagram
CHARGE
PUMP
VOLTAGE
REGULATOR
HALL-EFFECT
SENSORS
DECODING
LOGIC
THERMAL
PROTECTION
TACHO
MONOSTABLE
OCD1
OCD
OCD
OCD2
10V 5V
VCP
VSA
GATE
LOGIC
VBOOT VBOOT
OUT1
OUT2
SENSEA
VSB
OUT3
SENSEB
DIAG
EN
FWD/REV
BRAKE
H
3
H
1
RCPULSE
D99IN1095B
TACHO
RCOFF
H
2
OCD3
ONE SHOT
MONOSTABLE
MASKING
TIME
VBOOT
OCD1
10V
VBOOT
OCD2
10V
VBOOT
OCD3
10V
SENSE
COMPARATOR
+
-
PWM
VREF
£1
Electrical data L6229Q
4/28 Doc ID 15209 Rev 3
2 Electrical data
2.1 Absolute maximum ratings
2.2 Recommended operating conditions
Table 2. Absolute maximum ratings
Symbol Parameter Parameter Value Unit
VSSupply voltage VSA = VSB = VS60 V
VOD
Differential voltage between:
VSA, OUT1, OUT2, SENSEA and
VSB, OUT3, SENSEB
VSA = VSB = VS = 60 V;
VSENSEA = VSENSEB =
GND
60 V
VBOOT Bootstrap peak voltage VSA = VSB = VSVS + 10 V
VIN, VEN Logic inputs voltage range -0.3 to +7 V
VREF Voltage range at pin VREF -0.3 to +7 V
VRCOFF Voltage range at pin RCOFF -0.3 to +7 V
VRCPULSE Voltage range at pin RCPULSE -0.3 to +7 V
VSENSE
Voltage range at pins SENSEA and
SENSEB
-1 to +4 V
IS(peak)
Pulsed supply current (for each VS
pin)
VSA = VSB = VS;
TPULSE < 1 ms 3.55 A
ISRMS supply current (for each VS pin) VSA = VSB = VS1.4 A
Tstg, TOP
Storage and operating temperature
range -40 to 150 °C
Table 3. Recommended operating conditions
Symbol Parameter Parameter Min Max Unit
VSSupply voltage
V
SA
=
VSB =
VS852V
VOD
Differential voltage between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
V
SA
=
VSB =
VS;
V
SENSEA
= V
SENSEB
52 V
VREFA, VREFB
Voltage range at pins VREFA and
VREFB
-0.1 5 V
VSENSEA,
VSENSEB
Voltage range at pins SENSEA and
SENSEB
(pulsed tW < trr)
(DC)
-6
-1
6
1
V
V
IOUT RMS output current 1.4 A
TJOperating junction temperature -25 +125 °C
fsw Switching frequency 100 kHz
L6229Q Electrical data
Doc ID 15209 Rev 3 5/28
2.3 Thermal data
Table 4. Thermal data
Symbol Parameter Value Unit
R
th(JA)
Thermal resistance junction-ambient max. (1)
1. Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6
cm2 ground layer connected through 18 via holes (9 below the IC).
42 °C/W
Note: 6/28 on ction (top View) 1 The pins 210 8 are connsded to die PAD. 2 The die PAD must be connected to GND pin. Doc ID 15209 Rev 3
Pin connection L6229Q
6/28 Doc ID 15209 Rev 3
3 Pin connection
Figure 2. Pin connection (top view)
Note: 1 The pins 2 to 8 are connected to die PAD.
2 The die PAD must be connected to GND pin.
124
23
22
21
20
19
18
17
9 10111213141516
32 31 30 29 28 27 26 25
GND VCP
OUT2
VSA
GND
VSB
OUT3
NC
VBOO
T
NC
NC
NC
NC
NC
NC
NC
TACHO
NC
RCPULSE
FW/REW
EN
VREF
BRAKE
SENSEB
NC
OUT1
RCOFF
DIAG
H1
H3
H2
SENSEA
2
3
4
5
6
7
8
L6229Q Pin connection
Doc ID 15209 Rev 3 7/28
Table 5. Pin description
N° Pin Type Function
1, 21 GND GND Ground terminals.
9TACHO
Open drain
output
Frequency-to-voltage open drain output. Every pulse from pin H1 is shaped
as a fixed and adjustable length pulse.
11 RCPULSE RC pin
RC network pin. A parallel RC network connected between this pin and
ground sets the duration of the monostable pulse used for the frequency-to-
voltage converter.
12 SENSEBPower supply
Half bridge 3 source Pin. This pin must be connected together with pin
SENSEA to power ground through a sensing power resistor. At this pin also
the Inverting Input of the sense comparator is connected.
13 FWD/REV Logic input
Selects the direction of the rotation. HIGH logic level sets forward operation,
whereas LOW logic level sets reverse operation.
If not used, it has to be connected to GND or +5 V.
14 EN Logic input Chip enable. LOW logic level switches OFF all power MOSFETs.
If not used, it has to be connected to +5 V.
15 VREF Logic input Current controller reference voltage.
Do not leave this pin open or connect to GND.
16 BRAKE Logic input
Brake input pin. LOW logic level switches ON all high side power MOSFETs,
implementing the brake function.
If not used, it has to be connected to +5 V.
17 VBOOT Supply
voltage Bootstrap voltage needed for driving the upper power MOSFETs.
19 OUT3Power output Output half bridge 3.
20 VSBPower supply Half bridge 3 power supply voltage. It must be connected to the supply
voltage together with pin VSA.
22 VSAPower supply Half bridge 1 and half bridge 2 power supply voltage. It must be connected to
the supply voltage together with pin VSB.
23 OUT2Power output Output half bridge 2.
24 VCP Output Charge pump oscillator output.
25 H2Sensor input Single ended hall effect sensor input 2.
26 H3Sensor input Single ended hall effect sensor input 3.
27 H1Sensor input Single ended hall effect sensor input 1.
28 DIAG Open drain
output
Overcurrent detection and thermal protection pin. An internal open drain
transistor pulls to GND when an overcurrent on one of the high side
MOSFETs is detected or during thermal protection.
29 SENSEAPower supply Half bridge 1 and half bridge 2 source pin. This pin must be connected
together with pin SENSEB to power ground through a sensing power resistor.
30 RCOFF RC pin RC network pin. A parallel RC network connected between this pin and
ground sets the current controller OFF-Time.
31 OUT1Power output Output half bridge 1.
Electrical characteristics L6229Q
8/28 Doc ID 15209 Rev 3
4 Electrical characteristics
Table 6. Electrical characteristics
(VS = 48 V, TA = 25 °C, unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit
VSth(ON) Turn-on threshold 5.8 6.3 6.8 V
VSth(OFF) Turn-off threshold 5 5.5 6 V
ISQuiescent supply current All bridges OFF;
TJ = -25 °C to 125 °C(1) 510mA
Tj(OFF) Thermal shutdown temperature 165 °C
Output DMOS transistors
RDS(on)
High-side + low-side switch ON
resistance
TJ = 25 °C 1.47 1.69 Ω
TJ =125 °C (1) 2.35 2.70 Ω
IDSS Leakage current EN = Low; OUT = VS2mA
EN = Low; OUT = GND -0.3 mA
Source drain diodes
VSD Forward ON voltage ISD = 1.4 A, EN = LOW 1.15 1.3 V
trr Reverse recovery time If = 1.4 A 300 ns
tfr Forward recovery time 200 ns
Logic inputs (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW)
VIL Low level logic input voltage -0.3 0.8 V
VIH High level logic input voltage 2 7 V
IIL Low level logic input current GND logic input voltage -10 µA
IIH High level logic input current 7 V logic input voltage 10 µA
Vth(ON) Turn-on input threshold 1.8 2.0 V
Vth(OFF) Turn-off input threshold 0.8 1.3 V
Vth(HYS) Input threshold hysteresis 0.25 0.5 V
Switching characteristics
tD(ON)EN
Enable to output turn-on delay
time (2)
ILOAD = 1.4 A, resistive load
500 650 800 ns
tD(OFF)EN Enable to output turn-off delay time (2) 500 1000 ns
tD(on)IN
Other logic inputs to OUT turn-ON delay
time 1.6 µs
tD(off)IN
Other logic inputs to OUT turn-OFF
delay time 800 ns
tRISE Output rise time (2) 40 250 ns
tFALL Output fall time (2) 40 250 ns
tDT Dead time 0.5 1 µs
L6229Q Electrical characteristics
Doc ID 15209 Rev 3 9/28
fCP Charge pump frequency TJ = -25 °C to 125 °C (1) 0.6 1 MHz
PWM comparator and monostable
IRCOFF Source current at pin RCOFF VRCOFF = 2.5 V 3.5 5.5 mA
VOFFSET Offset voltage on sense comparator (3) Vref = 0.5 V ±5 mV
tprop Turn OFF propagation delay (4) Vref = 0.5 V 500 ns
tblank
Internal blanking time on sense
comparator 1µs
tON(min) Minimum on time 2.5 3 µs
tOFF PWM recirculation time ROFF = 20 kΩ; COFF = 1 nF 13 μs
ROFF = 100 kΩ; COFF = 1 nF 61 μs
IBIAS Input bias current at pin VREF 10 µA
Tacho monostable
IRCPULSE Source current at pin RCPULSE VRCPULSE = 2.5 V 3.5 5.5 mA
tPULSE Monostable of time RPUL = 20 kΩ; CPUL = 1 nF 12 μs
RPUL = 100 kΩ; CPUL = 1 nF 60 μs
RTA C HO Open drain ON resistance 40 60 W
Over current detection and protection
ISOVER Supply overcurrent protection threshold TJ = -25 to 125 °C (2) 2 2.8 3.55 A
ROPDR Open drain ON resistance IDIAG = 4 mA 40 60 W
IOH OCD high level leakage current VDIAG = 5 V 1 µA
tOCD(ON) OCD turn-ON delay time (4) IDIAG = 4 mA; CDIAG < 100 pF 200 ns
tOCD(OFF) OCD turn-OFF delay time (4) IDIAG = 4 mA; CDIAG < 100 pF 100 ns
1. Tested at 25 °C in a restricted range and guaranteed by characterization
2. See Figure 3.
3. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF.
4. See Figure 4.
Table 6. Electrical characteristics (continued)
(VS = 48 V, TA = 25 °C, unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit
Electrical characteristics L6229Q
10/28 Doc ID 15209 Rev 3
Figure 3. Switching characteristic definition
Figure 4. Overcurrent detection timing definition
V
th(ON)
V
th(OFF)
90%
10%
EN
I
OUT
t
t
t
FALL
t
D(OFF)EN
t
RISE
t
D(ON)EN
D01IN1316
I
SOVER
90%
10%
I
OUT
V
DIAG
t
OCD(OFF)
t
OCD(ON)
D02IN1387
ON
OFF
BRIDGE
VCP vsoa vg v58 'LI. DIN/N132 Doc ID 15209 Flev 3
L6229Q Circuit description
Doc ID 15209 Rev 3 11/28
5 Circuit description
5.1 Power stages and charge pump
The L6229Q integrates a three-phase bridge, which consists of 6 power MOSFETs
connected as shown on the block diagram (see Figure 1). each power MOS has an
RDS(ON) = 0.73 Ω (typical value @ 25 °C) with intrinsic fast freewheeling diode. Switching
patterns are generated by the PWM current controller and the hall effect sensor decoding
logic (see relative paragraph 3.3 and 3.5). Cross conduction protection is implemented by
using a dead time (tDT = 1 µs typical value) set by internal timing circuit between the turn off
and turn on of two power MOSFETs in one leg of a bridge.
Pins VSA and VSB must be connected together to the supply voltage (VS).
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped supply (VBOOT) is obtained
through an internal oscillator and few external components to realize a charge pump circuit
as shown in Figure 5. The oscillator output (pin VCP) is a square wave at 600 kHz (typically)
with 10 V amplitude. Recommended values/part numbers for the charge pump circuit are
shown in Tab l e 7 .
Figure 5. Charge pump circuit
Table 7. Charge pump external component values
Component Value
CBOOT 220 nF
CP10 nF
D1 1N4148
D2 1N4148
D2
C
BOOT
D1
C
P
V
S
VS
A
VCP VBOOT VS
B
D01IN132
8
12/28 . PROTECT‘ON . _|- 001 ”wage Figure 7. Pin EN open collector driving DIAG 5V OPEN COLLECTOR OUTPUT ESD PROTECTION I ul- momma Figure 8. Pin EN push-pull driving FUSHVPULL OUTPUT DUZ/N1379 Doc ID 15209 Flev 3
Circuit description L6229Q
12/28 Doc ID 15209 Rev 3
5.2 Logic inputs
Pins FWD/REV, BRAKE, EN, H1, H2 and H3 are TTL/CMOS and microcontroller compatible
logic inputs. The internal structure is shown in Figure 6. Typical value for turn-on and turn-off
thresholds are respectively Vth(ON)= 1.8 V and Vth(OFF)= 1.3 V.
Pin EN (Enable) has identical input structure with the exception that the drain of the
Overcurrent and thermal protection MOSFET is also connected to this pin. Due to this
connection some care needs to be taken in driving this pin. The EN input may be driven in
one of two configurations as shown in Figure 10 or Figure 11. If driven by an open drain
(collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in
Figure 10. If the driver is a standard Push-Pull structure the resistor REN and the capacitor
CEN are connected as shown in Figure 11. The resistor REN should be chosen in the range
from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 10 kΩ and
5.6 nF. More information on selecting the values is found in the overcurrent protection
section.
Figure 6. Logic inputs internal structure
Figure 7. Pin EN open collector driving
Figure 8. Pin EN push-pull driving
5V
D01IN1329
ESD
PROTECTION
5V
5V
OPEN
COLLECTOR
OUTPUT
R
EN
C
EN
EN
DIAG
D02IN137
8
ESD
PROTECTION
5V
PUSH-PULL
OUTPUT
R
EN
C
EN
EN
D02IN137
9
DIAG
ESD
PROTECTION
Doc ID 15209 Flev 3
L6229Q Circuit description
Doc ID 15209 Rev 3 13/28
5.3 PWM current control
The L6229Q includes a constant off time PWM current controller. The current control circuit
senses the bridge current by sensing the voltage drop across an external sense resistor
connected between the source of the three lower power MOS transistors and ground, as
shown in Figure 9. As the current in the motor increases the voltage across the sense
resistor increases proportionally. When the voltage drop across the sense resistor becomes
greater than the voltage at the reference input pin VREF the sense comparator triggers the
monostable switching the bridge off. The power MOS remain off for the time set by the
monostable and the motor current recirculates around the upper half of the bridge in slow
decay mode as described in the next section. When the monostable times out, the bridge
will again turn on. Since the internal dead time, used to prevent cross conduction in the
bridge, delays the turn on of the power MOS, the effective off time tOFF is the sum of the
monostable time plus the dead time.
Figure 10 shows the typical operating waveforms of the output current, the voltage drop
across the sensing resistor, the pin RC voltage and the status of the bridge. More details
regarding the synchronous rectification and the output stage configuration are included in
the next section.
Immediately after the power MOS turn on, a high peak current flows through the sense
resistor due to the reverse recovery of the freewheeling diodes. The L6229Q provides a 1 µs
blanking time tBLANK that inhibits the comparator output so that the current spike cannot
prematurely re trigger the monostable.
Figure 9. PWM current controller simplified schematic
DRIVERS
+
DEAD TIME
S
Q
R
DRIVERS
+
DEAD TIME DRIVERS
+
DEAD TIME
OUT3
OUT2
SENSEBSENSEA
RSENSE
D02IN1380
RCOFF
ROFF
COFF
VREF
OUT1
+
+
-
-
1μs
5mA
BLANKER
SENSE
COMPARATOR
MONOSTABLE
SET
2.5V
5V
FROM THE
LOW-SIDE
GATE DRIVERS
BLANKING TIME
MONOSTABLE
VSB
VS
VSA
TO GATE
LOGIC
(0) (1)
Circuit description L6229Q
14/28 Doc ID 15209 Rev 3
Figure 10. Output current regulation waveforms
Figure 11 shows the magnitude of the Off Time tOFF versus COFF and ROFF values. It can be
approximately calculated from the equations:
tRCFALL = 0.6 · ROFF · COFF
tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT
where ROFF and COFF are the external component values and tDT is the internally generated
Dead Time with:
20 kΩ ≤ ROFF ≤ 100 kΩ
0.47 nF ≤ COFF ≤ 100 nF
tDT = 1 µs (typical value)
Therefore:
tOFF(MIN) = 6.6 µs
tOFF(MAX) = 6 ms
These values allow a sufficient range of tOFF to implement the drive circuit for most motors.
The capacitor value chosen for COFF also affects the Rise Time tRCRISE of the voltage at the
pin RCOFF. The rise time tRCRISE will only be an issue if the capacitor is not completely
charged before the next time the monostable is triggered. Therefore, the on time tON, which
depends by motors and supply parameters, has to be bigger than tRCRISE for allowing a
good current regulation by the PWM stage. Furthermore, the on time tON can not be smaller
than the minimum on time tON(MIN).
OFF
BCDDA
tON tOFF
BC
ON
2.5V
0Slow Decay Slow Decay
1μs tBLANK
tRCRISE tRCRISE
SYNCHRONOUS RECTIFICATION
1μs tBLANK
5V
VRC
VSENSE
VREF
IOUT
VREF
RSENSE
D02IN1351
tOFF
1μs tDT 1μs tDT
tRCFALL tRCFALL
OFF OFF “OFF
L6229Q Circuit description
Doc ID 15209 Rev 3 15/28
tRCRISE = 600 · COFF
Figure 12 shows the lower limit for the on time tON for having a good PWM current regulation
capacity. It has to be said that tON is always bigger than tON(MIN) because the device imposes
this condition, but it can be smaller than tRCRISE - tDT
. In this last case the device continues
to work but the off time tOFF is not more constant.
So, small COFF value gives more flexibility for the applications (allows smaller on time and,
therefore, higher switching frequency), but, the smaller is the value for COFF
, the more
influential will be the noises on the circuit performance.
Figure 11. tOFF versus COFF and ROFF
Figure 12. Area where tON can vary maintaining the PWM regulation
tON tON MIN()
>2.5μs=
tON tRCRISE tDT
–>
⎩⎭
⎨⎬
⎧⎫
(typ. value)
0.1 1 10 100
1
10
100
1.103
1.104
Coff [nF]
toff [μs]
Roff = 100kΩ
Roff = 47kΩ
Roff = 20kΩ
0.1 1 10 100
1
10
100
Coff [nF]
ton(min) [us]
2.5μs (typ. value)
5.5 16/28 T T T A5} i l— a {3% 4 {3r 4 .l. .L .l. —iE:}— r figw r -l {Iai— dfififlflh l} i '7 Decoding logic The decoding logic section is a combinatory logic that provides the appropriate dri threerphase bridge outputs according to the signals coming from the three hall se detect rotor position in a Srphase BLDC motor. This novel combinatory logic discr between the actual sensor positions for sensors spaced at 60, 120, 240 and 300 degrees. This decoding method allows the implementation ol a universal IC witho dedicating pins to select the sensor configuration. There are eight possible inpul combinations for three sensor inputs. Six combinat valid for rotor positions with 120 electrical degrees sensor phasing (see Figure 14 1, 2, 3a, 4, 5 and 6a) and six combinations are valid for rotor positions with 60 ele degrees phasing (see Figure 15, positions 1, 2, 3b, 4, 5 and 6b). Four of them are common (1, 2, 4 and 5) whereas there are two combinations used only in 120 ele degrees sensor phasing (3a and 6a) and two combinations used only in 60 electr degrees sensor phasing (3b and 6b). The decoder can drive motors with different sensor configuration simply by follow Table 8. For any input conliguration (H‘, H2 and H3) there is one output conligurati OUT2 and OUT3). The output configuration 3a is the same than 3b and analogou conliguration 6a is the same lhan 6b. The sequence ol the Hall codes for 300 electrical degrees phasing is the reverse the sequence ol the Hall codes for 240 phasing is the reverse of 120. So, by decod Doc ID 15209 Flev 3
Circuit description L6229Q
16/28 Doc ID 15209 Rev 3
5.4 Slow decay mode
Figure 13 shows the operation of the bridge in the slow decay mode during the off time. At
any time only two legs of the three-phase bridge are active, therefore only the two active
legs of the bridge are shown in the figure and the third leg will be off. At the start of the Off
Time, the lower power MOS is switched off and the current recirculates around the upper
half of the bridge. Since the voltage across the coil is low, the current decays slowly. After
the dead time the upper power MOS is operated in the synchronous rectification mode
reducing the impedance of the freewheeling diode and the related conducting losses. When
the monostable times out, upper MOS that was operating the synchronous mode turns off
and the lower power MOS is turned on again after some delay set by the dead time to
prevent cross conduction.
Figure 13. Slow decay mode output stage configurations
5.5 Decoding logic
The decoding logic section is a combinatory logic that provides the appropriate driving of the
three-phase bridge outputs according to the signals coming from the three hall sensors that
detect rotor position in a 3-phase BLDC motor. This novel combinatory logic discriminates
between the actual sensor positions for sensors spaced at 60, 120, 240 and 300 electrical
degrees. This decoding method allows the implementation of a universal IC without
dedicating pins to select the sensor configuration.
There are eight possible input combinations for three sensor inputs. Six combinations are
valid for rotor positions with 120 electrical degrees sensor phasing (see Figure 14, positions
1, 2, 3a, 4, 5 and 6a) and six combinations are valid for rotor positions with 60 electrical
degrees phasing (see Figure 15, positions 1, 2, 3b, 4, 5 and 6b). Four of them are in
common (1, 2, 4 and 5) whereas there are two combinations used only in 120 electrical
degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical
degrees sensor phasing (3b and 6b).
The decoder can drive motors with different sensor configuration simply by following the
Ta bl e 8 . For any input configuration (H1, H2 and H3) there is one output configuration (OUT1,
OUT2 and OUT3). The output configuration 3a is the same than 3b and analogously output
configuration 6a is the same than 6b.
The sequence of the Hall codes for 300 electrical degrees phasing is the reverse of 60 and
the sequence of the Hall codes for 240 phasing is the reverse of 120. So, by decoding the 60
A) ON TIME B) 1μs DEAD TIME C) SYNCHRONOUS
RECTIFICATION
D) 1μs DEAD TIME
D01IN1336
o o g o . . . . o . o Ha H3 H2 H3 H H: H H3 H2 H3 H2 - H‘ H H H‘ H‘ o . 0 o o a . . O 0 Hz H H H2 H2 H9 H, H9
L6229Q Circuit description
Doc ID 15209 Rev 3 17/28
and the 120 codes it is possible to drive the motor with all the four conventions by changing
the direction set.
Figure 14. 120° hall sensor sequence
Figure 15. 60° hall sensor sequence
Table 8. 60 and 120 electrical degree decoding logic in forward direction
Hall 120° 1 2 3a - 4 5 6a -
Hall 60° 12 - 3b4 5-6b
H1HH L H L LHL
H2LH H HH LLL
H3LL L HHHHL
OUT1Vs High Z GND GND GND High Z Vs Vs
OUT2High Z Vs Vs Vs High Z GND GND GND
OUT3GND GND High Z High Z Vs Vs High Z High Z
Phasing 1->3 2->3 2->1 2->1 3->1 3->2 1->2 1->2
H1
H2 H2 H2 H2 H2 H3 H3 H3 H3 H3
H1 H1 H1 H1
H3 H2
H1
1 2 3a 4 5 6a
= H = L
H1 H1
H2 H2 H2 H2 H2
H3 H3 H3 H3 H3
H1 H1 H1 H1
H3
H2
1 2 3b 4 5 6b
= H = L
Circuit description L6229Q
18/28 Doc ID 15209 Rev 3
5.6 Tacho
A tachometer function consists of a monostable, with constant off time (tPULSE), whose input
is one hall effect signal (H1). It allows developing an easy speed control loop by using an
external op amp, as shown in Figure 17. For component values refer to Application
Information section.
The monostable output drives an open drain output pin (TACHO). At each rising edge of the
hall effect sensors H1, the monostable is triggered and the MOSFET connected to pin
TACHO is turned off for a constant time tPULSE (see Figure 16). The off time tPULSE can be
set using the external RC network (RPUL, CPUL) connected to the pin RCPULSE. Figure 18
gives the relation between tPULSE and CPUL, RPUL. We have approximately:
tPULSE = 0.6 · RPUL · CPUL
where CPUL should be chosen in the range 1 nF … 100 nF and RPUL in the range
20 kΩ … 100 kΩ.
By connecting the tachometer pin to an external pull-up resistor, the output signal average
value VM is proportional to the frequency of the hall effect signal and, therefore, to the motor
speed. This realizes a simple frequency-to-voltage converter. An op amp, configured as an
integrator, filters the signal and compares it with a reference voltage VREF
, which sets the
speed of the motor.
Figure 16. Tacho operation waveforms
VM
tPULSE
T
------------------ VDD
⋅=
T
tPULSE
H1
VTACHO
H2
H3
VM
VDD
PULSE cPUL PUL
L6229Q Circuit description
Doc ID 15209 Rev 3 19/28
Figure 17. Tachometer speed control loop
Figure 18. tPULSE versus CPUL and RPUL
CREF2
RPUL C
PUL
RDD
R3
R2
R1
C1
CREF1
VREF
TACHO
H1
TACHO
MONOSTABLE
RCPULSE
VDD
VREF
R4
1 10 100
10
100
1.103
1.104
Cpul [nF]
tpulse [μs]
RPUL = 100kΩ
RPUL = 47kΩ
RPUL = 20kΩ
20/28 Figure 20 shows the overcurrent delection operation. The disa recovering normal operalion can be easily programmed by me thresholds of the logic inputs. It is alfeoted whether by GEN and magnilude is reported m Figure 21. The delay tlme IDELAV befo an overcurrenl has been detected depends only by CEN value. Figure 22 GEN is also used for providing immunity 1o pin EN agalnst fast the value of CEN should be chosen as big as possible accordin delay tlme and the HEN value should be chosen The resistor REN should be chosen in the range values for HEN and CEN are respectlvely 100 kg disable lime. Doc ID 15209 Flev
Circuit description L6229Q
20/28 Doc ID 15209 Rev 3
5.7 Non-dissipative overcurrent detection and protection
The L6229Q integrates an overcurrent detection circuit (OCD) for full protection. This circuit
provides output-to-output and output-to-ground short circuit protection as well. With this
internal over current detection, the external current sense resistor normally used and its
associated power dissipation are eliminated. Figure 19 shows a simplified schematic for the
overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high side power MOS. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current IREF
. When the
output current reaches the detection threshold (typically ISOVER = 2.8 A) the OCD
comparator signals a fault condition. When a fault condition is detected, an internal open
drain MOS with a pull down capability of 4 mA connected to pin DIAG is turned on.
The pin DIAG can be used to signal the fault condition to a μC or to shut down the three-
phase bridge simply by connecting it to pin EN and adding an external R-C (see REN, CEN).
Figure 19. Overcurrent protection simplified schematic
Figure 20 shows the overcurrent detection operation. The disable time tDISABLE before
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs. It is affected whether by CEN and REN values and its
magnitude is reported in Figure 21. The delay time tDELAY before turning off the bridge when
an overcurrent has been detected depends only by CEN value. Its magnitude is reported in
Figure 22
CEN is also used for providing immunity to pin EN against fast transient noises. Therefore
the value of CEN should be chosen as big as possible according to the maximum tolerable
delay time and the REN value should be chosen according to the desired disable time.
The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended
values for REN and CEN are respectively 100 kΩ and 5.6 nF that allow obtaining 200 μs
disable time.
+
OVER TEMPERATURE
IREF
IREF
I1+I2 / n
I1 / n
HIGH SIDE DMOS
POWER SENSE
1 cell POWER SENSE
1 cell
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
POWER DMOS
n cells
HIGH SIDE DMOS HIGH SIDE DMOS
OUT1OUT2
VSA OUT3VSB
I1I2I3
I2/ n
I3/ n
OCD
COMPARATOR
TO GATE
LOGIC
INTERNAL
OPEN-DRAIN
RDS(ON)
40Ω TYP.
CEN
REN
DIAG
EN
VDD
μC or LOGIC
D02IN1381
EN EN DISABLE 134.54.... ‘DELAV versus EN Figure 22.
L6229Q Circuit description
Doc ID 15209 Rev 3 21/28
Figure 20. Overcurrent protection waveforms
Figure 21. tDISABLE versus CEN and REN
Figure 22. tDELAY versus CEN.
I
SOVER
I
OUT
V
th(ON)
V
th(OFF)
V
EN(LOW)
V
DD
t
OCD(ON)
t
D(ON)EN
t
EN(FALL)
t
EN(RISE)
t
DISABLE
t
DELAY
t
OCD(OFF)
t
D(OFF)EN
V
EN
=V
DIAG
BRIDGE
ON
OFF
OCD
ON
OFF
D02IN1383
1 10 100
1
10
100
1.103
CEN [nF]
tDISABLE [µs]
REN = 220 kΩREN = 100 kΩREN = 47 kΩ
REN = 33 kΩ
REN = 10 kΩ
1 10 100
1
10
100
1.103
CEN [nF]
tDISABLE [µs]
REN = 220 kΩREN = 100 kΩREN = 47 kΩ
REN = 33 kΩ
REN = 10 kΩ
110100
0.1
1
10
Cen [nF]
tdelay [μs]
Application information L6229Q
22/28 Doc ID 15209 Rev 3
6 Application information
A typical application using L6229Q is shown in Figure 23. Typical component values for the
application are shown in Ta b l e 9 . A high quality ceramic capacitor (C2) in the range of
100 nF to 200 nF should be placed between the power pins VSA and VSB and ground near
the L6229Q to improve the high frequency filtering on the power supply and reduce high
frequency transients generated by the switching. The capacitor (CEN) connected from the
EN input to ground sets the shut down time when an over current is detected (see
overcurrent protection). The two current sensing inputs (SENSEA and SENSEB) should be
connected to the sensing resistor RSENSE with a trace length as short as possible in the
layout. The sense resistor should be non-inductive resistor to minimize the dI/dt transients
across the resistor. To increase noise immunity, unused logic pins are best connected to 5 V
(high logic level) or GND (low logic level) (see pin description). It is recommended to keep
power ground and signal ground separated on PCB.
Table 9. Component values for typical application
Component Value
C1100 µF
C2100 nF
C3220 nF
CBOOT 220 nF
COFF 1 nF
CPUL 10 nF
CREF1 33 nF
CREF2 100 nF
CEN 5.6 nF
CP10 nF
D11N4148
D21N4148
R15 k6Ω
R21 k8Ω
R34 k7Ω
R41 MΩ
RDD 1 kΩ
REN 100 kΩ
RSENSE 0.6 Ω
ROFF 33 kΩ
RPUL 47 kΩ
RH1, RH2, RH3 10 kΩ
6.1 flflflflflflfl'fl Hi Output current capability and ic power dissipation In Figure 24 is shown the approximate relation between the output current and the IC power dissipation using PWM current control. For a given output current the power dissipated by the IC can be easily evaluated, in orderto establish which package should be used and how large must be the onboard copper dissipating area to guarantee a safe operating junction temperature (125 °C maximum). Figure 24. IC power dissipation versus output power Doc ID 15209 Flev 3
L6229Q Application information
Doc ID 15209 Rev 3 23/28
Figure 23. Typical application
6.1 Output current capability and ic power dissipation
In Figure 24 is shown the approximate relation between the output current and the IC power
dissipation using PWM current control.
For a given output current the power dissipated by the IC can be easily evaluated, in order to
establish which package should be used and how large must be the on-board copper
dissipating area to guarantee a safe operating junction temperature (125 °C maximum).
Figure 24. IC power dissipation versus output power
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 10111213141516
32 31 30 29 28 27 26 25
GND
NC
H1 H2 H3
H1 H2H3
NC
NC
NC
NC
NC
NC
BRAKE
FWD/REW
Cp
D1D2
Vs
8 ÷ 52 VDC
POWER
GROUND
SIGNAL
GROUND
+
_
M
COFF
ROFF
CPUL
RPUL
C3
R4
R2
R3RDD
RSENSE
ENABLE
CREF1 CREF1
REN
R1
CEN
VREF
Cboot
C1C2
TACHO
NC
RCPULSE
FW/REW
EN
VREF
BRAKE
SENSEB
VCP
OUT2
VSA
GND
VSB
OUT3
NC
VBOOT
NC
OUT1
RCOFF
DIAG
H1
H3
H2
SENSEA
to SENSEBto EN
HALL
SENSOR
THREE-PHASE MOTOR
RH1
RH2
RH3
+5V
+5V
No PWM
f
SW
= 30 kHz (slow decay)
Test Conditions:
Supply Voltage = 24 V
0 0.25 0.5 0.75 1 1.25 1.5
0
2
4
6
8
10
P
I
OUT
[A]
D [W]
I
OUT
I1
I3
I2 I
OUT
I
OUT
Application information L6229Q
24/28 Doc ID 15209 Rev 3
6.2 Thermal management
In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Therefore, it has to
be taken into account very carefully. Besides the available space on the PCB, the right
package should be chosen considering the power dissipation. Heat sinking can be achieved
using copper on the PCB with proper area and thickness.
For instance, using a VFQFPN32L 5 x 5 package the typical Rth(JA) is about 42 °C/W when
mounted on a double-layer FR4 PCB with a dissipating copper area of 0.5 cm2 on the top
side plus 6 cm2 ground layer connected through 18 via holes (9 below the IC).
L6229Q Package mechanical data
Doc ID 15209 Rev 3 25/28
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Note: VFQFPN stands for thermally enhanced very thin profile fine pitch quad flat package no
lead. Very thin profile: 0.80 < A < 1.00 mm.
Details of terminal 1 are optional but must be located on the top surface of the package by
using either a mold or marked features.
Table 10. VFQFPN 5 x 5 x 1.0, 32 lead, pitch 0.50
Dim.
Databook (mm)
Min Typ Max
A 0.80 0.85 0.95
b 0.18 0.25 0.30
b1 0.165 0.175 0.185
D 4.85 5.00 5.15
D2 3.00 3.10 3.20
D3 1.10 1.20 1.30
E 4.85 5.00 5.15
E2 4.20 4.30 4.40
E3 0.60 0.70 0.80
e0.50
L 0.30 0.40 0.50
ddd 0.08
“/FQFPN SXSXWO 32L F‘TCH 0. B (UTAC Thai SU3C0\.) Specim deswqm fi SEATMG PLANE m D C, 5 <7 ‘7="" 24="" b="" u)="" u="" u="" j="" u="" u="" u="" u="" 4="" ‘="" e="" "r="" m="" £="" 3="" e="" ’="" 1::="" c="" d="" c="" j="" j="" +="" l="" m="" 3="" c="" d="" c="" a)="" c32="" 4="" m="" c="" j="" m="" m="" m="" h="" 4‘="" 5="" b1="" 1="" ’="" b1="" i="" a}?="" a="" k="" b="" l="" d3="" d2="" h="" bowom="" wew="">
Package mechanical data L6229Q
26/28 Doc ID 15209 Rev 3
Figure 25. Package dimensions
L6229Q Revision history
Doc ID 15209 Rev 3 27/28
8 Revision history
Table 11. Document revision history
Date Revision Changes
25-Nov-2008 1 First release
26-Feb-2009 2 Updated Table 4 on page 5
30-Aug-2010 3 Updated Table 1 on page 1
L6229Q
28/28 Doc ID 15209 Rev 3
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