Datenblatt für CSD16340Q3 von Texas Instruments

X w TEXAS INSTRUMENTS 3233 3236
VGS − Gate to Source Voltage − V
0
2
4
6
8
10
12
14
16
0 3 4 7 8 9 10
RDS(on) − On-State Resistance − mW
G006
5 61 2
ID= 20A
TC= 125 C°
TC= 25 C°
Qg − GateCharge − nC
0
1
4
7
0 2 4 6 8 10 12
VG− GateVoltage − V
G003
3
2
5
6
8
ID=20A
V =12.5V
DS
1D
2D
3D
4
D
D
5
G
6S
7
S
8S
P0095-01
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CSD16340Q3
SLPS247E –DECEMBER 2009–REVISED AUGUST 2014
CSD16340Q3 25-V N-Channel NexFET™ Power MOSFET
1 Features Product Summary
1• Optimized for 5 V Gate Drive TA= 25°C VALUE UNIT
• Resistance Rated at VGS =2.5 V VDS Drain-to-Source Voltage 25 V
• Ultra-Low Qgand Qgd QgGate Charge Total (4.5 V) 6.5 nC
Qgd Gate Charge Gate-to-Drain 1.2 nC
• Low Thermal Resistance
VGS = 2.5 V 6.1 mΩ
• Avalanche Rated RDS(on) Drain-to-Source On-Resistance VGS = 4.5 V 4.3 mΩ
• Pb Free Terminal Plating VGS = 8 V 3.8 mΩ
• RoHS Compliant Vth Threshold Voltage 0.85 V
• Halogen Free
• SON 3.3-mm × 3.3-mm Plastic Package .
Ordering Information(1)
2 Applications Device Media Qty Package Ship
CSD16340Q3 13-Inch Reel 2500 SON 3.3 x 3.3 mm Tape and
• Point of Load Synchronous Buck Converter for Plastic Package Reel
CSD16340Q3T 7-Inch Reel 250
Applications in Networking, Telecom, and
Computing Systems (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Optimized for Control or Synchronous FET
Applications Absolute Maximum Ratings
TA= 25°C VALUE UNIT
3 Description VDS Drain-to-Source Voltage 25 V
This 25 V, 3.8 mΩ, 3.3 × 3.3 mm SON NexFET™ VGS Gate-to-Source Voltage +10 / –8 V
power MOSFET is designed to minimize losses in Continuous Drain Current, TC= 25°C 60 A
power conversion and optimized for 5 V gate drive IDContinuous Drain Current(1) 21 A
applications. IDM Pulsed Drain Current, TA= 25°C(2) 115 A
PDPower Dissipation(1) 3 W
Top View
TJ, Operating Junction and –55 to 150 °C
Tstg Storage Temperature Range
Avalanche Energy, single pulse
EAS 80 mJ
ID= 40 A, L = 0.1 mH, RG= 25 Ω
(1) Typical RθJA = 39°C/W on 1in2Cu (2 oz.) on 0.060" thick FR4
PCB.
(2) Pulse width ≤300 μs, duty cycle ≤2%
RDS(on) vs VGS Gate Charge
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
l TEXAS INSTRUMENTS
CSD16340Q3
SLPS247E –DECEMBER 2009–REVISED AUGUST 2014
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Table of Contents
6.1 Trademarks............................................................... 8
1 Features.................................................................. 16.2 Electrostatic Discharge Caution................................ 8
2 Applications ........................................................... 16.3 Glossary.................................................................... 8
3 Description ............................................................. 17 Mechanical, Packaging, and Orderable
4 Revision History..................................................... 2Information ............................................................. 9
5 Specifications......................................................... 37.1 Q3 Package Dimensions .......................................... 9
5.1 Electrical Characteristics........................................... 37.2 Recommended PCB Pattern................................... 10
5.2 Thermal Information.................................................. 47.3 Recommended Stencil Opening ............................. 10
5.3 Typical MOSFET Characteristics.............................. 57.4 Q3 Tape and Reel Information................................ 11
6 Device and Documentation Support.................... 8
4 Revision History
Changes from Revision D (November 2011) to Revision E Page
• Added 7" reel to Ordering Information ................................................................................................................................... 1
• Updated Mechanical Information ........................................................................................................................................... 9
Changes from Revision C (June 2011) to Revision D Page
• Replaced the THERMAL CHARACTERISTICS table with the new Thermal Information Table............................................ 4
• Replaced Figure 10 - Maximum Safe Operating Area ........................................................................................................... 6
Changes from Revision B (September 2010) to Revision C Page
• Deleted the Package Marking Information section ................................................................................................................ 9
Changes from Revision A (January 2010) to Revision B Page
• Changed Figure 2, reversed the order of the VGS labels........................................................................................................ 5
Changes from Original (December 2009) to Revision A Page
• Changed Qgin the PRODUCT SUMMARY table from: 6.8 To 6.5 nC .................................................................................. 1
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SLPS247E –DECEMBER 2009–REVISED AUGUST 2014
5 Specifications
5.1 Electrical Characteristics
(TA= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = 250 μA 25 V
IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 20 V 1 μA
IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = +10/–8 V 100 nA
VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = 250 μA 0.6 0.85 1.1 V
VGS = 2.5 V, IDS = 20 A 6.1 7.8 mΩ
RDS(on) Drain-to-Source On-Resistance VGS = 4.5 V, IDS = 20 A 4.3 5.5 mΩ
VGS = 8 V, IDS = 20 A 3.8 4.5 mΩ
gƒs Transconductance VDS = 15 V, IDS = 20 A 121 S
DYNAMIC CHARACTERISTICS
CISS Input Capacitance 1050 1350 pF
COSS Output Capacitance VGS = 0 V, VDS = 12.5 V, ƒ = 1 MHz 730 950 pF
CRSS Reverse Transfer Capacitance 53 69 pF
RgSeries Gate Resistance 1.5 3 Ω
QgGate Charge Total (4.5 V) 6.5 9.2 nC
Qgd Gate Charge Gate-to-Drain 1.2 nC
VDS = 12.5 V, ID= 20 A
Qgs Gate Charge Gate-to-Source 2.1 nC
Qg(th) Gate Charge at Vth 1 nC
QOSS Output Charge VDS = 13 V, VGS = 0 V 15 nC
td(on) Turn On Delay Time 4.8 ns
trRise Time 16.1 ns
VDS = 12.5 V, VGS = 4.5 V, ID= 20 A
RG= 2 Ω
td(off) Turn Off Delay Time 13.8 ns
tƒFall Time 5.2 ns
DIODE CHARACTERISTICS
VSD Diode Forward Voltage IS= 20 A, VGS = 0 V 0.8 1 V
Qrr Reverse Recovery Charge 14.5 nC
VDD = 13 V, IF= 20 A, di/dt = 300 A/μs
trr Reverse Recovery Time 20 ns
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l TEXAS INSTRUMENTS /\ \/ 5A1: gm“? (N am. Smut? E
GATE Source
DRAIN
M0161-01
GATE Source
DRAIN
M0161-02
CSD16340Q3
SLPS247E –DECEMBER 2009–REVISED AUGUST 2014
www.ti.com
5.2 Thermal Information
CSD16340Q3
THERMAL METRIC(1)(2) UNITS
Q3 (8 PINS)
θJA Junction-to-Ambient Thermal Resistance 42.0
θJCtop Junction-to-Case (top) Thermal Resistance 20.6
θJB Junction-to-Board Thermal Resistance 8.8 °C/W
ψJT Junction-to-Top Characterization Parameter 0.3
ψJB Junction-to-Board Characterization Parameter 8.7
θJCbot Junction-to-Case (bottom) Thermal Resistance 0.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
Max RθJA = 162°C/W
Max RθJA = 58°C/W when mounted on
when mounted on minimum pad area of
1 inch2of 2 oz. Cu. 2 oz. Cu.
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l TEXAS INSTRUMENTS sz Gum am
VGS − Gate to Source Voltage − V
5
15
25
35
40
45
1.71.1 1.3 1.5 2.1
ID− Drain Current − A
G002
50
0.7 0.9 1.9
VDS = 5V
0
10
20
30
TC= −55 C°
TC= 125 C°
TC= 25 C°
tP– PulseDuration–s
ZqJA – NormalizedThermalImpedance
G012
0.01
0.1
10
1
0.001
0.01 0.1 1 10 1000.001 1k
0.1
0.05
0.01
0.5
0.02
0.3
SinglePulse
DutyCycle=t /t
1 2
TypicalR JAq=138 C/W(minCu)
o
TJ=P xZq qJA JA
xR
t1
t2
P
CSD16340Q3
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SLPS247E –DECEMBER 2009–REVISED AUGUST 2014
5.3 Typical MOSFET Characteristics
(TA= 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics
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l TEXAS INSTRUMENTS Gnu: mm can: Gum Gnn7 Gncz
0.0 0.2 0.4 0.6 0.8 1.0
VSD − Source to Drain Voltage − V
ISD − Source to Drain Current − A
G008
100
1
0.01
0.0001
0.001
0.1
10
TC= 125 C°
TC= 25 C°
TC− Case Temperature − C°
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
−75 −25 25 75 125 175
NormalizedOn-StateResistance
G007
ID
GS
=20A
V =4.5V
TC− Case Temperature − C°
0.0
0.2
0.4
0.6
0.8
1.0
1.2
−75 −25 25 75 125 175
VGS(th) − ThresholdVoltage − V
G005
ID=250 Am
VGS − Gate to Source Voltage − V
0
2
4
6
8
10
12
14
16
0 3 4 7 8 9 10
RDS(on) − On-State Resistance − mW
G006
5 61 2
ID= 20A
TC= 125 C°
TC= 25 C°
Qg − GateCharge − nC
0
1
4
7
0 2 4 6 8 10 12
VG− GateVoltage − V
G003
3
2
5
6
8
ID=20A
V =12.5V
DS
CSD16340Q3
SLPS247E –DECEMBER 2009–REVISED AUGUST 2014
www.ti.com
Typical MOSFET Characteristics (continued)
(TA= 25°C unless otherwise stated)
Figure 4. Gate Charge Figure 5. Capacitance
Figure 6. Threshold Voltage vs Temperature Figure 7. On-Resistance vs Gate Voltage
Figure 8. Normalized On Resistance vs Temperature Figure 9. Typical Diode Forward Voltage
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l TEXAS INSTRUMENTS Vn: DraerrSumce Vanaae , v Emu Gnu
TC− Case Temperature − C°
0
10
20
30
40
50
60
70
−50 −25 0 25 50 75 100 125 150 175
ID− DrainCurrent − A
G011
80
t(AV) − Timein Avalanche − ms G010
1k
10
1
100
I(AV) − Peak AvalancheCurrent − A
0.01 0.1 10 1001
TC=25 C°
TC=125 C°
0.01
0.1
1
10
100
1000
0.01 0.1 1 10 100
VDS - Drain-to-Source Voltage - V
IDS - Drain-to-Source Current - A
1ms
10ms 100ms
1s DC
Single Pulse
Typical RthetaJA = 138ºC/W(min Cu)
Area Limited
by Rds(on)
G001
CSD16340Q3
www.ti.com
SLPS247E –DECEMBER 2009–REVISED AUGUST 2014
Typical MOSFET Characteristics (continued)
(TA= 25°C unless otherwise stated)
Figure 11. Single Pulse Unclamped Inductive Switching
Figure 10. Maximum Safe Operating Area
Figure 12. Maximum Drain Current vs Temperature
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SLPS247E –DECEMBER 2009–REVISED AUGUST 2014
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6 Device and Documentation Support
6.1 Trademarks
NexFET is a trademark of Texas Instruments.
6.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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CSD16340Q3
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SLPS247E –DECEMBER 2009–REVISED AUGUST 2014
7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q3 Package Dimensions
MILLIMETERS INCHES
DIM MIN NOM MAX MIN NOM MAX
A 0.950 1.000 1.100 0.037 0.039 0.043
A1 0.000 0.000 0.050 0.000 0.000 0.002
b 0.280 0.340 0.400 0.011 0.013 0.016
b1 0.310 NOM 0.012 NOM
c 0.150 0.200 0.250 0.006 0.008 0.010
D 3.200 3.300 3.400 0.126 0.130 0.134
D2 1.650 1.750 1.800 0.065 0.069 0.071
d 0.150 0.200 0.250 0.006 0.008 0.010
d1 0.300 0.350 0.400 0.012 0.014 0.016
E 3.200 3.300 3.400 0.126 0.130 0.134
E2 2.350 2.450 2.550 0.093 0.096 0.100
e 0.650 TYP 0.026
H 0.35 0.450 0.550 0.014 0.018 0.022
K 0.650 TYP 0.026 TYP
L 0.35 0.450 0.550 0.014 0.018 0.022
L1 0 — 0 0 — 0
θ0 — 0 0 — 0
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l TEXAS INSTRUMENTS 27122541 —-I F; 0150003) Ll m U $0410 171.9004» 3 500 :I 0.560 0 630 0.500 {X a) 4» 4-1.020-D [X 2) '71 K 3 C7. «0.340 (x a) 1 0.450 L 0.22;— 3 320 4—1AA5—> ? B 0750 I 0310(x6) ,| ,7DD JL
CSD16340Q3
SLPS247E –DECEMBER 2009–REVISED AUGUST 2014
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7.2 Recommended PCB Pattern
For recommended circuit layout for PCB designs, see application note SLPA005 –Reducing Ringing Through
PCB Layout Techniques.
7.3 Recommended Stencil Opening
All dimensions are in mm, unless otherwise specified.
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4.00 ±0.10 (See Note 1) 2.00 ±0.05
3.60
3.60
1.30
1.75 ±0.10
M0144-01
8.00 ±0.10
12.00 +0.30
–0.10
5.50 ±0.05
Ø 1.50 +0.10
–0.00
CSD16340Q3
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SLPS247E –DECEMBER 2009–REVISED AUGUST 2014
7.4 Q3 Tape and Reel Information
Notes:
1. 10 sprocket hole pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material: black static dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified).
5. Thickness: 0.30 ±0.05 mm
6. MSL1 260°C (IR and Convection) PbF-Reflow Compatible
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CSD16340Q3 ACTIVE VSON-CLIP DQG 8 2500 RoHS-Exempt
& Green SN Level-1-260C-UNLIM -55 to 150 CSD16340
CSD16340Q3T ACTIVE VSON-CLIP DQG 8 250 RoHS-Exempt
& Green SN Level-1-260C-UNLIM -55 to 150 CSD16340
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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Addendum-Page 2
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