Datenblatt für CSD86330Q3D von Texas Instruments

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Output Current (A)
Efficiency (%)
Power Loss (W)
0 5 10 15 20
50 0
60 1
70 2
80 3
90 4
100 5
G029
VGS = 5V
VIN = 12V
VOUT = 1.3V
fSW = 500kHz
LOUT = 1µH
TA = 25°C
Efficiency
Power Loss
G1R
D1
S2
D /S
2 1
G1
G2
S0474-04
ENABLE
ENABLE
PWM
GND
BST
DRVH
LL
DRVL
CSD86330Q3D
Driver IC
VDD VI
VO
VDD
Control
FET
Sync
FET
PWM
P0116-01
1
2
3VSW
VSW
VSW
4BG
5
TGR
6
TG
PGND
(Pin9)
7
VIN
8
VIN
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CSD86330Q3D
SLPS264D –OCTOBER 2010–REVISED MAY 2015
CSD86330Q3D Synchronous Buck NexFET™ Power Block
1 Features 3 Description
The CSD86330Q3D NexFET™ power block is an
1• Half-Bridge Power Block optimized design for synchronous buck applications
• 90% System Efficiency at 15 A offering high current, high efficiency, and high
• Up to 20 A Operation frequency capability in a small 3.3 mm × 3.3 mm
outline. Optimized for 5 V gate drive applications, this
• High Frequency Operation (Up To 1.5 MHz) product offers a flexible solution capable of offering a
• High Density – SON 3.3 mm × 3.3 mm Footprint high density power supply when paired with any 5 V
• Optimized for 5 V Gate Drive gate drive from an external controller/driver.
• Low Switching Losses TEXT ADDED FOR SPACING
• Ultra Low Inductance Package Top View
• RoHS Compliant
• Halogen Free
• Pb-Free Terminal Plating
2 Applications
• Synchronous Buck Converters
– High Frequency Applications
– High Current, Low Duty Cycle Applications TEXT ADDED FOR SPACING
Ordering Information(1)
• Multiphase Synchronous Buck Converters Device Media Qty Package Ship
• POL DC-DC Converters 13-Inch
CSD86330Q3D 2500
• IMVP, VRM, and VRD Applications Reel SON 3.3 mm × 3.3 mm Tape and
Plastic Package Reel
7-Inch
CSD86330Q3DT 250
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Added text for spacing
Added text for spacing
Added text for spacing
Added text for spacing
RDS(on) vs VGS Gate Charge
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
l TEXAS INSTRUMENTS
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SLPS264D –OCTOBER 2010–REVISED MAY 2015
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Table of Contents
6.3 Safe Operating Curves (SOA) ................................ 12
1 Features.................................................................. 16.4 Normalized Curves.................................................. 12
2 Applications ........................................................... 16.5 Calculating Power Loss and SOA .......................... 14
3 Description ............................................................. 17 Recommended PCB Design Overview .............. 15
4 Revision History..................................................... 27.1 Electrical Performance............................................ 15
5 Specifications......................................................... 37.2 Thermal Performance ............................................. 15
5.1 Absolute Maximum Ratings ...................................... 38 Device and Documentation Support.................. 17
5.2 Recommended Operating Conditions....................... 38.1 Trademarks............................................................. 17
5.3 Thermal Information.................................................. 38.2 Electrostatic Discharge Caution.............................. 17
5.4 Power Block Performance ........................................ 38.3 Glossary.................................................................. 17
5.5 Electrical Characteristics........................................... 49 Mechanical, Packaging, and Orderable
5.6 Typical Power Block Device Characteristics............. 5Information ........................................................... 18
5.7 Typical Power Block MOSFET Characteristics......... 79.1 Q3D Package Dimensions...................................... 18
6 Application and Implementation ........................ 10 9.2 Land Pattern Recommendation .............................. 19
6.1 Application Information............................................ 10 9.3 Stencil Recommendation ........................................ 19
6.2 Power Loss Curves ................................................ 12 9.4 Q3D Tape and Reel Information............................. 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2011) to Revision D Page
• Corrected 125°C line in Figure 20 to agree with data in Figure 22 ....................................................................................... 8
• Corrected 125°C line in Figure 21 to agree with data in Figure 23 ....................................................................................... 8
Changes from Revision B (September 2011) to Revision C Page
• Changed "DIM A" Millimeter Max value From: 1.55 To: 1.5 and Inches Max value From: 0.061 To: 0.059 ....................... 18
Changes from Revision A (December 2010) to Revision B Page
• Change RDS(on) to ZDS(on) ......................................................................................................................................................... 4
• Added Equivalent System Performance section .................................................................................................................. 10
• Added Electrical Performance bullet .................................................................................................................................... 15
Changes from Original (October 2010) to Revision A Page
• Changed IOUT Conditions From: 20A To: 15A, and the TYP value From: 2.9W To: 1.9W..................................................... 3
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SLPS264D –OCTOBER 2010–REVISED MAY 2015
5 Specifications
5.1 Absolute Maximum Ratings
TA= 25°C (unless otherwise noted)(1)
MIN MAX UNIT
VIN to PGND –0.8 25 V
Voltage range TGto TGR –8 10 V
BGto PGND –8 10 V
Pulsed Current Rating, IDM 60 A
Power Dissipation, PD6 W
Sync FET, ID= 65 A, L = 0.1 mH 211
Avalanche Energy EAS mJ
Control FET, ID= 42 A, L = 0.1 mH 88
Operating junction, TJ–55 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
5.2 Recommended Operating Conditions
TA= 25° (unless otherwise noted)
MIN MAX UNIT
Gate drive voltage, VGS 4.5 8 V
Input supply voltage, VIN 22 V
Switching frequency, fSW CBST = 0.1 µF (min) 200 1500 kHz
Operating current 20 A
Operating temperature, TJ125 °C
5.3 Thermal Information
TA= 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
Junction-to-ambient thermal resistance (Min Cu)(1) 135
RθJA Junction-to-ambient thermal resistance (Max Cu)(1)(2) 73 °C/W
Junction-to-case thermal resistance (Top of package)(1) 29
RθJC Junction-to-case thermal resistance (PGND Pin)(1) 2.5
(1) RθJC is determined with the device mounted on a 1 inch2(6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches× 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
(2) Device mounted on FR4 material with 1 inch2(6.45 cm2) Cu.
5.4 Power Block Performance
TA= 25° (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 15 A,
Power Loss, PLOSS(1) 1.9 W
fSW = 500 kHz,
LOUT = 1 µH, TJ= 25ºC
TGto TGR = 0 V
VIN Quiescent Current, IQVIN 10 µA
BGto PGND = 0 V
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high current 5 V driver IC.
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CSD86330Q3D
SLPS264D –OCTOBER 2010–REVISED MAY 2015
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5.5 Electrical Characteristics
TA= 25°C (unless otherwise stated)
Q1 Control FET Q2 Sync FET UNIT
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX
STATIC CHARACTERISTICS
BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = 250 µA 25 25 V
Drain-to-Source Leakage
IDSS VGS = 0 V, VDS = 20 V 1 1 µA
Current
Gate-to-Source Leakage
IGSS VDS = 0 V, VGS = +10 / –8 100 100 nA
Current
Gate-to-Source Threshold
VGS(th) VDS = VGS, IDS = 250 µA 0.9 1.4 2.1 0.9 1.1 1.6 V
Voltage
VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 15 A,
ZDS(on) Effective AC On-Impedance 8.8 3.3 mΩ
ƒSW = 500 kHz,
LOUT = 1 µH
gƒs Transconductance VDS = 15 V, IDS = 14 A 52 82 S
DYNAMIC CHARACTERISTICS
CISS Input Capacitance(1) 710 920 1280 1660 pF
COSS Output Capacitance(1) VGS = 0 V, VDS = 12.5 V, 350 455 680 880 pF
ƒ = 1 MHz
Reverse Transfer
CRSS 18 23 38 49 pF
Capacitance(1)
RGSeries Gate Resistance(1) 1.5 3.0 1.2 2.4 Ω
QgGate Charge Total (4.5 V)(1) 4.8 6.2 9.2 12 nC
Qgd Gate Charge - Gate-to-Drain 0.9 1.6 nC
VDS = 12.5 V,
Gate Charge - Gate-to- IDS = 14 A
Qgs 1.6 2.1 nC
Source
Qg(th) Gate Charge at Vth 0.9 1.2 nC
QOSS Output Charge VDS = 15.5 V, VGS = 0 V 7.2 13.6 nC
td(on) Turn On Delay Time 4.9 5.3 ns
trRise Time 7.5 6.3 ns
VDS = 12.5 V, VGS = 4.5 V,
IDS = 14 A, RG= 2 Ω
td(off) Turn Off Delay Time 8.5 15.8 ns
tƒFall Time 1.9 4.2 ns
DIODE CHARACTERISTICS
VSD Diode Forward Voltage IDS = 14 A, VGS = 0 V 0.85 1 0.8 1 V
Qrr Reverse Recovery Charge 3.9 7.3 nC
Vdd = 15.5 V, IF= 14 A,
di/dt = 300 A/µs
trr Reverse Recovery Time 13.9 19 ns
(1) Specified by design
Max RθJA = 76°C/W Max RθJA = 140°C/W
when mounted on when mounted on
1 inch2(6.45 cm2) of minimum pad area of
2 oz. (0.071 mm thick) 2 oz. (0.071 mm thick)
Cu. Cu.
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Ambient Temperature (°C)
Output Current (A)
0 10 20 30 40 50 60 70 80 90
0
5
10
15
20
25
G004
400LFM
200LFM
100LFM
Nat Conv
Output Current (A)
Power Loss (W)
0 2 4 6 8 10 12 14 16 18 20
0
0.5
1
1.5
2
2.5
3
3.5
4
G001
Junction Temperature (°C)
Power Loss, Normalized
-50 -25 0 25 50 75 100 125 150
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
G002
CSD86330Q3D
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SLPS264D –OCTOBER 2010–REVISED MAY 2015
5.6 Typical Power Block Device Characteristics
VIN = 12 V, VDD = 5 V, ƒSW = 500 kHz, VOUT = 1.2 V, LOUT = 1.0 µH, IOUT = 20 A, TJ= 125°C, unless stated otherwise.
Figure 1. Power Loss vs Output Current Figure 2. Power Loss vs Temperature
Figure 3. Safe Operating Area – PCB Vertical Mount(1) Figure 4. Safe Operating Area – PCB Horizontal Mount(1)
(1) The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with
dimensions of 4.0” (W) × 3.5” (L) × 0.062” (H) and 6 copper layers of 1 oz. copper thickness. See Application Section
for detailed explanation.
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Output Voltage (V)
Power Loss, Normalized
0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
-10.5
-7.9
-5.2
-2.6
0
2.6
5.2
7.9
10.5
13.1
15.7
G008
SOA Temperature Adj (°C)
Output Inductance (µH)
Power Loss, Normalized
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
-10.5
-7.9
-5.2
-2.6
0
2.6
5.2
7.9
10.5
13.1
15.7
G009
SOA Temperature Adj (°C)
Switching Frequency (kHz)
Power Loss, Normalized
200 400 600 800 1000 1200 1400 1600
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
-10.5
-7.9
-5.2
-2.6
0
2.6
5.2
7.9
10.5
13.1
15.7
G006
SOA Temperature Adj (°C)
Input Voltage (V)
Power Loss, Normalized
3 6 9 12 15 18 21 24
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
-10.5
-7.8
-5.2
-2.6
0
2.6
5.2
7.8
10.5
13.1
15.7
G007
SOA Temperature Adj (°C)
Board Temperature (°C)
Output Current (A)
0 20 40 60 80 100 120 140
0
5
10
15
20
25
G005
CSD86330Q3D
SLPS264D –OCTOBER 2010–REVISED MAY 2015
www.ti.com
Typical Power Block Device Characteristics (continued)
VIN = 12 V, VDD = 5 V, ƒSW = 500 kHz, VOUT = 1.2 V, LOUT = 1.0 µH, IOUT = 20 A, TJ= 125°C, unless stated otherwise.
Figure 5. Typical Safe Operating Area(1)
Figure 6. Normalized Power Loss vs Switching Frequency Figure 7. Normalized Power Loss vs Input Voltage
Figure 8. Normalized Power Loss vs Output Voltage Figure 9. Normalized Power Loss vs Output Inductance
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l TEXAS INSTRUMENTS EU 60 m ecu 100 100 mu m 8 8 Gnu m
Qg - Gate Charge - nC
VGS - Gate-to-Source Voltage - V
0 2 4 6 8
0
1
2
3
4
5
6
7
8
G014
ID = 14A
VDS = 12.5V
Qg - Gate Charge - nC
VGS - Gate-to-Source Voltage - V
0 3 6 9 12 15
0
1
2
3
4
5
6
7
8
G015
ID = 14A
VDS = 12.5V
VGS - Gate-to-Source Voltage - V
IDS - Drain-to-Source Current - A
1 1.5 2 2.5 3 3.5
0.001
0.01
0.1
1
10
100
TC = -55°C
TC = 25°C
TC = 125°C
G012
VDS = 5V
VGS - Gate-to-Source Voltage - V
IDS - Drain-to-Source Current - A
0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
0.001
0.01
0.1
1
10
100
TC = -55°C
TC = 25°C
TC = 125°C
G013
VDS = 5V
VDS - Drain-to-Source Voltage - V
IDS - Drain-to-Source Current - A
0 0.2 0.4 0.6 0.8 1
0
10
20
30
40
50
60
VGS = 4.5V
VGS = 6V
VGS = 8V
G010
VDS - Drain-to-Source Voltage - V
IDS - Drain-to-Source Current - A
0 0.05 0.1 0.15 0.2 0.25 0.3
0
10
20
30
40
50
60
VGS = 4.5V
VGS = 6V
VGS = 8V
G011
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SLPS264D –OCTOBER 2010–REVISED MAY 2015
5.7 Typical Power Block MOSFET Characteristics
TA= 25°C, unless stated otherwise.
Figure 10. Control MOSFET Saturation Figure 11. Sync MOSFET Saturation
Figure 12. Control MOSFET Transfer Figure 13. Sync MOSFET Transfer
Figure 14. Control MOSFET Gate Charge Figure 15. Sync MOSFET Gate Charge
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0
5
10
15
20
25
0 1 2 3 4 5 6 7 8 9 10
VGS - Gate-to- Source Voltage - V
RDS(on) - On-State Resistance - mΩ
TC = 25°C, I D = 14A
TC = 125°C, I D = 14A
G001
0
2
4
6
8
10
12
14
16
0 1 2 3 4 5 6 7 8 9 10
VGS - Gate-to- Source Voltage - V
RDS(on) - On-State Resistance - mΩ
TC = 25°C, I D = 14A
TC = 125°C, I D = 14A
G001
TC - Case Temperature - °C
VGS(th) - Threshold Voltage - V
-75 -25 25 75 125 175
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
G018
ID = 250µA
TC - Case Temperature - °C
VGS(th) - Threshold Voltage - V
-75 -25 25 75 125 175
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
G019
ID = 250µA
VDS - Drain-to-Source Voltage - V
C - Capacitance - nF
0 5 10 15 20 25
0.001
0.01
0.1
1
10
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
G016
f = 1MHz
VGS = 0V
VDS - Drain-to-Source Voltage - V
C - Capacitance - nF
0 5 10 15 20 25
0.01
0.1
1
10
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
G017
f = 1MHz
VGS = 0V
CSD86330Q3D
SLPS264D –OCTOBER 2010–REVISED MAY 2015
www.ti.com
Typical Power Block MOSFET Characteristics (continued)
TA= 25°C, unless stated otherwise.
Figure 16. Control MOSFET Capacitance Figure 17. Sync MOSFET Capacitance
Figure 18. Control MOSFET VGS(th) Figure 19. Sync MOSFET VGS(th)
Figure 20. Control MOSFET RDS(on) vs VGS Figure 21. Sync MOSFET RDS(on) vs VGS
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t(AV) - Time in Avalanche - ms
I(AV) - Peak Avalanche Current - A
0.01 0.1 1 10
1
10
100
TC = 25°C
TC = 125°C
G026
I(AV) = t(AV) ÷ (0.021 × L)
t(AV) - Time in Avalanche - ms
I(AV) - Peak Avalanche Current - A
0.01 0.1 1 10
1
10
100
TC = 25°C
TC = 125°C
G027
I(AV) = t(AV) ÷ (0.021 × L)
VSD - Source-to-Drain Voltage - V
ISD - Source-to-Drain Current - A
0 0.2 0.4 0.6 0.8 1 1.2
0.0001
0.001
0.01
0.1
1
10
100
TC = 25°C
TC = 125°C
G024
VSD - Source-to-Drain Voltage - V
ISD - Source-to-Drain Current - A
0 0.2 0.4 0.6 0.8 1 1.2
0.0001
0.001
0.01
0.1
1
10
100
TC = 25°C
TC = 125°C
G025
TC - Case Temperature - °C
Normalized On-State Resistance
-75 -25 25 75 125 175
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
G022
ID = 14A
VGS = 8V
TC - Case Temperature - °C
Normalized On-State Resistance
-75 -25 25 75 125 175
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
G023
ID = 14A
VGS = 8V
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SLPS264D –OCTOBER 2010–REVISED MAY 2015
Typical Power Block MOSFET Characteristics (continued)
TA= 25°C, unless stated otherwise.
Figure 22. Control MOSFET Normalized RDS(on) Figure 23. Sync MOSFET Normalized RDS(on)
Figure 24. Control MOSFET Body Diode Figure 25. Sync MOSFET Body Diode
Figure 26. Control MOSFET Unclamped Inductive Switching Figure 27. Sync MOSFET Unclamped Inductive Switching
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6 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Application Information
6.1.1 Equivalent System Performance
Many of today’s high performance computing systems require low power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s Synchronous Buck Topology. In particular, there has been an
emphasis in improving the performance of the critical Power Semiconductor in the Power Stage of this
Application (see Figure 28). As such, optimization of the power semiconductors in these applications, needs to
go beyond simply reducing RDS(ON).
Figure 28.
The CSD86330Q3D is part of TI’s Power Block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the Control FET and Sync FET connections (see Figure 29). A key
challenge solved by TI’s patented packaging technology is the system level impact of Common Source
Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases
switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the
MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system
efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI
and modification of switching loss equations are outlined in TI’s Application Note SLPA009.
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78
80
82
84
86
88
90
92
94
96
2 4 6 8 10 12 14 16 18 20 22
Output Current (A)
Efficiency (%)
PowerBlock HS/LS RDS(ON) = 8.8mΩ/4.6mΩ
Discrete HS/LS RDS(ON) = 8.8mΩ/4.6mΩ
Discrete HS/LS RDS(ON) = 8.8mΩ/3.3mΩ
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 1µH
fSW = 500kHz
TA = 25ºC
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0 2 4 6 8 10 12 14 16 18 20 22
Output Current (A)
Power Loss (W)
PowerBlock HS/LS RDS(ON) = 8.8mΩ/4.6mΩ
Discrete HS/LS RDS(ON) = 8.8mΩ/4.6mΩ
Discrete HS/LS RDS(ON) = 8.8mΩ/3.3mΩ
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 1µH
fSW = 500kHz
TA = 25ºC
CSD86330Q3D
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SLPS264D –OCTOBER 2010–REVISED MAY 2015
Application Information (continued)
Figure 29.
The combination of TI’s latest generation silicon and optimized packaging technology has created a
benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET
chipsets with lower RDS(ON).Figure 30 and Figure 31 compare the efficiency and power loss performance of the
CSD86330Q3D versus industry standard MOSFET chipsets commonly used in this type of application. This
comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The
performance of CSD86330Q3D clearly highlights the importance of considering the Effective AC On-Impedance
(ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET
RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s Power Block
technology.
TEXT ADDED FOR SPACING
Figure 30. Figure 31.
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Application Information (continued)
Table 1 compares the traditional DC measured RDS(ON) of CSD86330Q3D versus its ZDS(ON). This comparison
takes into account the improved efficiency associated with TI’s patented packaging technology. As such, when
comparing TI’s Power Block products to individually packaged discrete MOSFETs or dual MOSFETs in a
standard package, the in-circuit switching performance of the solution must be considered. In this example,
individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC
measured RDS(ON) values that are equivalent to CSD86330Q3D’s ZDS(ON) value in order to have the same
efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete
MOSFETs or dual MOSFETs in a standard package.
Table 1. Comparison of RDS(ON) vs ZDS(ON)
HS LS
Parameter Typ Max Typ Max
Effective AC On-Impedance ZDS(ON) (VGS = 5 V) 8.8 - 3.3 -
DC Measured RDS(ON) (VGS = 4.5 V) 8.8 11.5 4.6 6
The CSD86330Q3D NexFET power block is an optimized design for synchronous buck applications using 5 V
gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems
centric environment. System level performance curves such as Power Loss, Safe Operating Area, and
normalized graphs allow engineers to predict the product performance in the actual application.
6.2 Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. Figure 1 plots the power loss of the CSD86330Q3D as a function of load current. This curve
is measured by configuring and running the CSD86330Q3D as it would be in the final application (see
Figure 32).The measured power loss is the CSD86330Q3D loss and consists of both input conversion loss and
gate drive loss. Equation 1 is used to generate the power loss curve.
(VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) = Power Loss (1)
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
6.3 Safe Operating Curves (SOA)
The SOA curves in the CSD86330Q3D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the
temperature and airflow conditions required for a given load current. The area under the curve dictates the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of 4” (W) ×
3.5” (L) × 0.062” (T) and 6 copper layers of 1 oz. copper thickness.
6.4 Normalized Curves
The normalized curves in the CSD86330Q3D data sheet provides guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
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Product Folder Links: CSD86330Q3D
l TEXAS INSTRUMENTS (E %H
PWM
ENABLE
PWM
GND
BST
DRVH
LL
DRVL
CSD86330Q3D
Driver IC
VDD
GateDrive
Current(I )
DD
InputCurrent(I )
IN
InputVoltage(V )
IN
OutputCurrent(I )
OUT
TGR
VIN
PGND
VI
VO
VSW
TG
BG
GateDrive
Voltage(V )
DD
VDD
A
V
V
V
Control
FET
Sync
FET
Averaging
Circuit
AveragedSwitched
NodeVoltage
(VSW_AVG)
A
S0475-04
A
CSD86330Q3D
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SLPS264D –OCTOBER 2010–REVISED MAY 2015
Normalized Curves (continued)
Figure 32. Typical Application
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Board Temperature( C)°
020 40 60 80 100 120 140
0
5
10
15
20
25
G028
V =5V
GS
V =12V
V =1.3V
f =500kHz
L =1 H
IN
OUT
SW
OUT m
OutputCurrent(A)
1
2
3
CSD86330Q3D
SLPS264D –OCTOBER 2010–REVISED MAY 2015
www.ti.com
6.5 Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though
the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following
procedure will outline the steps the user should take to predict product performance for any set of system
conditions.
6.5.1 Design Example
Operating Conditions:
• Output Current = 15 A
• Input Voltage = 12 V
• Output Voltage = 1.2 V
• Switching Frequency = 1000 kHz
• Inductor = 0.4 µH
6.5.2 Calculating Power Loss
• Power Loss at 15 A = 2.2 W (Figure 1)
• Normalized Power Loss for input voltage ≈1.0 (Figure 7)
• Normalized Power Loss for output voltage ≈0.98 (Figure 8)
• Normalized Power Loss for switching frequency ≈1.17 (Figure 6)
• Normalized Power Loss for output inductor ≈1.06 (Figure 9)
•Final calculated Power Loss = 2.2 W × 1.0 × 0.98 × 1.17 × 1.06 ≈2.67 W
6.5.3 Calculating SOA Adjustments
• SOA adjustment for input voltage ≈0ºC (Figure 7)
• SOA adjustment for output voltage ≈–0.29ºC (Figure 8)
• SOA adjustment for switching frequency ≈4.1ºC (Figure 6)
• SOA adjustment for output inductor ≈1.5ºC (Figure 9)
•Final calculated SOA adjustment = 0 + (–0.29) + 4.1 + 1.5 ≈5.3ºC
In the design example above, the estimated power loss of the CSD86330Q3D would increase to 2.67 W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.3ºC. Figure 33
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 5.3ºC. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
Figure 33. Power Block SOA
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SLPS264D –OCTOBER 2010–REVISED MAY 2015
7 Recommended PCB Design Overview
There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and
Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief
description on how to address each parameter is provided.
7.1 Electrical Performance
The Power Block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, Driver IC, and output inductor.
• The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 34).
The example in Figure 34 uses 6 × 10 µF ceramic capacitors (TDK part number C3216X5R1C106KT or
equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of
vias interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and
C8 should follow in order.
• The Driver IC should be placed relatively close to the Power Block Gate pins. TGand BGshould connect to
the outputs of the Driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and
should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap
capacitor for the Driver IC will also connect to this pin.
• The switching node of the output inductor should be placed relatively close to the Power Block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level.
• In the event the switch node waveform exhibits ringing that reaches undesirable levels, the use of a Boost
Resistor or RC snubber can be an effective way to reduce the peak ring level. The recommended Boost
Resistor value will range between 1 Ωto 4.7 Ωdepending on the output characteristics of Driver IC used in
conjunction with the Power Block. The RC snubber values can range from 0.5 Ωto 2.2 Ωfor the R and 330
pF to 2200 pF for the C. Refer to TI App Note SLUP100 for more details on how to properly tune the RC
snubber values. The RC snubber should be placed as close as possible to the Vsw node and PGND see
Figure 34 (1)
7.2 Thermal Performance
The Power Block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 34 uses vias with a 10 mil drill hole
and a 16 mil capture pad.
• Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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Thermal Performance (continued)
Figure 34. Recommended PCB Layout (Top Down)
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SLPS264D –OCTOBER 2010–REVISED MAY 2015
8 Device and Documentation Support
8.1 Trademarks
NexFET is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
8.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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M0192-01
E1
E
q
5 6 78
1 2 34
L
d1
d2 K
b
d3
L
e
A
E2
D2
TopView
BottomView
SideView
5
9
6
7
8
1
2
3
4
qc1
D1
d
c
Exposedtieclipsmayvary
Pinout
Position
Designation
Pin1
VIN
Pin2
VIN
Pin3
TG
Pin4
TGR
Pin5
BG
Pin6
VSW
Pin7
VSW
Pin8
VSW
Pin9
PGND
CSD86330Q3D
SLPS264D –OCTOBER 2010–REVISED MAY 2015
www.ti.com
9 Mechanical, Packaging, and Orderable Information
9.1 Q3D Package Dimensions
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 1.40 1.5 0.055 0.059
b 0.280 0.400 0.011 0.016
c 0.150 0.250 0.006 0.010
c1 0.150 0.250 0.006 0.010
d 0.940 1.040 0.037 0.041
d1 0.160 0.260 0.006 0.010
d2 0.150 0.250 0.006 0.010
d3 0.250 0.350 0.010 0.014
D1 3.200 3.400 0.126 0.134
D2 2.650 2.750 0.104 0.108
E 3.200 3.400 0.126 0.134
E1 3.200 3.400 0.126 0.134
E2 1.750 1.850 0.069 0.073
e 0.650 TYP 0.026 TYP
L 0.400 0.500 0.016 0.020
θ0.00 — — —
K 0.300 TYP 0.012 TYP
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0.300(0.012)
0.300(0.012)
0.300
(0.012)
14
58
M0207-01
0.340
(0.013)
0.333
(0.013)
0.100
(0.004)
3.500(0.138)
0.160(0.005)
0.200(0.008)
0.550(0.022)
2.290
(0.090)
0.350(0.014)
0.850(0.033)
0.990
(0.039)
0.200
(0.008)
0.350(0.014)
0.210
(0.008)
14
58
M0193-01
0.440
(0.017)
0.210
(0.008)
1.900(0.075)
0.300(0.012)
0.650(0.026) 0.650(0.026)
3.600(0.142)
2.800
(0.110)
0.650
(0.026)
1.090
(0.043)
2.390
(0.094)
CSD86330Q3D
www.ti.com
SLPS264D –OCTOBER 2010–REVISED MAY 2015
9.2 Land Pattern Recommendation
NOTE: Dimensions are in mm (inches).
9.3 Stencil Recommendation
NOTE: Dimensions are in mm (inches).
For recommended circuit layout for PCB designs, see application note SLPA005 –Reducing Ringing Through
PCB Layout Techniques.
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4.00 ±0.10 (See Note 1) 2.00 ±0.05
3.60
3.60
1.30
1.75 ±0.10
M0144-01
8.00 ±0.10
12.00 +0.30
–0.10
5.50 ±0.05
Ø 1.50 +0.10
–0.00
CSD86330Q3D
SLPS264D –OCTOBER 2010–REVISED MAY 2015
www.ti.com
9.4 Q3D Tape and Reel Information
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ±0.0 5 mm
6. MSL1 260°C (IR and convection) PbF reflow compatible
Spacer
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I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension desIgned Io accommodaIe me component Iengm KO Dlmenslun desIgned to accommodate me componem Ihlckness 7 w Overen wmm OHhe earner cape i p1 Pitch between successwe cavIIy eemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CSD86330Q3D LSON-
CLIP DQZ 8 2500 330.0 12.4 3.55 3.55 1.7 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jun-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CSD86330Q3D LSON-CLIP DQZ 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jun-2020
Pack Materials-Page 2
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