Datenblatt für ADS1118 von Texas Instruments

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l V'.‘ INSTRUMENTS P414 mg PM

Digital Filter

and

Interface

Oscillator

Voltage

Reference

Temperature

Sensor

Mux PGA

16-bit

û

ADC

AIN0

AIN1

SCLK

VDD

GND

DOUT/DRDY

DIN

ADS1118

0.1 F

AIN2

AIN3

3.3 V

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &

Community

Reference

Design

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADS1118

SBAS457F –OCTOBER 2010–REVISED SEPTEMBER 2019

ADS1118 Ultrasmall, Low-Power, SPI™-Compatible, 16-Bit

Analog-to-Digital Converter with Internal Reference and Temperature Sensor

1 Features

1• Ultrasmall X2QFN Package:

2 mm × 1.5 mm × 0.4 mm

• Wide Supply Range: 2 V to 5.5 V

• Low Current Consumption:

– Continuous Mode: Only 150 μA

– Single-Shot Mode: Automatic Power Down

• Programmable Data Rate:

8 SPS to 860 SPS

• Single-Cycle Settling

• Internal Low-Drift Voltage Reference

• Internal Temperature Sensor:

0.5°C (Maximum) Error: 0°C to 70°C

• Internal Oscillator

• Internal PGA

• Four Single-Ended or Two Differential Inputs

2 Applications

• Temperature Measurement:

– Thermocouple Measurement

– Cold-Junction Compensation

– Thermistor Measurement

• Portable Instrumentation

• Factory Automation and Process Controls

3 Description

The ADS1118 is a precision, low power, 16-bit

analog-to-digital converter (ADC) that provides all

features necessary to measure the most common

sensor signals in an ultra-small, leadless X2QFN-10

package or a VSSOP-10 package. The ADS1118

integrates a programmable gain amplifier (PGA),

voltage reference, oscillator and high-accuracy

temperature sensor. These features, along with a

wide power supply range from 2 V to 5.5 V, make the

ADS1118 ideally suited for power- and space-

constrained, sensor-measurement applications.

The ADS1118 can perform conversions at data rates

up to 860 samples per second (SPS). The PGA offers

input ranges from ±256 mV to ±6.144 V, allowing

both large and small signals to be measured with

high resolution. An input multiplexer (MUX) allows to

measure two differential or four single-ended inputs.

The high-accuracy temperature sensor can be used

for system-level temperature monitoring or cold-

junction compensation for thermocouples.

The ADS1118 operates either in continuous-

conversion mode, or in a single-shot mode that

automatically powers down after a conversion.

Single-shot mode significantly reduces current

consumption during idle periods. Data are transferred

through a serial peripheral interface (SPI™). The

ADS1118 is specified from –40°C to +125°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

ADS1118 X2QFN (10) 1.50 mm × 2.00 mm

VSSOP (10) 3.00 mm × 3.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

K-Type Thermocouple Measurement

Using Integrated Temperature Sensor for Cold-Junction Compensation

l TEXAS INSTRUMENTS

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Device Comparison Table..................................... 5

6 Pin Configuration and Functions......................... 5

7 Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 6

7.2 ESD Ratings.............................................................. 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 7

7.6 Timing Requirements: Serial Interface...................... 9

7.7 Switching Characteristics: Serial Interface................ 9

7.8 Typical Characteristics............................................ 10

8 Parameter Measurement Information ................ 16

8.1 Noise Performance ................................................. 16

9 Detailed Description............................................ 17

9.1 Overview ................................................................. 17

9.2 Functional Block Diagram....................................... 17

9.3 Feature Description................................................. 18

9.4 Device Functional Modes........................................ 22

9.5 Programming........................................................... 23

9.6 Register Maps......................................................... 26

10 Application and Implementation........................ 28

10.1 Application Information.......................................... 28

10.2 Typical Application ............................................... 33

11 Power Supply Recommendations ..................... 36

11.1 Power-Supply Sequencing.................................... 36

11.2 Power-Supply Decoupling..................................... 36

12 Layout................................................................... 37

12.1 Layout Guidelines ................................................. 37

12.2 Layout Example .................................................... 38

13 Device and Documentation Support ................. 39

13.1 Documentation Support ........................................ 39

13.2 Receiving Notification of Documentation Updates 39

13.3 Community Resources.......................................... 39

13.4 Trademarks........................................................... 39

13.5 Electrostatic Discharge Caution............................ 39

13.6 Glossary................................................................ 39

14 Mechanical, Packaging, and Orderable

Information ........................................................... 39

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (October 2015) to Revision F Page

• Changed maximum VDD voltage from 5.5 V to 7 V in the Absolute Maximum Ratings table............................................... 6

• Changed bit description of Config Register bit 0.................................................................................................................. 27

Changes from Revision D (October 2013) to Revision E Page

• Added ESD Ratings table, Feature Description section, Noise Performance section, Device Functional Modes

section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

• Changed title, Description section, Features section, and block diagram on front page ....................................................... 1

• Changed title from Product Family to Device Comparison Table and deleted Package Designator column ........................ 5

• Updated descriptions and changed name of I/O column in Pin Configurations and Functions table .................................... 5

• Changed digital input voltage range and added minimum specification for TJin Absolute Maximum Ratings table ............ 6

• Added Differential input impedance specification in Electrical Characteristics ...................................................................... 7

• Changed Condition statement in Timing Requirements: Serial Interface ............................................................................. 9

• Moved tCSDOD, tDOPD, and tCSDOZ parameters from Timing Requirements to Switching Characteristics ................................ 9

• Moved tCSDOD and tCSDOZ values from MIN column to MAX column....................................................................................... 9

• Deleted Noise vs Input Signal,Noise vs Supply Voltage, and Noise vs Input Signal plots ................................................. 10

• Updated Overview section and deleted "Gain = 2/3, 1, 2, 4, 8, or 16" from Functional Block Diagram ............................. 17

• Updated Analog Inputs section............................................................................................................................................. 19

• Updated Full-Scale Range (FSR) and LSB Size section ..................................................................................................... 20

• Updated Reset and Power Up section ................................................................................................................................. 22

• Updated 32-Bit Data Transmission Cycle section................................................................................................................ 25

• Updated Register Maps section ........................................................................................................................................... 26

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• Updated Application Information section.............................................................................................................................. 28

• Updated Figure 48................................................................................................................................................................ 31

• Deleted Thermocouple Measurement With Cold Junction Temperature section, and moved Figure 50 to Typical

Application section................................................................................................................................................................ 33

Changes from Revision C (February 2013) to Revision D Page

• Deleted device graphic........................................................................................................................................................... 1

• Changed bit 1 to NOP0 in Figure 44.................................................................................................................................... 26

• Changed NOP bit description in Figure 44: changes bits[2:0] to bits [2:1] and changed NOP to NOP[1:0]........................ 27

Changes from Revision B (August 2012) to Revision C Page

• Changed document to current standards............................................................................................................................... 1

• Changed Single-Shot Mode sub-bullet in Low Current Consumption Features bullet........................................................... 1

• Changed Internal Temperature Sensor Features bullet......................................................................................................... 1

• Changed Description section.................................................................................................................................................. 1

• Changed Product Family table ............................................................................................................................................... 5

• Changed Function column name in Pin Descriptions table.................................................................................................... 5

• Changed Analog Input, Full-scale input voltage range parameter row in Electrical Characteristics table............................. 6

• Changed footnotes 1 and 2 in Electrical Characteristics table............................................................................................... 6

• Changed conditions for Electrical Characteristics table ......................................................................................................... 7

• Changed System Performance, Integral nonlinearity and Gain Error test conditions in Electrical Characteristics table....... 7

• Changed first two Temperature Sensor, Temperature sensor accuracy parameter test conditions in Electrical

Characteristics table ............................................................................................................................................................... 7

• Changed Power-Supply Requirements, Supply current parameter test conditions in Electrical Characteristics table.......... 8

• Changed footnote 3 of Timing Requirements: Serial Interface Timing table.......................................................................... 9

• Updated Figure 3.................................................................................................................................................................. 10

• Updated Figure 9.................................................................................................................................................................. 10

• Changed title of Figure 11 to Figure 14................................................................................................................................ 10

• Updated Figure 15 and Figure 33 ........................................................................................................................................ 11

• Changed conditions in Figure 21 to Figure 25 ..................................................................................................................... 12

• Updated Figure 20................................................................................................................................................................ 13

• Changed comments in Figure 27 to Figure 31..................................................................................................................... 13

• Changed Overview section................................................................................................................................................... 17

• Updated Multiplexer section ................................................................................................................................................. 18

• Changed Full-Scale Input section......................................................................................................................................... 20

• Changed Voltage Reference section.................................................................................................................................... 20

• Changed Oscillator section................................................................................................................................................... 20

• Added multiplication points to example equations in Converting from Digital Codes to Temperature section.................... 21

• Changed Serial Interface,Chip Select,Serial Clock,Data Input, and Data Output and Data Ready sections................... 23

• Changed Data Retrieval section........................................................................................................................................... 24

• Changed Registers section .................................................................................................................................................. 26

• Changed Aliasing,Reset and Power Up,Operating Modes, and Duty Cycling for Low Power sections ............................ 29

• Updated Figure 50................................................................................................................................................................ 33

l TEXAS INSTRUMENTS

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SBAS457F –OCTOBER 2010–REVISED SEPTEMBER 2019

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Changes from Revision A (July 2011) to Revision B Page

• Added (VSSOP) to titles of Figure 20 to Figure 25.............................................................................................................. 13

• Added Figure 26 to Figure 31............................................................................................................................................... 14

l TEXAS INSTRUMENTS 0w UUUU ﬂﬂﬂﬂ Amt ﬂﬂﬂﬂﬂ UUUUU

SCLK

GND

AIN0

AIN1

DIN

VDD

AIN3

AIN2

CS DOUT/

DRDY

AIN1

DIN

SCLK

GND

AIN0

AIN1

DIN

DOUT/

DRDY

VDD

AIN3

AIN2

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5 Device Comparison Table

DEVICE RESOLUTION

(Bits)

MAXIMUM SAMPLE

RATE

(SPS)

INPUT CHANNELS

Differential

(Single-Ended) PGA INTERFACE SPECIAL

FEATURES

ADS1118 16 860 2 (4) Yes SPI Temperature sensor

ADS1018 12 3300 2 (4) Yes SPI Temperature sensor

ADS1115 16 860 2 (4) Yes I2CComparator

ADS1114 16 860 1 (1) Yes I2CComparator

ADS1113 16 860 1 (1) No I2CNone

ADS1015 12 3300 2 (4) Yes I2CComparator

ADS1014 12 3300 1 (1) Yes I2CComparator

ADS1013 12 3300 1 (1) No I2CNone

6 Pin Configuration and Functions

RUG Package

10-Pin X2QFN

Top View

DGS Package

10-Pin VSSOP

Top View

Pin Functions

PIN TYPE DESCRIPTION

NO. NAME

1 SCLK Digital input Serial clock input

2 CS Digital input Chip select; active low. Connect to GND if not used.

3 GND Supply Ground

4 AIN0 Analog input Analog input 0. Leave unconnected or tie to VDD if not used.

5 AIN1 Analog input Analog input 1. Leave unconnected or tie to VDD if not used.

6 AIN2 Analog input Analog input 2. Leave unconnected or tie to VDD if not used.

7 AIN3 Analog input Analog input 3. Leave unconnected or tie to VDD if not used.

8 VDD Supply Power supply. Connect a 100-nF power supply decoupling capacitor to GND.

9 DOUT/DRDY Digital output Serial data output combined with data ready; active low

10 DIN Digital input Serial data input

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Power-supply voltage VDD to GND –0.3 7 V

Analog input voltage AIN0, AIN1, AIN2, AIN3 GND – 0.3 VDD + 0.3 V

Digital input voltage DIN, DOUT/DRDY, SCLK, CS GND – 0.3 VDD + 0.3 V

Input current, continuous Any pin except power supply pins –10 10 mA

Temperature Junction, TJ–40 150 °C

Storage, Tstg –60 150

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic

discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

(1) AINP and AINN denote the selected positive and negative inputs. AINx denotes one of the four available analog inputs.

(2) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be

applied to this device.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN NOM MAX UNIT

POWER SUPPLY

VDD Power supply VDD to GND 2 5.5 V

ANALOG INPUTS(1)

FSR Full-scale input voltage range(2) VIN = V(AINP) - V(AINN) See Table 3

V(AINx) Absolute input voltage GND VDD V

DIGITAL INPUTS

Input voltage GND VDD V

TEMPERATURE RANGE

TAOperating ambient temperature –40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.4 Thermal Information

THERMAL METRIC(1)

ADS1118

UNITDGS (VSSOP) RUG (X2QFN)

10 PINS 10 PINS

RθJA Junction-to-ambient thermal resistance 186.8 245.2 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 51.5 69.3 °C/W

RθJB Junction-to-board thermal resistance 108.4 172 °C/W

ψJT Junction-to-top characterization parameter 2.7 8.2 °C/W

ψJB Junction-to-board characterization parameter 106.5 170.8 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W

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(1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be

applied to this device.

(2) Best-fit INL; covers 99% of full-scale.

(3) Includes all errors from onboard PGA and voltage reference.

(4) Maximum value specified by characterization.

7.5 Electrical Characteristics

Maximum and minimum specifications apply from TA= –40°C to +125°C. Typical specifications are at TA= 25°C.

All specifications are at VDD = 3.3 V, data rate = 8 SPS, and full-scale range (FSR) = ±2.048 V (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG INPUTS

Common-mode input impedance

FSR = ±6.144 V(1) 8

MΩ

FSR = ±4.096 V(1), FSR = ±2.048 V 6

FSR = ±1.024 V 3

FSR = ±0.512 V, FSR = ±0.256 V 100

Differential input impedance

FSR = ±6.144 V(1) 22

MΩ

FSR = ±4.096 V(1) 15

FSR = ±2.048 V 4.9

FSR = ±1.024 V 2.4

FSR = ±0.512 V, FSR = ±0.256 V 710 kΩ

SYSTEM PERFORMANCE

Resolution (No missing codes) 16 Bits

DR Data rate 8, 16, 32, 64, 128, 250, 475, 860 SPS

Data rate variation All data rates –10% 10%

Output noise See Noise Performance section

INL Integral nonlinearity DR = 8 SPS, FSR = ±2.048 V(2) 1 LSB

Offset error FSR = ±2.048 V, differential inputs ±0.1 ±2 LSB

FSR = ±2.048 V, single-ended inputs ±0.25

Offset drift FSR = ±2.048 V 0.002 LSB/°C

Offset power-supply rejection FSR = ±2.048 V, DC supply variation 0.2 LSB/V

Offset channel match Match between any two inputs 0.6 LSB

Gain error(3) FSR = ±2.048 V, TA= 25°C 0.01% 0.15%

Gain drift(3)(4)

FSR = ±0.256 V 7

ppm/°CFSR = ±2.048 V 5 40

FSR = ±6.144 V(1) 5

Gain power-supply rejection 10 ppm/V

Gain match(3) Match between any two gains 0.01% 0.1%

Gain channel match Match between any two inputs 0.01% 0.1%

CMRR Common-mode rejection ratio

At DC, FSR = ±0.256 V 105

At DC, FSR = ±2.048 V 100

At DC, FSR = ±6.144 V(1) 90

fCM = 50 Hz, DR = 860 SPS 105

fCM = 60 Hz, DR = 860 SPS 105

TEMPERATURE SENSOR

Temperature range –40 125 °C

Temperature resolution 0.03125 °C/LSB

Accuracy

TA= 0°C to 70°C 0.2 ±0.5 °C

TA= –40°C to +125°C 0.4 ±1

vs supply 0.03125 ±0.25 °C/V

l TEXAS INSTRUMENTS

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Electrical Characteristics (continued)

Maximum and minimum specifications apply from TA= –40°C to +125°C. Typical specifications are at TA= 25°C.

All specifications are at VDD = 3.3 V, data rate = 8 SPS, and full-scale range (FSR) = ±2.048 V (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL INPUTS/OUTPUTS

VIH High-level input voltage 0.7 VDD VDD V

VIL Low-level input voltage GND 0.2 VDD V

VOH High-level output voltage IOH = 1 mA 0.8 VDD V

VOL Low-level output voltage IOL = 1 mA GND 0.2 VDD V

IHInput leakage, high VIH = 5.5 V –10 10 μA

ILInput leakage, low VIL = GND –10 10 μA

POWER SUPPLY

IVDD Supply current

Power down, TA= 25°C 0.5 2

μA

Power down 5

Operating, TA= 25°C 150 200

Operating 300

PDPower dissipation

VDD = 5 V 0.9

mWVDD = 3.3 V 0.5

VDD = 2 V 0.3

‘5‘ TEXAS INSTRUMENTS ’ _‘ {1+ \*L——1 » WN— IWX if. ''''''''''''''''''''''''''''' : ::::::::::f:.<:><:>

SCLK

DIN

DOUT

tSCLK

tCSSC tSPWH

tDIHD tSPWL

tCSDOZ

tDOHD

tDOPD

tSCCS

tSCSC

tCSH

tCSDOD

tDIST

Hi-Z Hi-Z

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(1) CS can be tied low permanently in case the serial bus is not shared with any other device.

(2) Holding SCLK low longer than 28 ms resets the SPI interface.

7.6 Timing Requirements: Serial Interface

Over operating ambient temperature range and VDD = 2 V to 5.5 V (unless otherwise noted)

MIN MAX UNIT

tCSSC Delay time, CS falling edge to first SCLK rising edge(1) 100 ns

tSCCS Delay time, final SCLK falling edge to CS rising edge 100 ns

tCSH Pulse duration, CS high 200 ns

tSCLK SCLK period 250 ns

tSPWH Pulse duration, SCLK high 100 ns

tSPWL Pulse duration, SCLK low(2) 100 ns

28 ms

tDIST Setup time, DIN valid before SCLK falling edge 50 ns

tDIHD Hold time, DIN valid after SCLK falling edge 50 ns

tDOHD Hold time, SCLK rising edge to DOUT invalid 0 ns

7.7 Switching Characteristics: Serial Interface

Over operating ambient temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tCSDOD Propagation delay time,

CS falling edge to DOUT driven DOUT load = 20 pF || 100 kΩto GND 100 ns

tDOPD Propagation delay time,

SCLK rising edge to valid new DOUT DOUT load = 20 pF || 100 kΩto GND 0 50 ns

tCSDOZ Propagation delay time,

CS rising edge to DOUT high impedance DOUT load = 20 pF || 100 kΩto GND 100 ns

Figure 1. Serial Interface Timing

l TEXAS INSTRUMENTS Supp‘y Vanage (V) Gm Inpm Swgna‘ M Inpm Swgna‘ w) mpm Slgnal (V)

−10

−8

−6

−4

−2

−0.5 −0.4 −0.2 −0.1 0 0.1 0.2 0.4 0.5

Input Signal (V)

Integral Nonlinearity (ppm)

T = −40°C

T = 25°C

T = 125°C

−5

−4

−3

−2

−1

−2 −1.5 −1 −0.5 0 0.5 1 1.5 2

Input Signal (V)

Integral Nonlinearity (ppm)

T = −40°C

T = 25°C

T = 125°C

−5

−4

−3

−2

−1

−2 −1.5 −1 −0.5 0 0.5 1 1.5 2

Input Signal (V)

Integral Nonlinearity (ppm)

T = −40°C

T = 25°C

T = 125°C

2.5

7.5

12.5

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Supply Voltage (V)

Integral Nonlinearity (ppm)

FSR = ±0.256 V

FSR = ±0.512 V

FSR = ±2.048 V

FSR = ±6.144 V

G010

Total Error (mV)

-2.048 -1.024 0 1.024 2.048

Input Signal (V)

−4

−3

−2

−1

−60 −40 −20 0 20 40 60 80 100 120 140

Temperature (°C)

Data Rate Error (%)

VDD = 2.0 V

VDD = 3.3 V

VDD = 5.0 V

G028

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7.8 Typical Characteristics

At TA= 25°C, VDD = 3.3 V, FSR = ±2.048 V (unless otherwise noted).

DR = 860 SPS, diff inputs, includes noise, offset and gain error

Figure 2. Total Error vs Input Signal Figure 3. Data Rate vs Temperature

Figure 4. INL vs Supply Voltage

FSR = ±2.048 V, DR = 8 SPS, VDD = 3.3 V, best fit

Figure 5. INL vs Input Signal

FSR = ±0.512 V, DR = 8 SPS, VDD = 3.3 V, best fit

Figure 6. INL vs Input Signal

FSR = ±2.048 V, DR = 8 SPS, VDD = 5 V, best fit

Figure 7. INL vs Input Signal

l TEXAS INSTRUMENTS Inpm Signal (V) cm Data Rate (SP5) Temperamre cc) W Supp‘y Vanage (V) mm mm

−60

−40

−20

2 2.5 3 3.5 4 4.5 5

Supply Voltage (V)

Offset Voltage (µV)

AIN0 to GND

AIN1 to GND

AIN2 to GND

AIN3 to GND

G005

−40

−30

−20

−10

−40 −20 0 20 40 60 80 100 120

Temperature (°C)

Offset Voltage (µV)

AIN0 to AIN1

AIN0 to AIN3

AIN1 to AIN3

AIN2 to AIN3

G006

8 16 32 64 128 250 475 8608 16 32 64 128 250 475 860

Data Rate (SPS)

Integral Nonlinearity (ppm)

T = −40°C

T =

A25°C

T =

A125°C

−60

−40

−20

−40 −20 0 20 40 60 80 100 120

Temperature (°C)

Offset Voltage (µV)

AIN0 to GND

AIN1 to GND

AIN2 to GND

AIN3 to GND

G004

−10

−8

−6

−4

−2

−0.5 −0.4 −0.2 −0.1 0 0.1 0.2 0.4 0.5

Input Signal (V)

Integral Nonlinearity (ppm)

T = −40°C

T = 25°C

T = 125°C

−60 −40 −20 0 20 40 60 80 100 120 140

Temperature (°C)

Integral Nonlinearity (ppm)

VDD = 2.0 V

VDD = 3.3 V

VDD = 5.0 V

G015

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Typical Characteristics (continued)

At TA= 25°C, VDD = 3.3 V, FSR = ±2.048 V (unless otherwise noted).

FSR = ±0.512 V, DR = 8 SPS, VDD = 5 V, best fit

Figure 8. INL vs Input Signal

FSR = ±2.048 V, DR = 8 SPS, best fit

Figure 9. INL vs Temperature

FSR = ±2.048 V, best fit

Figure 10. INL vs Data Rate Figure 11. Single-Ended Offset Voltage vs Temperature

Figure 12. Single-Ended Offset Voltage vs Supply Figure 13. Differential Offset Voltage vs Temperature

l TEXAS INSTRUMENTS Supply Vanage (V) 15 | —‘\\| Oﬁse‘ Dnﬂ (LSBPC) A 200 nos Temperame (c) FSR : i256 mV Supp‘y Vonage (V) 200

−0.02

−0.015

−0.01

−0.005

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

−0.02

−0.015

−0.01

−0.005

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

100

150

200

Gain Error (%)

Number of Occurrences

G000

0.15

0.1

0.05

0.1

0.15

Gain Error (%)

2 2.5 3 3.5 4 4.5 5 5.5

Supply Voltage (V)

FSR = 256 mV±

FSR = 2.048 V±

−10

−8

−6

−4

−2

−10

−8

−6

−4

−2

100

150

200

Offset (µV)

Number of Occurrences

G000

−0.05

−0.04

−0.03

−0.02

−0.01

0.01

0.02

0.03

0.04

0.05

−40 −20 0 20 40 60 80 100 120 140

Temperature (°C)

Gain Error (%)

FSR = ±0.256 V

FSR = ±0.512 V

FSR = ±1.024 V

FSR = ±2.048 V

FSR = ±4.096 V

FSR = ±6.144 V

−0.005

−0.004

−0.003

−0.002

−0.001

0.001

0.002

0.003

0.004

0.005

−0.005

−0.004

−0.003

−0.002

−0.001

0.001

0.002

0.003

0.004

0.005

Offset Drift (LSB/°C)

Number of Occurrences

G046

−40

−30

−20

−10

2 2.5 3 3.5 4 4.5 5

Supply Voltage (V)

Offset Voltage (µV)

AIN0 to AIN1

AIN0 to AIN3

AIN1 to AIN3

AIN2 to AIN3

G007

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Typical Characteristics (continued)

At TA= 25°C, VDD = 3.3 V, FSR = ±2.048 V (unless otherwise noted).

Figure 14. Differential Offset Voltage vs Supply

FSR = ±2.048 V, TA= –40°C to +125°C, MUX = AIN0 to AIN3,

540 units from 3 production lots

Figure 15. Offset Drift Histogram

FSR = ±2.048 V,

540 units from 3 production lots

Figure 16. Offset Histogram Figure 17. Gain Error vs Temperature

Figure 18. Gain Error vs Supply

FSR = ±2.048 V,

540 units from 3 production lots

Figure 19. Gain Error Histogram

l TEXAS INSTRUMENTS [V [V

Temperature Error (qC)

Number of Occurences

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

Temperature Error (qC)

Number of Occurences

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

Temperature Error (qC)

Number of Occurences

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

Temperature Error (qC)

Number of Occurences

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

Temperature Error (qC)

Number of Occurences

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

−40 −20 0 20 40 60 80 100 120

Temperature (°C)

Temperature Error (°C)

Average Temperature Error

Average ± 3 sigma

Average ± 6 sigma

G023

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Typical Characteristics (continued)

At TA= 25°C, VDD = 3.3 V, FSR = ±2.048 V (unless otherwise noted).

Figure 20. Temperature Sensor Error vs Temp (VSSOP)

TA= –40°C, 48 units from 3 production lots

Figure 21. Temperature Sensor Error Histogram (VSSOP)

TA= 0°C, 48 units from 3 production lots

Figure 22. Temperature Sensor Error Histogram (VSSOP)

TA= 25°C, 48 units from 3 production lots

Figure 23. Temperature Sensor Error Histogram (VSSOP)

TA= 70°C, 48 units from 3 production lots

Figure 24. Temperature Sensor Error Histogram (VSSOP)

TA= 125°C, 48 units from 3 production lots

Figure 25. Temperature Sensor Error Histogram (VSSOP)

l TEXAS INSTRUMENTS I“ I“

Temperature Error (qC)

Number of Occurences

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

Temperature Error (qC)

Number of Occurences

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

Temperature Error (qC)

Number of Occurences

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

Temperature Error (qC)

Number of Occurences

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

Temperature Error (qC)

Number of Occurences

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

-40 -20 0 20 40 60 80 100 120

Temperature Error (ƒC)

Temperature (ƒC)

Average Temperature Error

Average “ 3 sigma

Average “ 6 sigma

C007

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Typical Characteristics (continued)

At TA= 25°C, VDD = 3.3 V, FSR = ±2.048 V (unless otherwise noted).

Figure 26. Temperature Sensor Error vs Temp (X2QFN)

TA= –40°C, 94 units from production

Figure 27. Temperature Sensor Error Histogram (X2QFN)

TA= 0°C, 94 units from production

Figure 28. Temperature Sensor Error Histogram (X2QFN)

TA= 25°C, 94 units from production

Figure 29. Temperature Sensor Error Histogram (X2QFN)

TA= 70°C, 94 units from production

Figure 30. Temperature Sensor Error Histogram (X2QFN)

TA= 125°C, 94 units from production

Figure 31. Temperature Sensor Error Histogram (X2QFN)

l TEXAS INSTRUMENTS 300 5 v /, -— / / f _ . / / ////§/ / : Z/ Wu : 2 v VDD 130 Temperature we) m \npu‘ Frequency (Hz)

Gain (dB)

1 10 100 1k 10k

Input Frequency (Hz)

0.5

1.5

2.5

3.5

4.5

−40 −20 0 20 40 60 80 100 120 140

Temperature (°C)

Power−Down Current (µA)

VDD = 2.0 V

VDD = 3.3 V

VDD = 5.0 V

G003

300

250

200

150

100

Operating Current ( A)m

-40 -20 0 20 40 60 80 100 120 140

Temperature ( C)°

VDD = 5 V

VDD = 2 V VDD = 3.3 V

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Typical Characteristics (continued)

At TA= 25°C, VDD = 3.3 V, FSR = ±2.048 V (unless otherwise noted).

Figure 32. Operating Current vs Temperature Figure 33. Power-Down Current vs Temperature

DR = 8 SPS

Figure 34. Digital Filter Frequency Response

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8 Parameter Measurement Information

8.1 Noise Performance

Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input

signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and

decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between

modulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and thus

reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the input-

referred noise drops when reducing the output data rate because more samples of the internal modulator are

averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is

particularly useful when measuring low-level signals.

Table 1 and Table 2 summarize the device noise performance. Data are representative of typical noise

performance at TA= 25°C with the inputs shorted together externally. Table 1 show the input-referred noise in

units of μVRMS for the conditions shown. Note that µVPP values are shown in parenthesis. Table 2 shows the

corresponding data in effective number of bits (ENOB) calculated from μVRMS values using Equation 1. The

noise-free bits calculated from peak-to-peak noise values using Equation 2 are shown in parenthesis.

ENOB = ln (FSR / VRMS-Noise) / ln(2) (1)

Noise-Free Bits = ln (FSR / VPP-Noise) / ln(2) (2)

Table 1. Noise in μVRMS (μVPP) at VDD = 3.3 V

DATA RATE

(SPS)

FSR (Full-Scale Range)

±6.144 V ±4.096 V ±2.048 V ±1.024 V ±0.512 V ±0.256 V

8 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)

16 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)

32 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)

64 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)

128 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (12.35)

250 187.5 (252.09) 125 (148.28) 62.5 (84.03) 31.25 (39.54) 15.62 (16.06) 7.81 (18.53)

475 187.5 (266.92) 125 (227.38) 62.5 (79.08) 31.25 (56.84) 15.62 (32.13) 7.81 (25.95)

860 187.5 (430.06) 125 (266.93) 62.5 (118.63) 31.25 (64.26) 15.62 (40.78) 7.81 (35.83)

Table 2. ENOB from RMS Noise (Noise-Free Bits from Peak-to-Peak Noise) at VDD = 3.3 V

DATA RATE

(SPS)

FSR (Full-Scale Range)

±6.144 V ±4.096 V ±2.048 V ±1.024 V ±0.512 V ±0.256 V

8 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)

16 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)

32 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)

64 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)

128 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.33)

250 16 (15.57) 16 (15.75) 16 (15.57) 16 (15.66) 16 (15.96) 16 (14.75)

475 16 (15.49) 16 (15.13) 16 (15.66) 16 (15.13) 16 (14.95) 16 (14.26)

860 16 (14.8) 16 (14.9) 16 (15.07) 16 (14.95) 16 (14.61) 16 (13.8)

‘5‘ TEXAS INSTRUMENTS VDD GND

16-Bit

ADC

ΔΣ Serial

Peripheral

Interface

Voltage

Reference

Oscillator

DIN

DOUT/DRDY

SCLK

PGA

Device

AIN1

AIN2

GND

AIN0

AIN3

VDD

Mux

Temperature

Sensor

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9 Detailed Description

9.1 Overview

The ADS1118 is a very small, low-power, 16-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC). The

ADS1118 consists of a ΔΣ ADC core with adjustable gain, an internal voltage reference, a clock oscillator, and

an SPI. This device is also a highly linear and accurate temperature sensor. All of these features are intended to

reduce required external circuitry and improve performance. Functional Block Diagram shows the ADS1118

functional block diagram.

The ADS1118 ADC core measures a differential signal, VIN, that is the difference of V(AINP) and V(AINN). The

converter core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. This

architecture results in a very strong attenuation in any common-mode signals. Input signals are compared to the

internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a

code proportional to the input voltage.

The ADS1118 has two available conversion modes: single-shot mode and continuous conversion mode. In

single-shot mode, the ADC performs one conversion of the input signal upon request and stores the value to an

internal conversion register. The device then enters a power-down state. This mode is intended to provide

significant power savings in systems that require only periodic conversions or when there are long idle periods

between conversions. In continuous conversion mode, the ADC automatically begins a conversion of the input

signal as soon as the previous conversion is completed. The rate of continuous conversion is equal to the

programmed data rate. Data can be read at any time and always reflect the most recently completed conversion.

9.2 Functional Block Diagram

l TEXAS INSTRUMENTS T T w o Lin: GND

VDD

GND

AIN0

VDD

GND

AIN1

VDD

GND

AIN2

VDD

GND

AIN3

AINP

AINN

GND

Device

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9.3 Feature Description

9.3.1 Multiplexer

The ADS1118 contains an input multiplexer (mux), as shown in Figure 35. Either four single-ended or two

differential signals can be measured. Additionally, AIN0, AIN1, and AIN2 can be measured differentially to AIN3.

The multiplexer is configured by bits MUX[2:0] in the Config register. When single-ended signals are measured,

the negative input of the ADC is internally connected to GND by a switch within the multiplexer.

Figure 35. Input Multiplexer

When measuring single-ended inputs, the device does not output negative codes. These negative codes indicate

negative differential signals; that is, (V(AINP) – V(AINN)) < 0. Electrostatic discharge (ESD) diodes to VDD and GND

protect the ADS1118 inputs. To prevent the ESD diodes from turning on, keep the absolute voltage on any input

within the range given in Equation 3:

GND – 0.3 V < V(AINx) < VDD + 0.3 V (3)

If the voltages on the input pins can possibly violate these conditions, use external Schottky diodes and series

resistors to limit the input current to safe values (see the Absolute Maximum Ratings table).

Also, overdriving one unused input on the ADS1118 may affect conversions currently taking place on other input

pins. If overdriving unused inputs is possible, clamp the signal with external Schottky diodes.

l TEXAS INSTRUMENTS E 0 7 V MDE4H s‘ 52 :> A 0—/ 9—0

tSAMPLE

OFF

Equivalent

Circuit

f(MOD) = 250 kHz

ZCM

ZDIFF

ZCM

AINN

AINP

0.7 V

CA1

CA2

0.7 V

0.7 VAINN

AINP

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Feature Description (continued)

9.3.2 Analog Inputs

The ADS1118 uses a switched-capacitor input stage where capacitors are continuously charged and then

discharged to measure the voltage between AINPand AINN. This frequency at which the input signal is sampled

is called the sampling frequency or the modulator frequency (f(MOD)). ADS1118 has a 1 MHz internal oscillator

which is further divided by a factor of 4 to generate the modulator frequency at 250 kHz. The capacitors used in

this input stage are small, and to external circuitry, the average loading appears resistive. This structure is shown

in Figure 36. The resistance is set by the capacitor values and the rate at which they are switched. Figure 37

shows the setting of the switches illustrated in Figure 36. During the sampling phase, switches S1are closed.

This event charges CA1 to V(AINP), CA2 to V(AINN), and CBto (V(AINP) – V(AINN)). During the discharge phase, S1is

first opened and then S2is closed. Both CA1 and CA2 then discharge to approximately 0.7 V and CBdischarges to

0 V. This charging draws a very small transient current from the source driving the ADS1118 analog inputs. The

average value of this current can be used to calculate the effective impedance (Zeff), where Zeff = VIN / IAVERAGE.

Figure 36. Simplified Analog Input Circuit

Figure 37. S1and S2Switch Timing

The common-mode input impedance is measured by applying a common-mode signal to the shorted AINPand

AINNinputs and measuring the average current consumed by each pin. The common-mode input impedance

changes depending on the full-scale range, but is approximately 6 MΩfor the default full-scale range. In

Figure 36, the common-mode input impedance is ZCM.

The differential input impedance is measured by applying a differential signal to AINPand AINNinputs where one

input is held at 0.7 V. The current that flows through the pin connected to 0.7 V is the differential current and

scales with the full-scale range. In Figure 36, the differential input impedance is ZDIFF.

Make sure to consider the typical value of the input impedance. Unless the input source has a low impedance,

the ADS1118 input impedance may affect the measurement accuracy. For sources with high-output impedance,

buffering may be necessary. Active buffers introduce noise, and also introduce offset and gain errors. Consider

all of these factors in high-accuracy applications.

The clock oscillator frequency drifts slightly with temperature; therefore, the input impedances also drift. For most

applications, this input impedance drift is negligible, and can be ignored.

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Feature Description (continued)

9.3.3 Full-Scale Range (FSR) and LSB Size

A programmable gain amplifier (PGA) is implemented before the ADS1118 ΔΣ core. The full-scale range is

configured by three bits (PGA[2:0]) in the Config Register and can be set to ±6.144 V, ±4.096 V, ±2.048 V,

±1.024 V, ±0.512 V, ±0.256 V. Table 3 shows the FSR together with the corresponding LSB size. LSB size is

calculated from full-scale voltage by the formula shown in Equation 4. However, analog input voltages may never

exceed the analog input voltage limits given in the Electrical Characteristics. If a supply voltage of VDD greater

than 4 V is used, the ±6.144 V full-scale range allows input voltages to extend up to the supply. Note though that

in this case, or whenever the supply voltage is less than the full-scale range (for example, VDD = 3.3 V and full-

scale range = ±4.096 V), a full-scale ADC output code cannot be obtained. This inability means that some

dynamic range is lost.

LSB = FSR / 216 (4)

(1) This parameter expresses the full-scale range of the ADC scaling.

No more than VDD + 0.3 V must be applied to this device.

Table 3. Full-Scale Range and Corresponding LSB Size

FSR LSB SIZE

±6.144 V(1) 187.5 μV

±4.096 V(1) 125 μV

±2.048 V 62.5 μV

±1.024 V 31.25 μV

±0.512 V 15.625 μV

±0.256 V 7.8125 μV

9.3.4 Voltage Reference

The ADS1118 has an integrated voltage reference. An external reference cannot be used with this device. Errors

associated with the initial voltage reference accuracy and the reference drift with temperature are included in the

gain error and gain drift specifications in the Electrical Characteristics.

9.3.5 Oscillator

The ADS1118 has an integrated oscillator running at 1 MHz. No external clock is required to operate the device.

Note that the internal oscillator drifts over temperature and time. The output data rate will scale proportional with

the oscillator frequency.

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9.3.6 Temperature Sensor

The ADS1118 offers an integrated precision temperature sensor. The temperature sensor mode is enabled by

setting bit TS_MODE = 1 in the Config Register. Temperature data are represented as a 14-bit result that is left-

justified within the 16-bit conversion result. Data are output starting with the most significant byte (MSB). When

reading the two data bytes, the first 14 bits are used to indicate the temperature measurement result. One 14-bit

LSB equals 0.03125°C. Negative numbers are represented in binary twos complement format, as shown in

Table 4.

Table 4. 14-Bit Temperature Data Format

TEMPERATURE (°C) DIGITAL OUTPUT (BINARY) HEX

128 01 0000 0000 0000 1000

127.96875 00 1111 1111 1111 0FFF

100 00 1100 1000 0000 0C80

75 00 1001 0110 0000 0960

50 00 0110 0100 0000 0640

25 00 0011 0010 0000 0320

0.25 00 0000 0000 1000 0008

0.03125 00 0000 0000 0001 0001

0 00 0000 0000 0000 0000

–0.25 11 1111 1111 1000 3FF8

–25 11 1100 1110 0000 3CE0

–40 11 1011 0000 0000 3B00

9.3.6.1 Converting from Temperature to Digital Codes

For positive temperatures:

Twos complement is not performed on positive numbers. Therefore, simply convert the number to binary

code in a 14-bit, left justified format with the MSB = 0 to denote the positive sign.

Example: 50°C / (0.03125°C/count) = 1600 = 0640h = 00 0110 0100 0000

For negative temperatures:

Generate the twos complement of a negative number by complementing the absolute binary number and

adding 1. Then denote the negative sign with the MSB = 1.

Example: |–25°C| / (0.03125°C/count) = 800 = 0320h = 00 0011 0010 0000

Twos complement format: 11 1100 1101 1111 + 1 = 11 1100 1110 0000

9.3.6.2 Converting from Digital Codes to Temperature

To convert from digital codes to temperature, first check whether the MSB is a 0 or a 1. If the MSB is a 0,

simply multiply the decimal code by 0.03125°C to obtain the result. If the MSB = 1, subtract 1 from the result

and complement all of the bits. Then multiply the result by –0.03125°C.

Example: The device reads back 0960h: 0960h has an MSB = 0.

0960h × 0.03125°C = 2400 × 0.03125°C = 75°C

Example: The device reads back 3CE0h: 3CE0h has an MSB = 1.

Subtract 1 and complement the result: 3CE0h →0320h

0320h × (–0.03125°C) = 800 × (–0.03125°C) = –25°C

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9.4 Device Functional Modes

9.4.1 Reset and Power Up

When the ADS1118 powers up, a reset is performed. As part of the reset process, the ADS1118 sets all of its

bits in the Config Register to the respective default settings. By default, the ADS1118 enters a power-down state

at start-up. The device interface and digital blocks are active, but no data conversions are performed. The initial

power-down state of the ADS1118 is intended to relieve systems with tight power-supply requirements from

encountering a surge during power up.

9.4.2 Operating Modes

The ADS1118 operates in one of two modes: continuous-conversion or single-shot. The MODE bit in the Config

9.4.2.1 Single-Shot Mode and Power-Down

When the MODE bit in the Config register is set to 1, the ADS1118 enters a power-down state, and operates in

single-shot mode. This power-down state is the default state for the ADS1118 when power is first applied.

Although powered down, the device still responds to commands. The ADS1118 remains in this power-down state

until a 1 is written to the single-shot (SS) bit in the Config register. When the SS bit is asserted, the device

powers up, resets the SS bit to 0, and starts a single conversion. When conversion data are ready for retrieval,

the device powers down again. Writing a 1 to the SS bit while a conversion is ongoing has no effect. To switch to

continuous-conversion mode, write a 0 to the MODE bit in the Config register.

9.4.2.2 Continuous-Conversion Mode

In continuous-conversion mode (MODE bit set to 0), the ADS1118 continuously performs conversions. When a

conversion completes, the ADS1118 places the result in the Conversion register and immediately begins another

conversion. To switch to single-shot mode, write a 1 to the MODE bit in the Config register, or reset the device.

9.4.3 Duty Cycling for Low Power

The noise performance of a ΔΣ ADC generally improves when lowering the output data rate because more

samples of the internal modulator can be averaged to yield one conversion result. In applications where power

consumption is critical, the improved noise performance at low data rates may not be required. For these

applications, the ADS1118 supports duty cycling that can yield significant power savings by periodically

requesting high data rate readings at an effectively lower data rate. For example, an ADS1118 in power-down

state with a data rate set to 860 SPS can be operated by a microcontroller that instructs a single-shot conversion

every 125 ms (8 SPS). Because a conversion at 860 SPS only requires approximately 1.2 ms, the ADS1118

enters power-down state for the remaining 123.8 ms. In this configuration, the ADS1118 consumes

approximately 1/100th the power that is otherwise consumed in continuous conversion mode. The duty cycling

rate is completely arbitrary and is defined by the master controller. The ADS1118 offers lower data rates that do

not implement duty cycling and also offers improved noise performance if required.

l TEXAS INSTRUMENTS

CS(1)

SCLK

DOUT/DRDY

DIN

Hi-Z 8 µs

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9.5 Programming

9.5.1 Serial Interface

The SPI-compatible serial interface consists of either four signals (CS, SCLK, DIN, and DOUT/DRDY), or three

signals (in which case CS may be tied low). The interface is used to read conversion data, read and write

registers, and control device operation.

9.5.2 Chip Select (CS)

The chip select pin (CS) selects the ADS1118 for SPI communication. This feature is useful when multiple

devices share the same serial bus. Keep CS low for the duration of the serial communication. When CS is taken

high, the serial interface is reset, SCLK is ignored, and DOUT/DRDY enters a high-impedance state. In this state,

DOUT/DRDY cannot provide data-ready indication. In situations where multiple devices are present and

DOUT/DRDY must be monitored, lower CS periodically. At this point, the DOUT/DRDY pin either immediately

goes high to indicate that no new data are available, or immediately goes low to indicate that new data are

present in the Conversion register and are available for transfer. New data can be transferred at any time without

concern of data corruption. When a transmission starts, the current result is locked into the output shift register

and does not change until the communication completes. This system avoids any possibility of data corruption.

9.5.3 Serial Clock (SCLK)

The serial clock (SCLK) features a Schmitt-triggered input and is used to clock data on the DIN and

DOUT/DRDY pins into and out of the ADS1118. Even though the input has hysteresis, TI recommends keeping

SCLK as clean as possible to prevent glitches from accidentally shifting the data. If SCLK is held low for 28 ms,

the serial interface resets and the next SCLK pulse starts a new communication cycle. This time-out feature can

be used to recover communication when a serial interface transmission is interrupted. When the serial interface

is idle, hold SCLK low.

9.5.4 Data Input (DIN)

The data input pin (DIN) is used along with SCLK to send data to the ADS1118. The device latches data on DIN

on the SCLK falling edge. The ADS1118 never drives the DIN pin.

9.5.5 Data Output and Data Ready (DOUT/DRDY)

The data output and data ready pin (DOUT/DRDY) is used with SCLK to read conversion and register data from

the ADS1118. Data on DOUT/DRDY are shifted out on the SCLK rising edge. DOUT/DRDY is also used to

indicate that a conversion is complete and new data are available. This pin transitions low when new data are

ready for retrieval. DOUT/DRDY is also able to trigger a microcontroller to start reading data from the ADS1118.

In continuous-conversion mode, DOUT/DRDY transitions high again 8 µs before the next data ready signal

(DOUT/DRDY low) if no data are retrieved from the device. This transition is shown in Figure 38. Complete the

data transfer before DOUT/DRDY returns high.

(1) CS may be held low. If CS is low, DOUT/DRDY asserts low indicating new data are available.

Figure 38. DOUT/DRDY Behavior Without Data Retrieval in Continuous Conversion Mode

When CS is high, DOUT/DRDY is configured by default with a weak internal pullup resistor. This feature reduces

the risk of DOUT/DRDY floating near midsupply and causing leakage current in the master device. To disable

this pullup resistor and place the device into a high-impedance state, set the PULL_UP_EN bit to 0 in the Config

l TEXAS INSTRUMENTS

0x7FFF

OutputCode

-FS ¼0¼FS

InputVoltage(AIN AIN )-

P N

0x7FFE

0x0001

0x0000

0x8000

0xFFFF

0x8001

-FS

2-1

215 FS

2-1

215

ADS1118

SBAS457F –OCTOBER 2010–REVISED SEPTEMBER 2019

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Product Folder Links: ADS1118

Programming (continued)

9.5.6 Data Format

The ADS1118 provides 16 bits of data in binary twos complement format. A positive full-scale input produces an

output code of 7FFFh and a negative full-scale input produces an output code of 8000h. The output clips at these

codes for signals that exceed full-scale. Table 5 summarizes the ideal output codes for different input signals.

Figure 39 shows code transitions versus input voltage.

(1) Excludes the effects of noise, INL, offset, and gain errors.

Table 5. Input Signal versus Ideal Output Code

INPUT SIGNAL, VIN

(AINP– AINN)IDEAL OUTPUT CODE(1)

≥+FS (215 – 1)/215 7FFFh

+FS/215 0001h

0 0

–FS/215 FFFFh

≤–FS 8000h

Figure 39. ADS1118 Code Transition Diagram

9.5.7 Data Retrieval

Data is written to and read from the ADS1118 in the same manner for both single-shot and continuous

conversion modes, without having to issue any commands. The operating mode for the ADS1118 is selected by

the MODE bit in the Config register.

Set the MODE bit to 0 to put the device in continuous-conversion mode. In continuous-conversion mode, the

device is constantly starting new conversions even when CS is high.

Set the MODE bit to 1 for single-shot mode. In single-shot mode, a new conversion only starts by writing a 1 to

the SS bit.

The conversion data are always buffered, and retain the current data until replaced by new conversion data.

Therefore, data can be read at any time without concern of data corruption. When DOUT/DRDY asserts low,

indicating that new conversion data are ready, the conversion data are read by shifting the data out on

DOUT/DRDY. The MSB of the data (bit 15) on DOUT/DRDY is clocked out on the first SCLK rising edge. At the

same time that the conversion result is clocked out of DOUT/DRDY, new Config register data are latched on DIN

on the SCLK falling edge.

The ADS1118 also offers the possibility of direct readback of the Config register settings in the same data

transmission cycle. One complete data transmission cycle consists of either 32 bits (when the Config register

data readback is used) or 16 bits (only used when the CS line can be controlled and is not permanently tied low).

l TEXAS INSTRUMENTS ’ 7 W D * 4‘Cii7 x x w i X i 7 ’ 7 W D 7 4[:::7 X X X >’ >+ i X i 7 7 —\ !—| I— W D i 4‘CJ_/<:x:)c:d—c]_><:x:>C}

SCLK

DOUT/DRDY

DIN

Hi-Z

1 9

DATA MSB DATA LSB

CONFIG MSB CONFIG LSB

1 9

DATA MSB DATA LSB

CONFIG MSB CONFIG LSB

CS(1)

SCLK

DOUT/DRDY

DIN

Hi-Z

1 9 17 25

DATA MSB DATA LSB CONFIG MSB CONFIG LSB

CONFIG MSB CONFIG LSB

Next Data Ready

CS(1)

SCLK

DOUT/DRDY

DIN

Hi-Z

1 9 17 25

DATA MSB DATA LSB CONFIG MSB CONFIG LSB

CONFIG MSB CONFIG LSB CONFIG MSB CONFIG LSB

Next Data Ready

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9.5.7.1 32-Bit Data Transmission Cycle

The data in a 32-bit data transmission cycle consists of four bytes: two bytes for the conversion result, and an

additional two bytes for the Config Register read back. The device always reads the MSB first.

Write the same Config register setting twice during one transmission cycle as shown in Figure 40. If convenient,

write the Config register setting once during the first half of the transmission cycle, and then hold the DIN pin

either low (as shown in Figure 41) or high during the second half of the cycle. If no update to the Config register

is required, hold the DIN pin either low or high during the entire transmission cycle. The Config register setting

written in the first two bytes of a 32-bit transmission cycle is read back in the last two bytes of the same cycle.

(1) CS can be held low if the ADS1118 does not share the serial bus with another device. If CS is low, DOUT/DRDY

asserts low indicating new data are available.

Figure 40. 32-Bit Data Transmission Cycle With Config Register Readback

(1) CS can be held low if the ADS1118 does not share the serial bus with another device. If CS is low, DOUT/DRDY

asserts low indicating new data are available.

Figure 41. 32-Bit Data Transmission Cycle: DIN Held Low

9.5.7.2 16-Bit Data Transmission Cycle

If Config Register data are not required to be readback, the ADS1118 conversion data can also be clocked out in

a short 16-bit data transmission cycle, as shown in Figure 42. Therefore, CS must be taken high after the 16th

SCLK cycle. Taking CS high resets the SPI interface. The next time CS is taken low, data transmission starts

with the currently buffered conversion result on the first SCLK rising edge. If DOUT/DRDY is low when data

retrieval starts, the conversion buffer is already updated with a new result. Otherwise, if DOUT/DRDY is high, the

same result from the previous data transmission cycle is read.

Figure 42. 16-Bit Data Transmission Cycle

I TEXAS INSTRUMENTS

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9.6 Register Maps

The ADS1118 has two registers that are accessible through the SPI interface. The Conversion Register contains

the result of the last conversion. The Config Registerallows the user to change the ADS1118 operating modes

and query the status of the devices.

9.6.1 Conversion Register [reset = 0000h]

The 16-bit Conversion register contains the result of the last conversion in binary twos complement format.

Following power up, the Conversion register is cleared to 0, and remains 0 until the first conversion is completed.

The register format is shown in Figure 43.

Figure 43. Conversion Register

15 14 13 12 11 10 9 8

D15 D14 D13 D12 D11 D10 D9 D8

R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

76543210

D7 D6 D5 D4 D3 D2 D1 D0

R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. Conversion Register Field Descriptions

Bit Field Type Reset Description

15:0 D[15:0] R 0000h 16-bit conversion result

9.6.2 Config Register [reset = 058Bh]

The 16-bit Config register can be used to control the ADS1118 operating mode, input selection, data rate, full-

scale range, and temperature sensor mode. The register format is shown in Figure 44.

Figure 44. Config Register

15 14 13 12 11 10 9 8

SS MUX[2:0] PGA[2:0] MODE

R/W-0h R/W-0h R/W-2h R/W-1h

76543210

DR[2:0] TS_MODE PULL_UP_EN NOP[1:0] Reserved

R/W-4h R/W-0h R/W-1h R/W-1h R-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. Config Register Field Descriptions

Bit Field Type Reset Description

15 SS R/W 0h

Single-shot conversion start

This bit is used to start a single conversion. SS can only be written when in

power-down state and has no effect when a conversion is ongoing.

When writing:

0 = No effect

1 = Start a single conversion (when in power-down state)

Always reads back 0 (default).

14:12 MUX[2:0] R/W 0h

Input multiplexer configuration

These bits configure the input multiplexer.

000 = AINPis AIN0 and AINNis AIN1 (default)

001 = AINPis AIN0 and AINNis AIN3

010 = AINPis AIN1 and AINNis AIN3

011 = AINPis AIN2 and AINNis AIN3

100 = AINPis AIN0 and AINNis GND

101 = AINPis AIN1 and AINNis GND

110 = AINPis AIN2 and AINNis GND

111 = AINPis AIN3 and AINNis GND

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Table 7. Config Register Field Descriptions (continued)

Bit Field Type Reset Description

(1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V must be applied to this device.

11:9 PGA[2:0] R/W 2h

Programmable gain amplifier configuration

These bits configure the programmable gain amplifier.

000 = FSR is ±6.144 V(1)

001 = FSR is ±4.096 V(1)

010 = FSR is ±2.048 V (default)

011 = FSR is ±1.024 V

100 = FSR is ±0.512 V

101 = FSR is ±0.256 V

110 = FSR is ±0.256 V

111 = FSR is ±0.256 V

8 MODE R/W 1h

Device operating mode

This bit controls the ADS1118 operating mode.

0 = Continuous conversion mode

1 = Power-down and single-shot mode (default)

7:5 DR[2:0] R/W 4h

Data rate

These bits control the data rate setting.

000 = 8 SPS

001 = 16 SPS

010 = 32 SPS

011 = 64 SPS

100 = 128 SPS (default)

101 = 250 SPS

110 = 475 SPS

111 = 860 SPS

4 TS_MODE R/W 0h

Temperature sensor mode

This bit configures the ADC to convert temperature or input signals.

0 = ADC mode (default)

1 = Temperature sensor mode

3 PULL_UP_EN R/W 1h

Pullup enable

This bit enables a weak internal pullup resistor on the DOUT/DRDY pin only

when CS is high. When enabled, an internal 400-kΩresistor connects the bus

line to supply. When disabled, the DOUT/DRDY pin floats.

0 = Pullup resistor disabled on DOUT/DRDY pin

1 = Pullup resistor enabled on DOUT/DRDY pin (default)

2:1 NOP[1:0] R/W 1h

No operation

The NOP[1:0] bits control whether data are written to the Config register or not.

For data to be written to the Config register, the NOP[1:0] bits must be '01'. Any

other value results in a NOP command. DIN can be held high or low during SCLK

pulses without data being written to the Config register.

00 = Invalid data, do not update the contents of the Config register

01 = Valid data, update the Config register (default)

10 = Invalid data, do not update the contents of the Config register

11 = Invalid data, do not update the contents of the Config register

0 Reserved R 1h Reserved

Writing either 0 or 1 to this bit has no effect.

Always reads back 1.

l TEXAS INSTRUMENTS ﬂﬂﬂﬂ W—i

0.1 µF

VDD

DIN

DOUT

Microcontroller or

Microprocessor

with SPI Port

SCLK

GND

AIN0

AIN1

DIN

DOUT/DRDY

VDD

AIN3

AIN2

Device

Inputs Selected

from Configuration

SCLK

50 W

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The ADS1118 is a precision, 16-bit ΔΣ ADC that offers many integrated features to ease the measurement of the

most common sensor types including various type of temperature and bridge sensors. The following sections

give example circuits and suggestions for using the ADS1118 in various situations.

10.1.1 Serial Interface Connections

The principle serial interface connections for the ADS1118 are shown in Figure 45.

Figure 45. Typical Connections of the ADS1118

Most microcontroller SPI peripherals can operate with the ADS1118. The interface operates in SPI mode 1

where CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data are launched or changed only on

SCLK rising edges; data are latched or read by the master and slave on SCLK falling edges. Details of the SPI

communication protocol employed by the ADS1118 can be found in the Timing Requirements: Serial Interface

section.

It is a good practice to place 50-Ωresistors in the series path to each of the digital pins to provide some short

circuit protection. Care must be taken to still meet all SPI timing requirements because these additional series

resistors along with the bus parasitic capacitances present on the digital signal lines could slew the signals.

The fully-differential input of the ADS1118 is ideal for connecting to differential sources (such as thermocouples

and thermistors) with a moderately low source impedance. Although the ADS1118 can read fully-differential

signals, the device cannot accept negative voltages on either of its inputs because of ESD protection diodes on

each pin. When an input exceeds supply or drops below ground, these diodes turn on to prevent any ESD

damage to the device.

10.1.2 GPIO Ports for Communication

Most microcontrollers have programmable input/output (I/O) pins that can be set in software to act as inputs or

outputs. If an SPI controller is not available, the ADS1118 can be connected to GPIO pins and the SPI bus

protocol can be simulated. Using GPIO pins to generate the SPI interface only requires that the pins be

configured as push or pull inputs or outputs. Furthermore, if the SCLK line is held low for more than 28 ms, the

communication times out. This condition means that the GPIO ports must be capable of providing SCLK pulses

with no more than 28 ms between pulses.

Magnitude

f(MOD)/2 f(MOD)

Output

Data Rate

Frequency

External

Antialiasing Filter

Roll-Off

Magnitude

f(MOD)/2 f(MOD)

Output

Data Rate

Frequency

Digital Filter

Magnitude

f(MOD)/2 f(MOD)

Output

Data Rate

Frequency

Sensor

Signal

Unwanted

Signals

Unwanted

Signals

Aliasing of

Unwanted Signals

ADS1118

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Application Information (continued)

10.1.3 Analog Input Filtering

Analog input filtering serves two purposes: first, to limit the effect of aliasing during the sampling process and

second, to reduce external noise from being a part of the measurement.

As with any sampled system, aliasing can occur if proper antialias filtering is not in place. Aliasing occurs when

frequency components are present in the input signal that are higher than half the sampling frequency of the

ADC (also known as the Nyquist frequency). These frequency components fold back and show up in the actual

frequency band of interest below half the sampling frequency. The filter response of the digital filter repeats at

multiples of the sampling frequency, also known as the modulator frequency (f(MOD)), as shown in Figure 46.

Signals or noise up to a frequency where the filter response repeats are attenuated to a certain amount by the

digital filter depending on the filter architecture. Any frequency components present in the input signal around the

modulator frequency or multiples thereof are not attenuated and alias back into the band of interest, unless

attenuated by an external analog filter.

Figure 46. Effect of Aliasing

Many sensor signals are inherently bandlimited; for example, the output of a thermocouple has a limited rate of

change. In this case, the sensor signal does not alias back into the pass-band when using a ΔΣ ADC. However,

any noise pick-up along the sensor wiring or the application circuitry can potentially alias into the pass-band.

Power line-cycle frequency and harmonics are one common noise source. External noise can also be generated

from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors

and cellular phones. Another noise source typically exists on the printed-circuit-board (PCB) itself in the form of

clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the

measurement result.

l TEXAS INSTRUMENTS

0.1 µF

VDD

SCLK

GND

AIN0

AIN1

DIN

DOUT/DRDY

VDD

AIN3

AIN2

Device

Inputs Selected

from Configuration

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Application Information (continued)

A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either totally eliminate aliasing, or to

reduce the effect of aliasing to a level within the noise floor of the sensor. Ideally, any signal beyond f(MOD) / 2 is

attenuated to a level below the noise floor of the ADC. The digital filter of the ADS1118 attenuates signals to a

certain degree, as shown in Figure 34. In addition, noise components are usually smaller in magnitude than the

actual sensor signal. Therefore, using a first-order RC filter with a cutoff frequency set at the output data rate or

10x higher is generally a good starting point for a system design.

10.1.4 Single-Ended Inputs

Although the ADS1118 has two differential inputs, the device can measure four single-ended signals. Figure 47

shows a single-ended connection scheme. The ADS1118 is configured for single-ended measurement by

configuring the MUX to measure each channel with respect to ground. Data are then read out of one input based

on the selection in the Config Register. The single-ended signal can range from 0 V up to positive supply or +FS,

whichever is lower. Negative voltages cannot be applied to this circuit because the ADS1118 can only accept

positive voltages with respect to ground. The ADS1118 does not lose linearity within the input range.

The ADS1118 offers a differential input voltage range of ±FS. The single-ended circuit shown in Figure 47

however only uses the positive half of the ADS1118 FS input voltage range because differentially negative inputs

are not produced. Because only half of the FS range is used, one bit of resolution is lost. For optimal noise

performance, TI recommends using differential configurations whenever possible. Differential configurations

maximize the dynamic range of the ADC and provide strong attenuation of common-mode noise.

NOTE: Digital pin connections omitted for clarity.

Figure 47. Measuring Single-Ended Inputs

The ADS1118 is also designed to allow AIN3 to serve as a common point for measurements by adjusting the

mux configuration. AIN0, AIN1, and AIN2 can all be measured with respect to AIN3. In this configuration the

ADS1118 can operate with inputs where AIN3 serves as the common point. This ability improves the usable

range over the single-ended configuration because negative differential voltages are allowed when GND < V(AIN3)

< VDD; however, common-mode noise attenuation is not offered.

‘5‘ TEXAS INSTRUMENTS

SCLK

DIN

DOUT

CS1

CS2

DIN

DOUT/DRDY

VDD

AIN3

AIN2

AIN1

AIN0

GND

SCLK

DIN

DOUT/DRDY

VDD

AIN3

AIN2

AIN1

AIN0

GND

SCLK

Device

Microcontroller or

Microprocessor

50 W

ADS1118

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Application Information (continued)

10.1.5 Connecting Multiple Devices

When connecting multiple ADS1118 devices to a single SPI bus, SCLK, DIN, and DOUT/DRDY can be safely

shared by using a dedicated chip-select (CS) for each SPI-enabled device. By default, when CS goes high for

the ADS1118, DOUT/DRDY is pulled up to VDD by a weak pullup resistor. This feature is intended to prevent

DOUT/DRDY from floating near mid-rail and causing excess current leakage on a microcontroller input. If the

PULL_UP_EN bit in the Config Register is set to 0, the DOUT/DRDY pin enters a 3-state mode when CS

transitions high. The ADS1118 cannot issue a data ready pulse on DOUT/DRDY when CS is high. To evaluate

when a new conversion is ready from the ADS1118 when using multiple devices, the master can periodically

drop CS to the ADS1118. When CS goes low, the DOUT/DRDY pin immediately drives either high or low. If the

DOUT/DRDY line drives low on a low CS, new data are currently available for clocking out at any time. If the

DOUT/DRDY line drives high, no new data are available and the ADS1118 returns the last read conversion

result. Valid data can be retrieved from the ADS1118 at anytime without concern of data corruption. If a new

conversion becomes available during data transmission, that conversion is not available for readback until a new

SPI transmission is initiated.

NOTE: Power and input connections omitted for clarity.

Figure 48. Connecting Multiple ADS1118s

l TEXAS INSTRUMENTS NO YES

INITIALIZE POWER DOWNDATA CAPTURE

YES

Configure microcontroller SPI interface to SPI

mode 1 (CPOL = 0, CPHA = 1);

If the pin is not tied low permanently,CS

configure the microcontroller GPIO connected

to as an output;CS

Configure the microcontroller GPIO connected

to the pin as a falling edge triggeredDRDY

interrupt input;

Set to the device low;CS

Write the config register to set the device to

FSR = ±0.512 V, continuous conversion

mode, data rate = 64 SPS

Clear to high to reset the serial interfaceCS

Power-up; Wait for supplies to settle to

nominal to ensure power-up reset is complete;

Wait for 50 µs

Take lowCS

Read out conversion result

and clear CS to high before

Delay for minimum td(CSSC)

Take lowCS

Set MODE bit in config register to '1'

to enter power-down and single-shot

mode

Clear to highCS

Wait for DOUT/

DRDY to transition

low

Delay for minimum td(CSSC)

DOUT/ goes low againDRDY

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Application Information (continued)

10.1.6 Pseudo Code Example

The flow chart in Figure 49 shows a pseudo code sequence with the required steps to set up communication

between the device and a microcontroller to take subsequent readings from the ADS1118. As an example, the

default Config Register settings are changed to set up the device in FSR = ±0.512 V, continuous conversion

mode and 64-SPS data rate.

Figure 49. Pseudo Code Example Flow Chart

l TEXAS INSTRUMENTS 33v

Digital Filter

and

Interface

Oscillator

Voltage Reference

Temperature

Sensor

Mux PGA 16-bit

ûADC

±256-mV FSR

AIN0

AIN1

SCLK

VDD

GND

DOUT/DRDY

DIN

ADS1118

GND

GND 0.1 F

AIN2

AIN3

GND

3.3 V

RPU

1 M

CCMA

0.1 F

RDIFFA

500 

RPD

1 MCCMB

0.1 F

RDIFFB

500 

1 F

GND

3.3 V

RPU

1 M

CCMA

0.1 F

RDIFFA

500 

RPD

1 MCCMB

0.1 F

RDIFFB

500 

1 F

3.3 V

ADS1118

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10.2 Typical Application

Figure 50 shows the basic connections for an independent, two-channel thermocouple measurement system

when using the internal high-precision temperature sensor for cold-junction compensation. Apart from the

thermocouples, the only external circuitry required are biasing resistors, first order low-pass, anti-aliasing filters,

and a power supply decoupling capacitor.

Figure 50. Two-Channel Thermocouple Measurement System

10.2.1 Design Requirements

Table 8 shows the design parameters for this application.

(1) With offset calibration, and no gain calibration. Measurement does not account for thermocouple

inaccuracy.

Table 8. Design Parameters

DESIGN PARAMETER VALUE

Supply voltage 3.3 V

Reference voltage Internal

Update rate ≥100 readings per second

Thermocouple type K

Temperature measurement range –200°C to +1250°C

Measurement accuracy at TA= 25°C(1) ±0.7°C

10.2.2 Detailed Design Procedure

The biasing resistors (RPU and RPD) serve two purposes. The first purpose is to set the common-mode voltage of

the thermocouple to within the specified voltage range of the device. The second purpose is to offer a weak

pullup and pulldown to detect an open thermocouple lead. When one of the thermocouple leads fails open, the

positive input will be pulled to VDD and the negative input will be pulled to GND. The ADC consequently reads a

full-scale value, which is outside the normal measurement range of the thermocouple voltage, to indicate this

failure condition. When choosing the values of the biasing resistors, care must be taken so that the biasing

current does not degrade measurement accuracy. The biasing current flows through the thermocouple and can

cause self-heating and additional voltage drops across the thermocouple leads. Typical values for the biasing

resistors range from 1 MΩto 50 MΩ.

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Although the device digital filter attenuates high-frequency components of noise, TI recommends providing a first-

order, passive RC filter at the inputs to further improve performance. The differential RC filter formed by RDIFFA,

RDIFFB, and the differential capacitor CDIFF offers a cutoff frequency that is calculated using Equation 5. While the

digital filter of the ADS1118 strongly attenuates high-frequency components of noise, TI recommends to provide

a first-order, passive RC filter to further suppress high-frequency noise and avoid aliasing. Care must be taken

when choosing the filter resistor values because the input currents flowing into and out of the device cause a

voltage drop across the resistors. This voltage drop shows up as an additional offset error at the ADC inputs. TI

recommends limiting the filter resistor values to below 1 kΩ.

fC= 1 / [2π· (RDIFFA + RDIFFB) · CDIFF] (5)

Two common-mode filter capacitors (CCMA and CCMB) are also added to offer attenuation of high-frequency,

common-mode noise components. TI recommends that the differential capacitor CDIFF be at least an order of

magnitude (10x) larger than these common-mode capacitors because mismatches in the common-mode

capacitors can convert common-mode noise into differential noise.

The highest measurement resolution is achieved when the largest potential input signal is slightly lower than the

FSR of the ADC. From the design requirement, the maximum thermocouple voltage (VTC) occurs at a

thermocouple temperature (TTC) of 1250°C. At this temperature, VTC = 50.644 mV, as defined in the tables

published by the National Institute of Standards and Technology (NIST) using a cold-junction temperature (TCJ)

of 0°C. A thermocouple produces an output voltage that is proportional to the temperature difference between the

thermocouple tip and the cold junction. If the cold junction is at a temperature below 0°C, the thermocouple

produces a voltage larger than 50.644 mV. The isothermal block area is constrained by the operating

temperature range of the device. Therefore, the isothermal block temperature is limited to –40°C. A K-type

thermocouple at TTC = 1250°C produces an output voltage of VTC = 50.644 mV – (–1.527 mV) = 52.171 mV

when referenced to a cold-junction temperature of TCJ = –40°C. The device offers a full-scale range of ±0.256 V

and that is what is used in this application example.

The device integrates a high-precision temperature sensor that can be used to measure the temperature of the

cold junction. The temperature sensor mode is enabled by setting bit TS_MODE = 1 in the Config register. The

accuracy of the overall temperature sensor depends on how accurately the ADS1118 can measure the cold

junction, and hence, careful component placement and PCB layout considerations must be employed for

designing an accurate thermocouple system. The ADS1118 Evaluation Module provides a good starting point

and offers an example to achieve good cold-junction compensation performance. The ADS1118 Evaluation

Module uses the same schematic as shown in Figure 50, except with only one thermocouple channel connected.

Refer to the application note, Precision Thermocouple Measurement With the ADS1118,SBAA189, for details on

how to optimize your component placement and layout to achieve good cold-junction compensation performance.

The calculation procedure to achieve cold-junction compensation can be done in several ways. A typical way is

to interleave readings between the thermocouple inputs and the temperature sensor. That is, acquire one on-chip

temperature result, TCJ, for every thermocouple ADC voltage measured, VTC. To account for the cold junction,

first convert the temperature sensor reading within the ADS1118 to a voltage (VCJ) that is proportional to the

thermocouple currently being used. This process is generally accomplished by performing a reverse lookup on

the table used for the thermocouple voltage-to-temperature conversion. Adding these two voltages yields the

thermocouple-compensated voltage (VActual), where VActual = VCJ + VTC. VActual is then converted to a temperature

(TActual) using the same NIST lookup table. A block diagram showing this process is given in Figure 51. Refer to

the application note, Precision Thermocouple Measurement With the ADS1118,SBAA189, for a detailed

explanation of this method.

l TEXAS INSTRUMENTS 0m 06

Thermocouple Voltage (mV)

Measurement Error (mV)

-10 0 10 20 30 40 50 60

-0.01

-0.005

0.005

0.01

Temperature (qC)

Measurement Error (qC)

-200 0 200 400 600 800 1000 1200 1400

-0.6

-0.4

-0.2

0.2

0.4

0.6

Thermocouple

Voltage

On-chip

Temperature 

T Æ V V Æ T Result

Device MCU

VTC

TCJ VCJ VActual

TActual

ADS1118

www.ti.com

SBAS457F –OCTOBER 2010–REVISED SEPTEMBER 2019

Product Folder Links: ADS1118

Figure 51. Software Flow Block Diagram

Figure 52 and Figure 53 show the measurement results. The measurements are taken at TA= TCJ = 25°C. A

system offset calibration is performed at TTC = 25°C that equates to VTC = 0 V when TCJ = 25°C. No gain

calibration was performed during the measurements. The data in Figure 52 are taken using a precision voltage

source as the input signal instead of a thermocouple. The solid black line in Figure 53 is the respective

temperature measurement error and is calculated from the data in Figure 52 using the NIST tables. The solid

black line in Figure 53 is the measurement error due to the ADC gain and nonlinearity error. The dashed blue

lines in Figure 53 include the guard band for the temperature sensor inaccuracy (±0.5°C), in addition to the

device gain and nonlinearity error. Note that the measurement results in Figure 52 and Figure 53 do not account

for the thermocouple inaccuracy that must also be considered while designing a thermocouple measurement

system.

10.2.3 Application Curves

Figure 52. Voltage Measurement Error vs VTC Figure 53. Temperature Measurement Error vs TTC

l TEXAS INSTRUMENTS mp

0.1 µF

VDD

SCLK

GND

AIN0

AIN1

DIN

DOUT/DRDY

VDD

AIN3

AIN2

Device

ADS1118

SBAS457F –OCTOBER 2010–REVISED SEPTEMBER 2019

www.ti.com

Product Folder Links: ADS1118

11 Power Supply Recommendations

The device requires a single power supply, VDD, to power both the analog and digital circuitry of the device.

11.1 Power-Supply Sequencing

Wait approximately 50 µs after VDD is stabilized before communicating with the device to allow the power-up

reset process to complete.

11.2 Power-Supply Decoupling

Good power-supply decoupling is important to achieve optimum performance. VDD must be decoupled with at

least a 0.1-µF capacitor, as shown in Figure 54. The 0.1-μF bypass capacitor supplies the momentary bursts of

extra current required from the supply when the ADS1118 is converting. Place the bypass capacitor as close to

the power-supply pin of the device as possible using low-impedance connections. TI recommends using multi-

layer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL)

characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise

environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noise

immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to

ground planes.

Figure 54. Power Supply Decoupling

l TEXAS INSTRUMENTS

Device Microcontroller

Signal

Conditioning

(RC Filters

and

Amplifiers)

Supply

Generation

Connector

or Antenna

Ground Fill or

Ground Plane

Optional: Split

Ground Cut

Ground Fill or

Ground Plane

Optional: Split

Ground Cut

Interface

Transceiver

Ground Fill or

Ground Plane

Ground Fill or

Ground Plane

ADS1118

www.ti.com

SBAS457F –OCTOBER 2010–REVISED SEPTEMBER 2019

Product Folder Links: ADS1118

12 Layout

12.1 Layout Guidelines

TI recommends employing best design practices when laying out a printed-circuit-board (PCB) for both analog

and digital components. This recommendation generally means that the layout separates analog components

[such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital

components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate

arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching

regulators]. An example of good component placement is shown in Figure 55. Although Figure 55 provides a

good example of component placement, the best placement for each application is unique to the geometries,

components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every

design and careful consideration must always be used when designing with any analog component.

Figure 55. System Component Placement

The use of split analog and digital ground planes is not necessary for improved noise performance (although for

thermal isolation this option is a worthwhile consideration). However, the use of a solid ground plane or ground

fill in PCB areas with no components is essential for optimum performance. If the system being used employs a

split digital and analog ground plane, TI generally recommends that the ground planes be connected together as

close to the device as possible. A two-layer board is possible using common grounds for both analog and digital

grounds. Additional layers can be added to simplify PCB trace routing. Ground fill may also reduce EMI and RFI

issues.

TI also strongly recommends that digital components, especially RF portions, be kept as far as practically

possible from analog circuitry in a given system. Additionally, minimize the distance that digital control traces run

through analog areas and avoid placing these traces near sensitive analog components. Digital return currents

usually flow through a ground path that is as close to the digital path as possible. If a solid ground connection to

a plane is not available, these currents may find paths back to the source that interfere with analog performance.

The implications that layout has on the temperature-sensing functions are much more significant than for ADC

functions.

Supply pins must be bypassed to ground with a low-ESR ceramic capacitor. The optimum placement of the

bypass capacitors is as close as possible to the supply pins. The ground-side connections of the bypass

capacitors must be low-impedance connections for optimum performance. The supply current flows through the

bypass capacitor terminal first and then to the supply pin to make the bypassing most effective.

Analog inputs with differential connections must have a capacitor placed differentially across the inputs. The

differential capacitors must be of high quality. The best ceramic chip capacitors are C0G (NPO), which have

stable properties and low noise characteristics. Thermally isolate a copper region around the thermocouple input

connections to create a thermally-stable cold junction. Obtaining acceptable performance with alternate layout

schemes is possible as long as the above guidelines are followed.

‘5‘ TEXAS INSTRUMENTS IIIIIIIIIIIIIIIIIIIIIIIIII

SCLK

AIN0

DOUT/

DRDY

VDD

AIN3

AIN2

SCLK

DIN

VDD

Device

AIN3

AIN0

AIN1

GND

AIN2

AIN1

DIN

DOUT/DRDY

SCLK

DIN

DOUT/DRDY

Vias connect to either the bottom layer or

an internal plane. The bottom layer or

internal plane are dedicated GND planes

SCLK

AIN0 AIN1

DIN DOUT/

DRDY

VDD

AIN3

AIN2

GND

Device

AIN3

AIN2

VDD

AIN0

AIN1

ADS1118

SBAS457F –OCTOBER 2010–REVISED SEPTEMBER 2019

www.ti.com

Product Folder Links: ADS1118

12.2 Layout Example

Figure 56. X2QFN Package

Figure 57. VSSOP Package

l TEXAS INSTRUMENTS

ADS1118

www.ti.com

SBAS457F –OCTOBER 2010–REVISED SEPTEMBER 2019

Product Folder Links: ADS1118

13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Precision Thermocouple Measurement with the ADS1118 application report

• Texas Instruments, ADS1118EVM User Guide and Software Tutorial user guide

• Texas Instruments, 430BOOST-ADS1118 Booster Pack user' guide

• Texas Instruments, ADS1118 Boosterpack quick start

• Texas Instruments, A Glossary of Analog-to-Digital Specifications and Performance Characteristics

application report

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

13.3 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.4 Trademarks

E2E is a trademark of Texas Instruments.

SPI is a trademark of Motorola.

All other trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

TEXAS INSTRUMENTS Samples Sample: Sample: Samples

PACKAGE OPTION ADDENDUM

www.ti.com 25-Aug-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ADS1118IDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 BBEI

ADS1118IDGST ACTIVE VSSOP DGS 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 BBEI

ADS1118IRUGR ACTIVE X2QFN RUG 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SDQ

ADS1118IRUGT ACTIVE X2QFN RUG 10 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SDQ

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 25-Aug-2021

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF ADS1118 :

•Automotive : ADS1118-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«m» Reel Diameter AD Dimension deswgned to accommodate the componem wwdlh ED Dimension desxgned to accommodate the componenl \engm K0 Dimenslun deswgned to accommodate the componem thickness , w OveraH wwdm loe earner cape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D Sprockemules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADS1118IDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

ADS1118IDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

ADS1118IRUGR X2QFN RUG 10 3000 179.0 8.4 1.75 2.25 0.65 4.0 8.0 Q1

ADS1118IRUGT X2QFN RUG 10 250 179.0 8.4 1.75 2.25 0.65 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Aug-2021

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS1118IDGSR VSSOP DGS 10 2500 367.0 367.0 38.0

ADS1118IDGST VSSOP DGS 10 250 213.0 191.0 35.0

ADS1118IRUGR X2QFN RUG 10 3000 200.0 183.0 25.0

ADS1118IRUGT X2QFN RUG 10 250 200.0 183.0 25.0

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Aug-2021

Pack Materials-Page 2

DGSOO10A I

www.ti.com

PACKAGE OUTLINE

TYP

5.05

4.75

1.1 MAX

8X 0.5

10X 0.27

0.17

0.15

0.05

TYP

0.23

0.13

0 - 8

0.25

GAGE PLANE

0.7

0.4

NOTE 3

3.1

2.9

NOTE 4

3.1

2.9

4221984/A 05/2015

VSSOP - 1.1 mm max heightDGS0010A

SMALL OUTLINE PACKAGE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA.

110

0.1 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 3.200

DGSOO10A

www.ti.com

EXAMPLE BOARD LAYOUT

(4.4)

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

10X (1.45)

10X (0.3)

8X (0.5)

(R )

TYP

0.05

4221984/A 05/2015

VSSOP - 1.1 mm max heightDGS0010A

SMALL OUTLINE PACKAGE

SYMM

LAND PATTERN EXAMPLE

SCALE:10X

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

DGSOO10A

www.ti.com

EXAMPLE STENCIL DESIGN

(4.4)

8X (0.5)

10X (0.3)

10X (1.45)

(R ) TYP0.05

4221984/A 05/2015

VSSOP - 1.1 mm max heightDGS0010A

SMALL OUTLINE PACKAGE

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

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Datenblatt für ADS1118 von Texas Instruments

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