Datenblatt für MC(10,100)EP08 von onsemi

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0N Semiconductor® www.0nsemi.com Q as HHHH BEBE I— o. HHHH 153% FREE HERE I— o. HHHH ‘E'E'E'E "Fol addmiona‘ marking \nfolma ANDBDOZ/D sow—a N B (Pb-Fleel TSSOP-E (Pb-Free) For inlormation on tape and ye includmg part orientalion and refer «0 our Tape and Reel P lions Brochure, BRDSOn/D

April, 2021 − Rev. 8

1Publication Order Number:

MC10EP08/D

3.3 V/5 V ECL 2-Input

Differential XOR/XNOR

MC10EP08, MC100EP08

Description

The MC10/100EP08 is a differential XOR/XNOR gate. The EP08 is

ideal for applications requiring the fastest AC performance available.

The 100 Series contains temperature compensation.

Features

•250 ps Typical Propagation Delay

•Maximum Frequency = > 3 GHz Typical

•PECL Mode Operating Range:

VCC = 3.0 V to 5.5 V with VEE = 0 V

•NECL Mode Operating Range:

VCC = 0 V with VEE = −3.0 V to −5.5 V

•Open Input Default State

•Safety Clamp on Inputs

•Q Output Will Default LOW with Inputs Open or at VEE

•These Devices are Pb-Free, Halogen Free and are RoHS Compliant

www.onsemi.com

SOIC−8 NB

D SUFFIX

CASE 751−07

MARKING DIAGRAMS*

TSSOP−8

DT SUFFIX

CASE 948R−02

ALYWG

HP08

ALYWG

KP082

*For additional marking information, refer to

Application Note AND8002/D.

HEP08

ALYW

KEP01

ALYW

(Note: Microdot may be in either location)

SOIC−8 NB TSSOP−8

Y = Year

W = Work Week

G= Pb-Free Package

H = MC10

K = MC100

Device Package Shipping†

ORDERING INFORMATION

MC10EP08DG SOIC−8 NB

(Pb-Free)

98 Units / Tube

MC10EP08DR2G SOIC−8 NB

(Pb-Free)

2500 /

Tape & Reel

MC10EP08DTG TSSOP−8

(Pb-Free)

100 Units / Tube

MC100EP08DG SOIC−8 NB

(Pb-Free)

98 Units / Tube

MC100EP08DTG TSSOP−8

(Pb-Free)

100 Units / Tube

TSSOP−8

(Pb-Free)

2500 /

Tape & Reel

MC100EP08DTR2G

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifica-

tions Brochure, BRD8011/D.

A = Assembly Location

L = Wafer Lot

l—H- W 81 WWW & For addmonal mformauon, see Appncanon Note AN DBOOSLD

MC10EP08, MC100EP08

www.onsemi.com

VEE

VCC

Figure 1. 8-Lead Pinout (Top View) and Logic Diagram

QD1

Table 1. PIN DESCRIPTION

D0, D1, D0, D1

Q, Q ECL Data Outputs

FUNCTION

ECL Data Inputs

D0* D1* D0** D1** Q Q

LLHHLH

L HHL HL

H LLH HL

H HLL LH

Table 2. TRUTH TABLE

VCC

VEE

Positive Supply

Negative Supply

* Pins will default LOW when left open.

** Pins will default to 0.666% of VCC when left open.

Table 3. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor 75 kW

Internal Input Pullup Resistor 37.5 kW

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 4 kV

> 200 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg

SOIC−8 NB

TSSOP−8

Level 1

Level 3

Flammability Rating

Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 135 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

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MC10EP08, MC100EP08

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Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC PECL Mode Power Supply VEE = 0 V 6 V

VEE NECL Mode Power Supply VCC = 0 V −6 V

VIPECL Mode Input Voltage

NECL Mode Input Voltage

VEE = 0 V

VCC = 0 V

VI ≤ VCC

VI ≥ VEE

−6

Iout Output Current Continuous

Surge

100

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm

500 lfpm

SOIC−8 NB

190

130

°C/W

qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W

qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm

500 lfpm

TSSOP−8

185

140

°C/W

qJC Thermal Resistance (Junction-to-Case) Standard Board TSSOP−841 to 44 °C/W

Tsol Wave Solder (Pb-Free) < 2 to 3 sec @ 260°C 265 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

Table 5. 10EP DC CHARACTERISTICS, PECL (VCC = 3.3 V, VEE = 0 V (Note 1))

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 20 28 36 20 30 38 20 32 38 mA

VOH Output HIGH Voltage (Note 2) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV

VOL Output LOW Voltage (Note 2) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV

VIH Input HIGH Voltage (Single-Ended) 2090 2415 2155 2480 2215 2540 mV

VIL Input LOW Voltage (Single-Ended) 1365 1690 1430 1755 1490 1815 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration) (Note 3)

2.0 3.3 2.0 3.3 2.0 3.3 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current

0.5

−150

0.5

−150

0.5

−150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.

2. All loading with 50 W to VCC − 2.0 V.

3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

MC10EP08, MC100EP08

www.onsemi.com

Table 6. 10EP DC CHARACTERISTICS, PECL (VCC = 5.0 V, VEE = 0 V (Note 1))

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 20 28 36 20 30 38 20 32 38 mA

VOH Output HIGH Voltage (Note 2) 3865 3940 4115 3930 4055 4180 3990 4115 4240 mV

VOL Output LOW Voltage (Note 2) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV

VIH Input HIGH Voltage (Single-Ended) 3790 4115 3855 4180 3915 4240 mV

VIL Input LOW Voltage (Single-Ended) 3065 3390 3130 3455 3190 3515 mV

VIHCMR Input HIGH Voltage Common Mode Range

(Differential Configuration) (Note 3)

2.0 5.0 2.0 5.0 2.0 5.0 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current

0.5

−150

0.5

−150

0.5

−150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.

2. All loading with 50 W to VCC − 2.0 V.

3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Table 7. 10EP DC CHARACTERISTICS, NECL (VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 1))

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 20 28 36 20 30 38 20 32 38 mA

VOH Output HIGH Voltage (Note 2) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV

VOL Output LOW Voltage (Note 2) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV

VIH Input HIGH Voltage (Single-Ended) −1210 −885 −1145 −820 −1085 −760 mV

VIL Input LOW Voltage (Single-Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 3)

VEE + 2.0 0.0 VEE + 2.0 0.0 VEE + 2.0 0.0 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current

0.5

−150

0.5

−150

0.5

−150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Input and output parameters vary 1:1 with VCC.

2. All loading with 50 W to VCC − 2.0 V.

3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

MC10EP08, MC100EP08

www.onsemi.com

Table 8. 100EP DC CHARACTERISTICS, PECL (VCC = 3.3 V, VEE = 0 V (Note 1))

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 20 28 36 20 30 38 20 32 40 mA

VOH Output HIGH Voltage (Note 2) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV

VOL Output LOW Voltage (Note 2) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV

VIH Input HIGH Voltage (Single-Ended) 2075 2420 2075 2420 2075 2420 mV

VIL Input LOW Voltage (Single-Ended) 1355 1675 1355 1675 1355 1675 mV

VIHCMR Input HIGH Voltage Common Mode Range

(Differential Configuration) (Note 3)

2.0 3.3 2.0 3.3 2.0 3.3 V

IIH Input HIGH Current 150 150 150 mA

IIL put LOW Current

0.5

−150

0.5

−150

0.5

−150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.

2. All loading with 50 W to VCC − 2.0 V.

3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Table 9. 100EP DC CHARACTERISTICS, PECL (VCC = 5.0 V, VEE = 0 V (Note 1))

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 20 28 36 20 30 38 20 32 40 mA

VOH Output HIGH Voltage (Note 2) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV

VOL Output LOW Voltage (Note 2) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV

VIH Input HIGH Voltage (Single-Ended) 3775 4120 3775 4120 3775 4120 mV

VIL Input LOW Voltage (Single-Ended) 3055 3375 3055 3375 3055 3375 mV

VIHCMR Input HIGH Voltage Common Mode Range

(Differential Configuration) (Note 3)

2.0 5.0 2.0 5.0 2.0 5.0 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current

0.5

−150

0.5

−150

0.5

−150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.

2. All loading with 50 W to VCC − 2.0 V.

3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Propagauon De ompm Dweren D‘ mo Q U Cum 0‘ U

MC10EP08, MC100EP08

www.onsemi.com

Table 10. 100EP DC CHARACTERISTICS, NECL (VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 1))

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 20 28 36 20 30 38 20 32 40 mA

VOH Output HIGH Voltage (Note 2) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV

VOL Output LOW Voltage (Note 2) −1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV

VIH Input HIGH Voltage (Single-Ended) −1225 −880 −1225 −880 −1225 −880 mV

VIL Input LOW Voltage (Single-Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 3)

VEE + 2.0 0.0 VEE + 2.0 0.0 VEE + 2.0 0.0 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current

0.5

−150

0.5

−150

0.5

−150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Input and output parameters vary 1:1 with VCC.

2. All loading with 50 W to VCC − 2.0 V.

3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Table 11. AC CHARACTERISTICS (VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 1))

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

fmax Maximum Frequency (Figure 2) > 3 > 3 > 3 GHz

tPLH,

tPHL

Propagation Delay to

Output Differential

D, D to Q, Q 170 220 280 180 250 300 200 270 320

tJITTER Cycle-to-Cycle Jitter (Figure 2) 0.2 < 1 0.2 < 1 0.2 < 1 ps

VPP Input Voltage Swing

(Differential Configuration)

150 800 1200 150 800 1200 150 800 1200 mV

Output Rise/Fall Times

Q, Q (20%−80%) 70 120 170 80 130 180 100 150 200

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.

V 4 1 00 1 (J ITTER) 0 x 0 1000 2000 3000 4000 5000 6000 FHEQUENCY (MHzi Figure 2. Fmax/Jiller (See Application Note ANDaozozD www.cnsemi.com 7

MC10EP08, MC100EP08

www.onsemi.com

100

200

300

400

500

600

700

800

900

0 1000 2000 3000 4000 5000 6000

Figure 2. Fmax/Jitter

FREQUENCY (MHz)

(JITTER)

VOUTpp (mV)

JITTEROUT ps (RMS)

Figure 3. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices)

Driver

Device

Receiver

Device

Q D

Zo = 50 W

50 W50 W

VTT

VTT = VCC − 2.0 V

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MC10EP08, MC100EP08

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Resource Reference of Application Notes

AN1405/D −ECL Clock Distribution Techniques

AN1406/D −Designing with PECL (ECL at +5.0 V)

AN1503/D −ECLinPSt I/O SPiCE Modeling Kit

AN1504/D −Metastability and the ECLinPS Family

AN1568/D −Interfacing Between LVDS and ECL

AN1642/D −The ECL Translator Guide

AND8001/D −Odd Number Counters Design

AND8002/D −Marking and Date Codes

AND8020/D −Termination of ECL Logic Devices

AND8066/D −Interfacing with ECLinPS

AND8090/D −AC Characteristics of ECL Devices

ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

0N Semiwndudw" m @ HHHH HHHH HHHH HERE 4 FUDGE] !HHH !HHH gHHH EHHH 1 1 } x ‘ 1 (...... a. ............. ... ......M .. SW. CW ........ .. ... 0. SW .. W- .. ...... ...... ...... ...... 0. SW ...... ... .... .. .... ...... ...... .. ... ...... ...... o. ......m... .. ...... .. ...... ...... ... 5...... .. .. ...... ... .. ...... a. s............ ...... ... ...... ...... ...... .....w... .. .. ... ...... ......w... ....-. ... ... ... ...... ...... ...... ...... ...5......... .. ...... ...... o. 5.--.-. .... ...... ... ...... ...... .... ..............

SOIC−8 NB

CASE 751−07

ISSUE AK

DATE 16 FEB 2011

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

SCALE 1:1

STYLES ON PAGE 2

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

XXXXX = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

GENERIC

MARKING DIAGRAM*

XXXXX

ALYWX

IC Discrete

XXXXXX

AYWW

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

Discrete

XXXXXX

AYWW

(Pb−Free)

XXXXX

ALYWX

(Pb−Free)

XXXXXX = Specific Device Code

A = Assembly Location

Y = Year

WW = Work Week

G= Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB42564B

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

SOIC−8 NB

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SOIC−8 NB

CASE 751−07

ISSUE AK

DATE 16 FEB 2011

STYLE 4:

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

8. COMMON CATHODE

STYLE 1:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

7. BASE

8. EMITTER

STYLE 2:

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

6. EMITTER, #2

7. BASE, #1

8. EMITTER, #1

STYLE 3:

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. GATE, #1

8. SOURCE, #1

STYLE 6:

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

STYLE 5:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

6. GATE

7. SOURCE

8. SOURCE

STYLE 7:

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

3. BASE, #2

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

STYLE 9:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 10:

PIN 1. GROUND

2. BIAS 1

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

STYLE 11:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 15:

PIN 1. ANODE 1

2. ANODE 1

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

5. RXE

6. VEE

7. GND

8. ACC

STYLE 18:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

STYLE 19:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. MIRROR 2

7. DRAIN 1

8. MIRROR 1

STYLE 20:

PIN 1. SOURCE (N)

2. GATE (N)

3. SOURCE (P)

4. GATE (P)

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 21:

PIN 1. CATHODE 1

2. CATHODE 2

3. CATHODE 3

4. CATHODE 4

5. CATHODE 5

6. COMMON ANODE

7. COMMON ANODE

8. CATHODE 6

STYLE 22:

PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC

3. COMMON CATHODE/VCC

4. I/O LINE 3

5. COMMON ANODE/GND

6. I/O LINE 4

7. I/O LINE 5

8. COMMON ANODE/GND

STYLE 23:

PIN 1. LINE 1 IN

2. COMMON ANODE/GND

3. COMMON ANODE/GND

4. LINE 2 IN

5. LINE 2 OUT

6. COMMON ANODE/GND

7. COMMON ANODE/GND

8. LINE 1 OUT

STYLE 24:

PIN 1. BASE

2. EMITTER

3. COLLECTOR/ANODE

4. COLLECTOR/ANODE

5. CATHODE

6. CATHODE

7. COLLECTOR/ANODE

8. COLLECTOR/ANODE

STYLE 25:

PIN 1. VIN

2. N/C

3. REXT

4. GND

5. IOUT

6. IOUT

7. IOUT

8. IOUT

STYLE 26:

PIN 1. GND

2. dv/dt

3. ENABLE

4. ILIMIT

5. SOURCE

6. SOURCE

7. SOURCE

8. VCC

STYLE 27:

PIN 1. ILIMIT

2. OVLO

3. UVLO

4. INPUT+

5. SOURCE

6. SOURCE

7. SOURCE

8. DRAIN

STYLE 28:

PIN 1. SW_TO_GND

2. DASIC_OFF

3. DASIC_SW_DET

4. GND

5. V_MON

6. VBULK

7. VBULK

8. VIN

STYLE 29:

PIN 1. BASE, DIE #1

2. EMITTER, #1

3. BASE, #2

4. EMITTER, #2

5. COLLECTOR, #2

6. COLLECTOR, #2

7. COLLECTOR, #1

8. COLLECTOR, #1

STYLE 30:

PIN 1. DRAIN 1

2. DRAIN 1

3. GATE 2

4. SOURCE 2

5. SOURCE 1/DRAIN 2

6. SOURCE 1/DRAIN 2

7. SOURCE 1/DRAIN 2

8. GATE 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB42564B

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2

SOIC−8 NB

0N Semiwndudw" HH‘H-H-g an GAVE mas SHAL mum PER sun: 5 7’|:I o mMENsIaNeDoEsMa a t M FLASH OR mmusm anomusm SHALL N H H H H 7 PERsmE s vsmmnmuuagns A pm: /'° a O 6 A a F nsrsmcs arm :I s D‘MENSIDN AAND BA H mm mm: rwr DETAIL E 7* Hummus mm mm m A um 1m 5 um um ._ \ c m ‘ m / u nus n15 5mm 4.3 r non mu m": / a n ss‘asc n nzs‘ asc DETAIL E L ‘ 90 ESE II n ‘ \ s " \ ON Sanaanaua-m and are hademavks a! Semxcanduclur Campunenls lnduslnes. Lu: dha ON Semxcanduclar ar us suhsxdxanes n the mnuaa Slates andJm mhev cmm‘nes ON Semxcunduclar vesewes ma “gm to make changes wuhum mnna. mouse to any pruduns necem ON Semanduc‘m makes nu wanamy. represenlalmn m guarantee regardmg ma smaamw at W; manuals can any pamcu‘av purpase nnv dues ON Samanuuamy assume any Mammy ansmg mac xna appncauan m use M any pmduclnv mum and specmcsl‘y dwsc‘axms any and an Mammy mc‘udmg Wham hmma‘mn spema‘ cansequenha‘ m \nmdeula‘ damages ON Semxmnduclar dues nn| away any hcense under Ms yam nghls Ivar xna

CASE 948R−02

ISSUE A DATE 04/07/2000

TSSOP 8

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A2.90 3.10 0.114 0.122

B2.90 3.10 0.114 0.122

C0.80 1.10 0.031 0.043

D0.05 0.15 0.002 0.006

F0.40 0.70 0.016 0.028

G0.65 BSC 0.026 BSC

L4.90 BSC 0.193 BSC

M0 6 0 6

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

___ _

SEATING

PLANE

PIN 1

DETAIL E

2X L/2

−U−

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

8x REFK

SCALE 2:1

IDENT

K0.25 0.40 0.010 0.016

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98AON00236D

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

TSSOP 8

a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www menu cumrsuerguwaxem Mavkmg gm 9 www nnserm cum

www.onsemi.com

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

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designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

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