The D3 (hot) state occurs with the e300 core in a sleep mode where the PLL is not running but 1V VDD is still applied to the entire chip. A soft reset enables the return to D0 state from this state. Also, if PME is enabled, context must be maintained. Specific to the 8313 family, the D3 (warm) state runs with VDD removed from a portion of the die. The final state is the D3 (cold) state with full power down. When power is restored to the chip, it must go through the normal Power-On Reset (POR).