In summary, the P5 platform introduces 64-bit processing to the QorIQ family, while leveraging architectural features pioneered in the P4 platform, including the three-level cache hierarchy for low latencies, hardware hypervisor for robust virtualization support, data path acceleration architecture (DPAA) for offloading packet handling tasks from the core, Trust architecture for preventing unauthorized code from being run on a system, and the CoreNet switch fabric which eliminates internal bottlenecks. This enables architectural compatibility from the P5 platform to the P4 platform and also to the P3 platform, which uses the same architecture. As a highly integrated device with integrated memory controllers—SATA, XAUI, SGMII, PCI Express® and Serial RapidIO® interconnects— the P5 platform fills a need in the embedded market for single-chip solutions with high single-threaded performance that fit within a 30W power budget. In addition, the QorIQ P5 family provides an excellent ecosystem, internally developed software and hardware as well as support from a variety of third party partners to help speed a design to market.