The P5020 processor is based on dual 64-bit e5500 power architecture cores running at up to 2GHz. Each core includes a 512KB backside L2 cache for more efficient memory access. The processor can support up to 64Gb addressing and its memory controller block provides support for dual DDR3/DDR3L operating at up to 1.3GHz. DDR3 helps to reduce power and provides 30% better throughput than prior DDR memory configurations. DDR3L is the low power version of DDR3 allowing for up to 25% power savings. The processor is an integrated SOC and includes a wide variety of high speed I/O interfaces so the user can design for any application need. The P5020 processor is highly integrated with four PCI Express® controllers, two Serial RapidIO controllers, two SATA 2.0 controllers and two USB 2.0 with PHY. The processor is switch based and uses the CoreNet switch fabric first introduced in the P4 platform. This switch fabric connects to a dual 1 Mb shared CoreNet platform cache w/ECC. The SerDes lanes can be Muxed to support a mix of I/O and Ethernet peripherals. The platform supports up to five Gigabit Ethernet controllers with SGMII and one 10 Gigabit Ethernet controller. The data path acceleration architecture acts as an offload mechanism for the main CPU cores and includes a security engine, a pattern matching engine and a RAID5/6 engine.