Scheda tecnica NTMS10P02R2 di onsemi

Commenti/errori della scheda tecnica

MOSFET 0N Semiconductor®

June, 2019 − Rev. 3

1Publication Order Number:

NTMS10P02R2/D

NTMS10P02R2

MOSFET – Power, Single,

P-Channel, Enhancement

Mode, SOIC-8

-10 Amps, -20 Volts

Features

•Ultra Low RDS(on)

•Higher Efficiency Extending Battery Life

•Logic Level Gate Drive

•Miniature SOIC−8 Surface Mount Package

•Diode Exhibits High Speed, Soft Recovery

•Avalanche Energy Specified

•SOIC−8 Mounting Information Provided

•Pb−Free Package is Available

Applications

•Power Management in Portable and Battery−Powered Products,

i.e.: Cellular and Cordless Telephones and PCMCIA Cards

MAXIMUM RATINGS

Rating Symbol Value Unit

Drain−to−Source Voltage VDSS −20 Vdc

Gate−to−Source Voltage − Continuous VGS "12 Vdc

Thermal Resistance −

Junction−to−Ambient (Note 1)

Total Power Dissipation @ TA = 25°C

Continuous Drain Current @ 25°C

Continuous Drain Current @ 70°C

Maximum Operating Power Dissipation

Maximum Operating Drain Current

Pulsed Drain Current (Note 3)

RqJA

IDM

2.5

−10

−8.0

0.6

−5.5

−50

°C/W

Thermal Resistance −

Junction−to−Ambient (Note 2)

Total Power Dissipation @ TA = 25°C

Continuous Drain Current @ 25°C

Continuous Drain Current @ 70°C

Maximum Operating Power Dissipation

Maximum Operating Drain Current

Pulsed Drain Current (Note 3)

RqJA

IDM

1.6

−8.8

−6.4

0.4

−4.5

−44

°C/W

Operating and Storage Temperature Range TJ, Tstg −55 to

+150

°C

Single Pulse Drain−to−Source Avalanche En-

ergy − Starting TJ = 25°C

(VDD = −20 Vdc, VGS = −4.5 Vdc,

Peak IL = 5.0 Apk, L = 40 mH, RG = 25 W)

EAS 500 mJ

Maximum Lead Temperature for Soldering

Purposes, 1/8″ from case for 10 seconds

TL260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Mounted onto a 2″ square FR−4 Board

(1 in sq, Cu 0.06″ thick single sided), t = 10 seconds.

2. Mounted onto a 2″ square FR−4 Board

(1 in sq, Cu 0.06″ thick single sided), t = steady state.

Device Package Shipping†

ORDERING INFORMATION

NTMS10P02R2 SOIC−8

http://onsemi.com

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

SOIC−8

CASE 751

STYLE 12

MARKING DIAGRAM &

PIN ASSIGNMENT

E10P02 = Specific Device Code

A = Assembly Location

Y = Year

WW = Work Week

G= Pb−Free Package

E10P02

AYWW G

SS SG

DD DD

(Note: Microdot may be in either location)

NTMS10P02R2G SOIC−8

(Pb−Free)

2500/Tape & Reel

−10 AMPERES

−20 VOLTS

14 mW @ VGS = −4.5 V

P−Channel

NTMS10P02R2

http://onsemi.com

3. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2%.

NTMS10P02R2

http://onsemi.com

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) (Note 4)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

(VGS = 0 Vdc, ID = −250 mAdc)

Temperature Coefficient (Positive)

V(BR)DSS

−20

−

−12.1

−

Vdc

mV/°C

Zero Gate Voltage Drain Current

(VDS = −20 Vdc, VGS = 0 Vdc, TJ = 25°C)

(VDS = −20 Vdc, VGS = 0 Vdc, TJ = 70°C)

IDSS

−

−1.0

−5.0

mAdc

Gate−Body Leakage Current

(VGS = −12 Vdc, VDS = 0 Vdc)

IGSS

− − −100

nAdc

Gate−Body Leakage Current

(VGS = +12 Vdc, VDS = 0 Vdc)

IGSS

− − 100

nAdc

ON CHARACTERISTICS

Gate Threshold Voltage

(VDS = VGS, ID = −250 mAdc)

Temperature Coefficient (Negative)

VGS(th)

−0.6

−

−0.88

2.8

−1.20

−

Vdc

mV/°C

Static Drain−to−Source On−State Resistance

(VGS = −4.5 Vdc, ID = −10 Adc)

(VGS = −2.5 Vdc, ID = −8.8 Adc)

RDS(on)

−

0.012

0.017

0.014

0.020

Forward Transconductance (VDS = −10 Vdc, ID = −10 Adc) gFS −30 −Mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

(VDS = −16 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Ciss −3100 3640 pF

Output Capacitance Coss −1100 1670

Reverse Transfer Capacitance Crss −475 1010

SWITCHING CHARACTERISTICS (Notes 5 & 6)

Turn−On Delay Time

(VDD = −10 Vdc, ID = −1.0 Adc,

VGS = −4.5 Vdc,

RG = 6.0 W)

td(on) −25 35 ns

Rise Time tr−40 65

Turn−Off Delay Time td(off) −110 190

Fall Time tf−110 190

Turn−On Delay Time

(VDD = −10 Vdc, ID = −10 Adc,

VGS = −4.5 Vdc,

RG = 6.0 W)

td(on) −25 −ns

Rise Time tr−100 −

Turn−Off Delay Time td(off) −100 −

Fall Time tf−125 −

Total Gate Charge (VDS = −10 Vdc,

VGS = −4.5 Vdc,

ID = −10 Adc)

Qtot −48 70 nC

Gate−Source Charge Qgs −6.5 −

Gate−Drain Charge Qgd −17 −

BODY−DRAIN DIODE RATINGS (Note 5)

Diode Forward On−Voltage (IS = −2.1 Adc, VGS = 0 Vdc)

(IS = −2.1 Adc, VGS = 0 Vdc, TJ = 125°C)

VSD −

−

−0.72

−0.60

−1.2

−

Vdc

Diode Forward On−Voltage (IS = −10 Adc, VGS = 0 Vdc)

(IS = −10 Adc, VGS = 0 Vdc, TJ = 125°C)

VSD −

−

−0.90

−0.75

−

Vdc

Reverse Recovery Time

(IS = −2.1 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/ms)

trr −65 100 ns

ta−25 −

tb−40 −

Reverse Recovery Stored Charge QRR −0.075 −mC

4. Handling precautions to protect against electrostatic discharge is mandatory.

5. Indicates Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%.

6. Switching characteristics are independent of operating junction temperature.

0 0.25 050 0.75 100 1,25 1.50 175 2,0 0 0,5 10 15 20 2.5

NTMS10P02R2

http://onsemi.com

Figure 1. On−Region Characteristics

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

5.0

2.001.751.501.251.000.750.500.250

-ID, DRAIN CURRENT (AMPS)

Figure 2. Transfer Characteristics

−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

2.52.01.51.00.50

8.0

6.0

4.0

2.0

Figure 3. On−Resistance versus

Gate−To−Source Voltage

−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

0.100

0.075

0.050

0.025

108.06.04.02.00

RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 4. On-Resistance versus Drain Current

and Gate Voltage

−ID, DRAIN CURRENT (AMPS)

1814106.0

0.016

0.012

RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)

0.0080

0.020

Figure 5. On−Resistance Variation with

Temperature

TJ, JUNCTION TEMPERATURE (°C)

1.6

1.4

1.2

1.0

0.8

1501251007550250−25−50

Figure 6. Drain−To−Source Leakage Current

versus Voltage

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

1814106.02.0

1000

100

-IDSS, LEAKAGE (nA)

0.6

10,000

-ID, DRAIN CURRENT (AMPS)

VDS ≥ −10 V

TJ = −55°C

25°C

100°C

ID = −10 A

TJ = 25°C

TJ = 25°CVGS = −2.5 V

VGS = −4.5 V

RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

ID = −10 A

VGS = −4.5 V

TJ = 125°C

VGS = 0 V

TJ = 100°C

TJ = 25°C

VGS = −1.7 V

−1.9 V

−2.1 V−2.3 V

−3.1 V

−10 V

NTMS10P02R2

http://onsemi.com

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

2000

8000

Figure 7. Capacitance Variation

10 0 5.0 105.0

TJ = 25°C

Ciss

Coss

Crss

15 20

4000

6000

Ciss

Crss

VGS = 0 V VDS = 0 V

−VDS

−VGS

10,000

Figure 8. Gate−To−Source and Drain−To−Source

Voltage versus Total Charge

RG, GATE RESISTANCE (OHMS)

1.0 10 100

100

t, TIME (ns)

VDD = −10 V

ID = −1.0 A

VGS = −4.5 V

td(on)

Figure 9. Resistive Switching Time Variation

versus Gate Resistance

−V

GS, GATE−TO−SOURCE VOLTAGE (VOLTS)

2.0

1.0

Qg, TOTAL GATE CHARGE (nC)

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

5.0

10 20 40

ID = −10 A

TJ = 25°C

VDS

VGS

1000

3.0

2.0 4.0

6.0

4.0 8.0

td(off)

RG, GATE RESISTANCE (OHMS)

1.0 10 100

100

t, TIME (ns)

VDD = −10 V

ID = −10 A

VGS = −4.5 V tr

td(on)

Figure 10. Resistive Switching Time Variation

versus Gate Resistance

1000

td(off)

vGS : 2.5 v SINGLE PULSE : 25’5 — HD5IUI’II LIMIT THERMAL LIMIT —-— PACKAGE LIMIT Normalized Chm 001530 006529 019mm 054th as Innsmr IDIBSBF IossnF IlamF In 7 I OE—OS I 0E—04 1.0E—03 I,0E-02 I.0E-0I I 0E+00 I 0E+0I I.0E+ L TIME (s) RIma(IIEFFEC THERMAL 9 9 SINGLE PULSE 0.001 Figure 14. Thermal Response hllp://onsemi.com 6

NTMS10P02R2

http://onsemi.com

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

0.50 0.55 0.60 0.65

0.4

0.8

−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 11. Diode Forward Voltage versus Current

−IS, SOURCE CURRENT (AMPS)

2.0 VGS = 0 V

TJ = 25°C

1.2

0.70

1.6

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

0.1

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

0.1

1.0

−ID, DRAIN CURRENT (AMPS)

RDS(on) LIMIT

THERMAL LIMIT

PACKAGE LIMIT

VGS = 2.5 V

SINGLE PULSE

TC = 25°C

1.0

100

10 ms

1.0 ms

100 ms

Figure 13. Diode Reverse Recovery Waveform

di/dt

trr

0.25 IS

TIME

TYPICAL ELECTRICAL CHARACTERISTICS

Figure 14. Thermal Response

t, TIME (s)

Rthja(t), EFFECTIVE TRANSIENT

THERMAL RESISTANCE

1.0

0.1

0.01

D = 0.5

SINGLE PULSE

1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01

0.2

0.05

0.01

1.0E+02 1.0E+03

0.001

0.0163 W0.0652 W0.1988 W0.6411 W0.9502 W

72.416 F1.9437 F0.5541 F0.1668 F0.0307 F

Chip

Ambient

Normalized to qja at 10s.

0.1

0.02

0N Semiwndudw" m @ HHHH HHHH HHHH HERE 4 FUDGE] !HHH !HHH gHHH EHHH 1 1 } x ‘ 1 (...... a. ............. ... ......M .. SW. CW ........ .. ... 0. SW .. W- .. ...... ...... ...... ...... 0. SW ...... ... .... .. .... ...... ...... .. ... ...... ...... o. ......m... .. ...... .. ...... ...... ... 5...... .. .. ...... ... .. ...... a. s............ ...... ... ...... ...... ...... .....w... .. .. ... ...... ......w... ....-. ... ... ... ...... ...... ...... ...... ...5......... .. ...... ...... o. 5.--.-. .... ...... ... ...... ...... .... ..............

SOIC−8 NB

CASE 751−07

ISSUE AK

DATE 16 FEB 2011

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

SCALE 1:1

STYLES ON PAGE 2

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

XXXXX = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

GENERIC

MARKING DIAGRAM*

XXXXX

ALYWX

IC Discrete

XXXXXX

AYWW

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

Discrete

XXXXXX

AYWW

(Pb−Free)

XXXXX

ALYWX

(Pb−Free)

XXXXXX = Specific Device Code

A = Assembly Location

Y = Year

WW = Work Week

G= Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB42564B

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

SOIC−8 NB

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SOIC−8 NB

CASE 751−07

ISSUE AK

DATE 16 FEB 2011

STYLE 4:

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

8. COMMON CATHODE

STYLE 1:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

7. BASE

8. EMITTER

STYLE 2:

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

6. EMITTER, #2

7. BASE, #1

8. EMITTER, #1

STYLE 3:

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. GATE, #1

8. SOURCE, #1

STYLE 6:

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

STYLE 5:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

6. GATE

7. SOURCE

8. SOURCE

STYLE 7:

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

3. BASE, #2

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

STYLE 9:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 10:

PIN 1. GROUND

2. BIAS 1

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

STYLE 11:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 15:

PIN 1. ANODE 1

2. ANODE 1

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

5. RXE

6. VEE

7. GND

8. ACC

STYLE 18:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

STYLE 19:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. MIRROR 2

7. DRAIN 1

8. MIRROR 1

STYLE 20:

PIN 1. SOURCE (N)

2. GATE (N)

3. SOURCE (P)

4. GATE (P)

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 21:

PIN 1. CATHODE 1

2. CATHODE 2

3. CATHODE 3

4. CATHODE 4

5. CATHODE 5

6. COMMON ANODE

7. COMMON ANODE

8. CATHODE 6

STYLE 22:

PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC

3. COMMON CATHODE/VCC

4. I/O LINE 3

5. COMMON ANODE/GND

6. I/O LINE 4

7. I/O LINE 5

8. COMMON ANODE/GND

STYLE 23:

PIN 1. LINE 1 IN

2. COMMON ANODE/GND

3. COMMON ANODE/GND

4. LINE 2 IN

5. LINE 2 OUT

6. COMMON ANODE/GND

7. COMMON ANODE/GND

8. LINE 1 OUT

STYLE 24:

PIN 1. BASE

2. EMITTER

3. COLLECTOR/ANODE

4. COLLECTOR/ANODE

5. CATHODE

6. CATHODE

7. COLLECTOR/ANODE

8. COLLECTOR/ANODE

STYLE 25:

PIN 1. VIN

2. N/C

3. REXT

4. GND

5. IOUT

6. IOUT

7. IOUT

8. IOUT

STYLE 26:

PIN 1. GND

2. dv/dt

3. ENABLE

4. ILIMIT

5. SOURCE

6. SOURCE

7. SOURCE

8. VCC

STYLE 27:

PIN 1. ILIMIT

2. OVLO

3. UVLO

4. INPUT+

5. SOURCE

6. SOURCE

7. SOURCE

8. DRAIN

STYLE 28:

PIN 1. SW_TO_GND

2. DASIC_OFF

3. DASIC_SW_DET

4. GND

5. V_MON

6. VBULK

7. VBULK

8. VIN

STYLE 29:

PIN 1. BASE, DIE #1

2. EMITTER, #1

3. BASE, #2

4. EMITTER, #2

5. COLLECTOR, #2

6. COLLECTOR, #2

7. COLLECTOR, #1

8. COLLECTOR, #1

STYLE 30:

PIN 1. DRAIN 1

2. DRAIN 1

3. GATE 2

4. SOURCE 2

5. SOURCE 1/DRAIN 2

6. SOURCE 1/DRAIN 2

7. SOURCE 1/DRAIN 2

8. GATE 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB42564B

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2

SOIC−8 NB

a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www menu cumrsuerguwaxem Mavkmg gm 9 www nnserm cum

www.onsemi.com

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

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