Scheda tecnica TLC5973 di Texas Instruments

Commenti/errori della scheda tecnica

I TEXAS INSTRUMENTS L l i W" T T T m, 7 § 7 § H’VW # f +7 +7 4H7 +

GND

VCC

Controller

OUT0

SDO

SDI

VCC

GND

IREF

OUT1

OUT2

Device

OUT0

SDO

SDI

VCC

GND

IREF

OUT1

OUT2

Device

RIREF RIREF

Power

Supply

(5 V)

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLC5973

SBVS225B –MARCH 2013–REVISED MAY 2014

TLC5973 3-Channel, 12-Bit, PWM Constant-Current LED Driver

with Single-Wire Interface (EasySet™)

1 Features

1• Three Constant Sink Current Channels

• Current Capability:

– 2 mA to 35 mA per Channel (VCC ≤4.0 V)

– 2 mA to 50 mA per Channel (VCC > 4.0 V)

• Grayscale (GS) Control with PWM:

– 12-Bit (4096 Steps)

• Single-Wire Interface (EasySet)

• Power-Supply (VCC) Voltage Range:

– 3Vto6V

• OUT Pins Maximum Voltage: Up to 21 V

• Integrated Shunt Regulator

• Data Transfer Maximum Rate:

– Bits per Second (bps): 3 Mbps

• Internal GS Clock Oscillator: 12 MHz (typ)

• Display Repeat Rate: 2.9 kHz (typ)

• Output Delay Switching to Prevent Inrush Current

• Unlimited Device Cascading

• Operating Temperature: –40°C to 85°C

2 Applications

This device is targeted towards one application.

The primary application for this device is for RGB

LED cluster lamp displays.

3 Description

The TLC5973 is an easy-to-use, 3-channel, 50-mA

constant sink current LED driver. The single-wire,

3-Mbps serial interface (EasySet) provides a solution

for minimizing wiring cost. The LED driver provides

12-bit pulse width modulation (PWM) resolution. The

display repeat rate is achieved at 2.9 kHz (typ) with

an integrated 12-MHz grayscale (GS) clock oscillator.

The driver also provides unlimited cascading

capability.

All output sink constant currents can be set by an

external resistor. The TLC5973 has an internal shunt

regulator that can be used for higher VCC power-

supply voltage applications.

Device Information(1)

DEVICE NAME PACKAGE BODY SIZE

TLC5973 SOIC (8) 4.9 mm × 3.91 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

space

Typical Application Circuit Example

l TEXAS INSTRUMENTS

TLC5973

SBVS225B –MARCH 2013–REVISED MAY 2014

www.ti.com

Product Folder Links: TLC5973

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 3

6.1 Absolute Maximum Ratings ..................................... 3

6.2 Handling Ratings....................................................... 3

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Switching Characteristics.......................................... 6

6.7 Typical Characteristics.............................................. 6

7 Parameter Measurement Information .................. 7

7.1 Pin-Equivalent Input and Output Schematic

Diagrams.................................................................... 7

7.2 Test Circuits .............................................................. 7

7.3 Timing Diagrams....................................................... 8

8 Detailed Description............................................ 10

8.1 Overview ................................................................. 10

8.2 Functional Block Diagram....................................... 11

8.3 Feature Description................................................. 11

8.4 Device Functional Modes........................................ 13

8.5 Programming........................................................... 19

8.6 Register Maps......................................................... 21

9 Applications and Implementation ...................... 22

9.1 Application Information............................................ 22

9.2 Typical Applications ................................................ 22

10 Power Supply Recommendations ..................... 28

11 Layout................................................................... 28

11.1 Layout Guidelines ................................................. 28

11.2 Layout Example .................................................... 28

12 Device and Documentation Support ................. 29

12.1 Trademarks........................................................... 29

12.2 Electrostatic Discharge Caution............................ 29

12.3 Glossary................................................................ 29

13 Mechanical, Packaging, and Orderable

Information ........................................................... 29

4 Revision History

Changes from Revision A (May 2013) to Revision B Page

• Changed format to meet latest data sheet standards; added Applications and Implementation,Power Supply

Recommendations, and Layout sections, moved existing sections ....................................................................................... 1

• Changed 8-bit pulse width modulation to 12-bit pulse width modulation in Description section ........................................... 1

• Changed tH0 and tH1 parameter units from µs to ns in Recommended Operating Conditions table ..................................... 4

• Changed Figure 8: deleted top SDO, changed bottom SDO to OUTn................................................................................. 7

• Changed Figure 11: deleted extraneous breaks in traces, extraneous data call-outs, and tH1 on GSLAT trace,

changed data transfer trace note to Internal to 1st Device and 1st Data to 47th Data in 48-Bit Shift Register LSB trace.... 9

• Changed functional block diagram: changed Upper 8 Bits to Upper 12 Bits on 48-Bit Shift Register block ....................... 11

• Added Grayscale (GS) Control,EasySet and Shunt Regulator, and No Limit Cascading sections .................................... 11

• Changed Connector Design title .......................................................................................................................................... 13

• Changed Figure 13: changed OUTntraces GSDATA = 4093 and GSDATA = 4094 ......................................................... 15

• Changed description of the Data ‘0’ and Data ‘1’ Write Sequence (Data Write Sequence) section ................................... 16

• Changed title of Controlling Devices Connected in Series section ...................................................................................... 19

• Changed Data 101 to Data 1010 in Figure 18 .................................................................................................................... 19

• Changed eight MSBs to 12 MSBs in third sentence of the Register and Data Latch Configuration section....................... 21

• Changed Figure 21: corrected 3AAh bit set sequence ........................................................................................................ 21

• Changed Figure 26: changed number of LEDs in optional dashed box .............................................................................. 26

• Changed Table 7: changed all values in RVCC column and first and last values in Resistor Wattage column .................... 27

Changes from Original (March 2013) to Revision A Page

• Changed second paragraph of Grayscale (GS) Function (PWM Control) section............................................................... 13

• Changed tCYCLE setting range in Data Transfer Rate (tCYCLE) Measurement Sequence section .......................................... 16

• Updated Figure 18................................................................................................................................................................ 19

• Updated Figure 21 and Table 3............................................................................................................................................ 21

l TEXAS INSTRUMENTS 0 C C 0C E MUUU

VCC

IREF

SDI

SDO

OUT0

OUT1

OUT2

GND

TLC5973

www.ti.com

SBVS225B –MARCH 2013–REVISED MAY 2014

Product Folder Links: TLC5973

5 Pin Configuration and Functions

D Package

SO-8

(Top View)

Pin Functions

I/O DESCRIPTIONNAME NO.

OUT0 1 O Constant sink current driver outputs.

Multiple outputs can be configured in parallel to increase the sink drive current capability.

Different voltages can be applied to each output.

OUT1 2 O

OUT2 3 O

GND 4 — Power ground

SDO 5 O Serial data output

SDI 6 I Serial data input. This pin is internally pulled down to GND with a 1-MΩ(typ) resistor.

IREF 7 I/O Output current programming pin. A resistor connected between IREF and GND sets the current for

each constant-current output. Place the external resistor close to the device.

VCC 8 — Power-supply voltage

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

(2) All voltages are with respect to network ground pin.

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Voltage(2)

Supply, VCC VCC –0.3 7.0 V

Input range, VIN SDI –0.3 VCC + 1.2 V

Output range, VOUT OUT0 to OUT2 –0.3 21 V

SDO –0.3 7.0 V

Current Output (dc), IOUT OUT0 to OUT2 0 60 mA

Operating junction temperature, TJ–40 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 Handling Ratings

MIN MAX UNIT

Tstg Storage temperature range –55 150 °C

V(ESD) Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins(1) –8000 8000

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins(2) –2000 2000

l TEXAS INSTRUMENTS

TLC5973

SBVS225B –MARCH 2013–REVISED MAY 2014

www.ti.com

Product Folder Links: TLC5973

6.3 Recommended Operating Conditions

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

DC CHARACTERISTICS

VCC Supply voltage No internal shunt regulator mode 3.0 5.0 5.5 V

Internal shunt regulator mode 6.0 V

VOVoltage applied to output OUT0 to OUT2 21 V

VIH High-level input voltage SDI 0.7 × VCC VCC V

VIL Low-level input voltage SDI GND 0.3 × VCC V

VIHYST Input voltage hysteresis SDI 0.2 × VCC V

IOH High-level output current SDO –2 mA

IOL Low-level output current

SDO 2 mA

OUT0 to OUT2 (VCC ≤4.0 V) 2 35 mA

OUT0 to OUT2 (VCC > 4.0 V) 2 50 mA

IREG Shunt regulator sink current VCC 20 mA

TAOperating free-air temperature range –40 85 °C

TJOperating junction temperature range –40 125 °C

AC CHARACTERISTICS

fCLK (SDI) Data transfer rate SDI 100 3000 kHz

tSDI SDI input pulse duration SDI 60 0.5 / fCLK ns

tWH Pulse duration, high SDI 14 ns

tWL Pulse duration, low SDI 14 ns

tH0 Hold time: end of sequence (EOS) SDI↑to SDI↑3.5 / fCLK 5.5 / fCLK ns

tH1 Hold time: data latch (GSLAT) SDI↑to SDI↑8 / fCLK ns

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.4 Thermal Information

THERMAL METRIC(1)

TLC5973

UNITD (SO)

8 PINS

RθJA Junction-to-ambient thermal resistance 134.6

°C/W

RθJC(top) Junction-to-case (top) thermal resistance 88.6

RθJB Junction-to-board thermal resistance 75.3

ψJT Junction-to-top characterization parameter 37.7

ψJB Junction-to-board characterization parameter 74.8

RθJC(bot) Junction-to-case (bottom) thermal resistance N/A

I at V = 1.0 V

O OUTn nUT

(I at V = 3.0 V) (I at V = 1.0 V)

OUT OUTn-

n n nO OUTUT

D(%/V) = ´

3.0 V 1.0 V-

100

I at V = 3.0 V

OUT CCn

(I at V = 5.5 V) (I at V = 3.0 V)

OUT OUT CCn n

CC -

D(%/V) = ´

5.5 V 3.0 V-

100

I (mA) = 43.4

OUT (IDEAL)n´1.20

RIREF ( )W

D(%) =

Ideal Output Current

-Ideal Output Current

I + I + I

OUT0 O 1 O 2UT UT

3´100

D(%) =

-1

IOUTn

I + I + I

O 0 O 1 O 2UT UT UT

´100

TLC5973

www.ti.com

SBVS225B –MARCH 2013–REVISED MAY 2014

Product Folder Links: TLC5973

(1) The deviation of each output (OUT0 to OUT2) from the constant-current average. Deviation is calculated by the formula:

, where n = 0 to 2.

(2) Deviation of the constant-current average in each color group from the ideal constant-current value. Deviation is calculated by the

formula:

Ideal current is calculated by the formula:

, where n = 0 to 2.

(3) Line regulation is calculated by the formula:

, where n = 0 to 2.

(4) Load regulation is calculated by the equation:

, where n = 0 to 2.

6.5 Electrical Characteristics

At TA= –40°C to 85°C, VCC = 3 V to 6.0 V, and CVCC = 0.1 µF. Typical values at TA= 25°C and VCC = 5.0 V, unless otherwise

noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOH High-level output voltage (SDO) IOH = –2 mA VCC – 0.4 VCC V

VOL Low-level output voltage (SDO) IOL = 2 mA 0 0.4 V

VIREF Reference voltage output RIREF = 1.5 kΩ1.18 1.20 1.23 V

VRShunt regulator output voltage (VCC) ICC = 1 mA, SDI = low 5.9 V

ICC0

Supply current (VCC)

VCC = 3.0 V to 5.5 V , SDI = low, all grayscale (GSn) =

FFFh, VOUTn = 1 V, SDO = 15 pF, RIREF = 27 kΩ

(IOUTn = 2-mA target) 3 6 mA

ICC1

VCC = 3.0 V to 5.5 V, SDI = low, all grayscale (GSn) = FFFh,

VOUTn = 1 V, SDO = 15 pF, RIREF = 3 kΩ

(IOUTn = 17-mA target) 4 7 mA

ICC2

VCC = 3.0 V to 5.5 V, SDI = 5 MHz, all grayscale (GSn) =

FFFh, VOUTn = 1 V, SDO = 15 pF,

RIREF = 3 kΩ(IOUTn = 17-mA target) 5 8 mA

ICC3

VCC = 3.0 V to 5.5 V, SDI = 5 MHz, all grayscale (GSn) =

FFFh, VOUTn = 1 V, SDO = 15 pF,

RIREF = 1.5 kΩ(IOUTn = 34-mA target) 5.5 10 mA

IOLC Constant output current

(OUT0 to OUT2) All OUTn= on, VOUTn = 1 V, VOUTfix = 1 V,

RIREF = 1.5 kΩ31 34 37 mA

IOLKG Output leakage current

(OUT0 to OUT2) GSn= 000h, VOUTn = 21 V TJ= –40°C to 85°C 0.1 μA

TJ= 85°C to 125°C 0.2 μA

ΔIOLC0 Constant-current error

(channel-to-channel)(1) All OUTn= on, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ±0.5% ±3%

ΔIOLC1 Constant-current error

(device-to-device)(2) All OUTn= on, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ±0.5% ±6%

ΔIOLC2 Line regulation of constant-current

output(3) All OUTn= on, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ±0.5 ±1 %/V

ΔIOLC3 Load regulation of constant-current

output(4) All OUTn= on, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ±0.5 ±1 %/V

RPD Internal pull-down resistance (SDI) At SDI 1 MΩ

l TEXAS INSTRUMENTS lac

1.04

1.16

1.30

1.49

1.74

2.08

2.60

3.47

5.21

10.4

26.0

100

0 10 20 30 40 50

IREF, Reference Resistance (k)

IOLC, Output Current (mA)

C001

0 0.5 1 1.5 2 2.5 3

Output Current (mA)

Output Voltage (V)

C002

RIREF = 1.1 k

RIREF = 1.5 k

RIREF = 2.7 k

RIREF = 1.8 k

RIREF = 5.1 k

RIREF = 10 k

RIREF = 27 k

TLC5973

SBVS225B –MARCH 2013–REVISED MAY 2014

www.ti.com

Product Folder Links: TLC5973

6.6 Switching Characteristics

At TA= –40°C to 85°C, VCC = 3.0 V to 5.5 V, CL= 15 pF, RL= 110 Ω, and VLED = 5.0 V, unless otherwise noted.

Typical values are at TA= 25°C and VCC = 5.0 V.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tR0 Rise time SDO 2 6 12 ns

tR1 OUTn(on →off) 200 400 ns

tF0 Fall time SDO 2 6 12 ns

tF1 OUTn(off →on) 200 400 ns

tD0 Propagation delay

SDI↑to SDO↑30 50 ns

tD1 OUT0↓to OUT1↓, OUT1↓to OUT2↓,

OUT0↑to OUT1↑, OUT1↑to OUT2↑25 ns

tWO Shift data output one pulse duration SDO↑to SDO↓15 25 45 ns

fOSC Internal GS oscillator frequency 8 12 16 MHz

6.7 Typical Characteristics

At TA= 25°C and VCC = 12 V, unless otherwise noted.

Figure 1. Reference Resistance vs Output Current (OUTn)

VCC = 5 V

Figure 2. Output Current vs Output Voltage (OUTn)

l TEXAS INSTRUMENTS vcc 7 ﬂ vcc ",4 <7 %="">

VCC

RIREF

VOUTfix

VOUTn

VCC

OUTn(1)

OUTnGND

IREF

VCC

GND

SDO

(1)

IREF

RIREF

VCC

GND

IREF OUTn(1)

RIREF

(2) VLED

OUTn(1)

GND

VCC

SDO

GND

VCC

SDI

GND

TLC5973

www.ti.com

SBVS225B –MARCH 2013–REVISED MAY 2014

Product Folder Links: TLC5973

7 Parameter Measurement Information

7.1 Pin-Equivalent Input and Output Schematic Diagrams

Figure 3. SDI Figure 4. SDO

(1) n = 0 to 2.

Figure 5. OUT0 Through OUT2

7.2 Test Circuits

(1) n = 0 to 2.

(2) CLincludes measurement probe and jig capacitance.

Figure 6. Rise and Fall Time Test Circuit for

OUTn

(1) CLincludes measurement probe and jig capacitance.

Figure 7. Rise and Fall Time Test Circuit for SDO

(1) n = 0 to 2.

Figure 8. Constant-Current Test Circuit for OUTn

l TEXAS INSTRUMENTS ‘DE 1

90%

10%

VOUTnH

VOUTnL

VOUTnH

VOUTnL

50%

tD1

t , t ,

R1 F1 D1

OUTn

OUTn+ 1

tD1

tF1 tR1

90%

10%

tR0

VOH

VOL

VCC

GND

50%

tD0

t , t ,

R0 F0 D0 W 0

t , t

SDI(1)

SDO

tF0

tW0

tH0 H1

, t

50%

tWH tWL

VCC

GND

tWH WL

, t

SDI(1)

t , t

H0 H1

50%

48th Data

1st Data of Next Device (t case) or

1st Data of Next Sequence (t case).

H1 VCC

GND

TLC5973

SBVS225B –MARCH 2013–REVISED MAY 2014

www.ti.com

Product Folder Links: TLC5973

7.3 Timing Diagrams

(1) Input pulse rise and fall time is 1 ns to 3 ns.

Figure 9. Input Timing

(1) Input pulse rise and fall time is 1 ns to 3 ns.

Figure 10. Output Timing

! TEXAS INSTRUMENTS ﬂ WMJLW;‘I_H_ \ HJL\ x \\ \\ A x x x 5;“ x. \\ x H H H H IL H H x x x X A x‘ W x x m x \\ x x—‘—&\—x— —K# 1— H , K— HM H H HK—x— H x—

tR1

tF0

fCLK(SDI)

SDI

SDO

tD0

tD1

OUT0 ON

OFF

tF1

(V )

OUTnH

(V )

OUTnL

OUT1

OUT2

VCC

Data Transfer

Period Memory

(Internal in 1st Device)

1st Device

1st Data (0)

fCLK(SDI)

Data transfer period (tCYCLE) is stored.

tSDI

tWO

tWL

tWH

OUTEN Signal

(Internal) Low = SDI data are not output from SDO.

SCLK Signal

(Internal in 1st Device)

48-Bit Shift Register MSB

(Internal in 1st Device)

48-Bit Shift Register MSB-1

(Internal in 1st Device)

48-Bit Shift Register LSB+1

(Internal in 1st Device)

Recognized Data,

SIN Signal

(Internal in 1st Device)

48-Bit Shift Register LSB

(Internal in 1st Device)

GSLAT Signal

(Internal in 1st Device)

New GS Data

tR0

(All GS data are ‘0’ when VCC powers up.)

Data transfer period (tCYCLE) is stored.

2nd

Data (0)

3rd

Data (1)

4th

Data (1)

5th

Data (1)

48th

Data (0)

2nd Device

1st Data (0)

2nd

Data (0)

48th

Data (0)

1st Device

1st Data (0)

1st Data (0) 47th

Data 48th Data (0)

4th Data (1)3rd Data (1)2nd Data (0)

5th Data (1)

1st Data (0) 4th Data (1)3rd Data (1)2nd Data (0)

5th Data (1)

4th Data (1)

1st Data (0) 3rd Data (1)2nd Data (0)

1st Data (0)

48th Data (0)

3rd Data (0)

2nd Data (0)

(1)

SCLK Signal

(Internal in 2nd Device)

48th Data (0)

47th

Data

47th Data

2nd Data (0)

1st Data (0)

46th

Data

High = SDI data are output from SDO.

1st Data (0)

(All GS data are ‘0’ when VCC powers up.)

47th Data (0) 48th Data (0)

New GS Data

36-Bit GS Data Latch

(Internal in 1st Device)

GS Data Latch

(Internal in 2nd Device)

GSLAT Signal

(Internal in 2nd Device)

48-Bit Shift Register LSB

(Internal in 2nd Device)

t (for EOS)

H0 t (for GSLAT)

48th Data (0)

TLC5973

www.ti.com

SBVS225B –MARCH 2013–REVISED MAY 2014

Product Folder Links: TLC5973

Timing Diagrams (continued)

(1) OUTnon-time changes, depending on the data in the 36-bit GS data latch.

Figure 11. Data Write and OUTnSwitching Timing

l TEXAS INSTRUMENTS

TLC5973

SBVS225B –MARCH 2013–REVISED MAY 2014

www.ti.com

Product Folder Links: TLC5973

8 Detailed Description

8.1 Overview

The TLC5973 is 3-channel, 50-mA, constant-current LED driver that can control LED on-time with pulse width

modulation (PWM) in 4096 steps for grayscale (GS) control. A maximum of 68 billion colors can be generated

with red, green, and blue LEDs connected to each constant-current output. Furthermore, a reference clock

generator is implemented in the device, which means that the reference clock for PWM timing control is not

required to be supplied from an external clock generator or controller.

The device adopts a single-wire input or output system. Therefore, communication wire cost and communication

wire failure are reduced. Further wire cost reduction can be attained when supplying power to the device. One

wire can be eliminated because the device power can be generated from the LED power line with the internal

shunt regulator.

The device can reduce the amount of incorrect data writes because the one-write command is required to write

GS data to the device. The maximum data transfer rate for the device is 3 Mbps. Therefore, GS data can be

updated with a high refresh rate even if many devices are connected in series. The number of TLC5973 devices

connected in series is not limited because the TLC5973 has an internal buffer that drives the output signal.

l TEXAS INSTRUMENTS cum ouﬂ ouTz

Command

Decoder (3AAh)

Interface

Control

Upper 12 Bits

SDO

GND

48-Bit Shift Register

36-Bit GS Data Latch

GS Clock

Counter

3-Channel Constant Sink Current Driver

Switching Delay

LSB MSB

0 47

LSB MSB

0 35

VCC

SDI

OUT2

UVLO

Shunt

Regulator reset

Internal

Oscillator

12-Bit PWM Timing Control

OUT0 OUT1

VCC

sin

sclk

12 MHz

Lower 36 Bits

IREF

reset

Pulse

Generator

reset

gslat

outen

TLC5973

www.ti.com

SBVS225B –MARCH 2013–REVISED MAY 2014

Product Folder Links: TLC5973

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Grayscale (GS) Control

This control feature is a 12-bit (4096-step) grayscale (GS) control that provides a wide range of color generation.

68 billion colors can be generated with the red, green, and blue LEDs. Connect the LEDs to the device OUTn

pins, as described in the Applications and Implementation section.

8.3.2 EasySet and Shunt Regulator

This device includes a single-wire serial interface (EasySet) and a shunt regulator. The total number of wires for

power supply and data write operations can be reduced with the EasySet and shunt regulator included in the

design.

l TEXAS INSTRUMENTS ‘DLC

R (k ) =

IREF W

IOLC (mA)

VIREF (V)

´43.4

TLC5973

SBVS225B –MARCH 2013–REVISED MAY 2014

www.ti.com

Product Folder Links: TLC5973

Feature Description (continued)

8.3.3 No Limit Cascading

This feature results in no limitation on the number of total cascaded devices used in series in an application. This

advantage is attained because a timing-adjusted pulse generator is implemented in the device.

8.3.4 Constant Sink Current Value

The output current value of each channel (IOLC) is programmed by a single resistor (RIREF) that is placed between

the IREF and GND pins. The current value can be calculated by Equation 1:

where:

• VIREF = the internal reference voltage on IREF (typically 1.20 V), and

• IOLC = 2 mA to 50 mA (1)

IOLC is the current for each output. Each output sinks IOLC current when it is turned on. RIREF must be between

1 kΩand 27 kΩin order to hold IOLC between 50 mA (typ) and 1.93 mA (typ). Otherwise, the output may be

unstable. Refer to Figure 1 and Table 1 for the constant-current sink values for specific external resistor values.

Table 1. Constant-Current Output versus

External Resistor Value

IOLC (mA) RIREF (kΩ, typ)

50 1.04

45 1.16

40 1.30

35 1.49

30 1.74

25 2.08

20 2.60

15 3.47

10 5.21

5 10.4

2 26.0

l TEXAS INSTRUMENTS 5m * Connector (Ma‘e)

VCC (V )

LED

GND

SDI Connector (Male)

N+2nd

Device

PCB

To N-1st

Device

PCB or

Controller

and Power

Supply

N+1st Device PCB

Nth Device PCB

TLC5973

www.ti.com

SBVS225B –MARCH 2013–REVISED MAY 2014

Product Folder Links: TLC5973

8.3.5 Connector Design

When the connector pin of the device application printed circuit board (PCB) is connected or disconnected to

other PCBs, the power must be turned off to avoid device malfunction or failure. Furthermore, designing the

connector GND pin to be longer than other pins (as shown in Figure 12) is preferable. This arrangement allows

the GND line to either be connected first or disconnected last, which is imperative for proper device function.

Figure 12. Connector Pin Design Application

8.4 Device Functional Modes

8.4.1 Grayscale (GS) Function (PWM Control)

The TLC5973 can adjust the brightness of each output channel using a pulse width modulation (PWM) control

scheme. The PWM data bit length for each output is 12 bits. The architecture of 12 bits per channel results in

4096 brightness steps, from 0% to 99.98% on-time duty cycle.

The PWM operation for OUTnis controlled by an 12-bit grayscale (GS) counter. The GS counter increments on

each internal GS clock (GSCLK) rising edge. All OUTnare turned on when the GS counter is ‘1’, except when

OUTnare programed to GS data '0' in the 36-bit GS data latch. After turning on, each output is turns off when

the GS counter value exceeds the programmed GS data for the output. The GS counter resets to 000h and all

outputs are forced off when the GS data are written to the 36-bit GS data latch. Afterwards, the GS counter

begins incrementing and PWM control is started from the next internal GS clock.

l TEXAS INSTRUMENTS

TLC5973

SBVS225B –MARCH 2013–REVISED MAY 2014

www.ti.com

Product Folder Links: TLC5973

Device Functional Modes (continued)

Table 2 summarizes the GS data values versus the output ideal on-time duty cycle. Furthermore, actual on-time

differs from the ideal on-time because the output drivers and control circuit have some timing delay. When the

device is powered on, all outputs are forced off and remain off until the non-zero GS data are written to the 36-bit

GS data latch.

Table 2. Output Duty Cycle and Total On-Time versus GS Data

GS DATA NO. OF GSCLKs

OUTnTURNS ON NO. OF GSCLKs

OUTnTURNS OFF TOTAL IDEAL TIME

(µs) ON-TIME DUTY (%)DECIMAL HEX

0 0 Off Off 0 0

1 1 1 2 0.08 0.02

2 2 1 3 0.17 0.05

——————

255 0FE 1 256 21.25 6.23

256 0FF 1 257 21.33 6.25

257 100 1 258 21.42 6.27

——————

511 1FF 1 512 42.58 12.48

512 200 1 513 42.67 12.50

513 201 1 514 42.75 12.52

——————

1023 3FF 1 1024 85.25 24.98

1024 400 1 1025 85.33 25.00

1025 401 1 1026 85.42 25.00

——————

2047 7FF 1 2048 170.6 49.98

2048 800 1 2049 170.7 50.00

2049 801 1 2050 170.8 50.02

——————

4093 FFD 1 4094 341.1 99.93

4094 FFE 1 4095 341.2 99.95

4095 FFF 1 4096 341.3 99.98

l TEXAS INSTRUMENTS

t = GSCLK 2048x

t = GSCLK 2047x

t = GSCLK 2046x

t = GSCLK x 1

t = GSCLK 3x

t = GSCLK 2x

1 2 3 4

No driver turns on.

OFF

t = GSCLK 4095x

OFF

t = GSCLK 4093x

(V )

OUTnH

t = GSCLK 4094x

OFF

t = GSCLK 1x

OFF

2047

2048

2049

4094 1

4095

4096

Grayscale

Reference Clock, GSCLK

(Internal)

OUT

(GSDATA = 0)

(V )

OUTnL

OUT

(GSDATA = 1)

OUT

(GSDATA = 2)

OUT

(GSDATA = 3)

OUT

(GSDATA = 2046)

OUT

(GSDATA = 2047)

OUT

(GSDATA = 2048)

OUT

(GSDATA = 4093)

OUT

(GSDATA = 4094)

OUT

(GSDATA = 4095)

TLC5973

www.ti.com

SBVS225B –MARCH 2013–REVISED MAY 2014

Product Folder Links: TLC5973

8.4.1.1 PWM Control

The GS counter keeps track of the number of grayscale reference clocks (GSCLKs) from the internal oscillator.

Each output stays on while the counter is less than or equal to the programmed GS value. Each output turns off

when the GS counter is greater than the GS value in the 36-bit GS data latch. Figure 13 illustrates the PWM

operation timing.

(1) Actual on-time differs from the ideal on-time.

Figure 13. PWM Operation

l TEXAS INSTRUMENTS m sm 2nd SDI 5 MH— H 777777777777777777777 +1 Data u Wmmg Da|a 1 Wrmng

SDI

When the second SDI

rising edge is not input, it

is recognized as ‘0’.

t = 0.9 x t

SDI CYCLE

This time must be between t x 0.9 and t x 2.0

CYCLE CYCLE

t = 0.5 x t

SDI CYCLE

When the second SDI

rising edge is input by

0.5 x t it

is recognized as ‘1’.

CYCLE,

Dotted line waveform

is accepted.

Data 0 Writing

First SDI

Rising Edge

Data 1 Writing

First SDI

Rising Edge

Second SDI

Rising Edge

SDI

tCYCLE

2nd SDI

Rising Edge

1st SDI

Rising Edge

TLC5973

SBVS225B –MARCH 2013–REVISED MAY 2014

www.ti.com

Product Folder Links: TLC5973

8.4.2 One-Wire Interface (EasySet) Data Writing Method

There are four sequences to write GS data into the TLC5973 via a single-wire interface. This section discusses

each sequence in detail.

8.4.2.1 Data Transfer Rate (tCYCLE) Measurement Sequence

The TLC5973 measures the time between the first and second SDI rising edges either after the device is

powered up or when the GS data latch sequence is executed (as described in the GS Data Latch Sequence

(GSLAT) section) and the time is internally stored as tCYCLE. tCYCLE serves as a base time used to recognize one

complete data write operation, a 48-bit data write operation, and a GS data write operation to the GS data latch.

tCYCLE can be set between 0.33 µs and 10 µs (fCLK(SDI) = 100 kHz to 3000 kHz). In this sequence, two instances

of data ‘0’ are written to the LSB side of the 48-bit shift register. Figure 14 shows the tCYCLE measurement timing.

Figure 14. Data Transfer Rate (tCYCLE) Measurement

8.4.2.2 Data ‘0’ and Data ‘1’ Write Sequence (Data Write Sequence)

When the second SDI rising edge is not input before 0.9 × tCYCLE elapses from the first SDI rising edge input, the

data are recognized as '0'. When the second SDI rising edge is input before 50% of tCYCLE elapses from the first

SDI rising edge input, the data are recognized as '1'. This write sequence must be repeated 46 times after the

tCYCLE measurement sequence in order to send the write command to the higher 10-bit (3AAh) and 36-bit GS

data. Figure 15 shows the data ‘0’ and ‘1’ write timing.

Figure 15. Data ‘0’ and ‘1’ Write Operation

l TEXAS INSTRUMENTS , The my SD‘ nsmg edge a! me \as| mum da|a A, . ’ / z I v ’ / O

SDO

SDI

The first SDI rising edge of the last input data.

GS data are not changed.

GS data latch signal is not generated.

Shift register data are locked.

High = pulse signal output from SDO.

Low = pulse signal not

output from SDO.

3.5 x t (min) to 5.5 x t (max)

CYCLE CYCLE

48-Bit Shift

(Internal)

GSLATignal

(Internal)

36-Bit GS

Data Latch

(Internal)

OUTEN Signal

(Internal)

TLC5973

www.ti.com

SBVS225B –MARCH 2013–REVISED MAY 2014

Product Folder Links: TLC5973

8.4.2.3 One Communication Cycle End of Sequence (EOS)

One communication cycle end of sequence (EOS) must be input after the 48-bit data are written because the

TLC5973 does not count the number of input data. When SDI is held low for the EOS hold time (tH0), the 48-bit

shift register values are locked and a buffered SDI signal is output from SDO to transfer GS data to the next

device. Figure 16 shows the EOS timing.

Figure 16. End of Sequence (EOS)

l TEXAS INSTRUMENTS

SDO

The first SDI rising edge of the last input data.

SDI

New GS Data

High = pulse signal output from SDO.

48-Bit Shift

(Internal)

GSLAT Signal

(Internal)

GS Data in

36-Bit

Data Latch

(Internal)

OUTEN Signal

(Internal) Low = pulse signal not output from SDO.

Shift register data are

written after GSLAT is input.

8 x t (min)

CYCLE

TLC5973

SBVS225B –MARCH 2013–REVISED MAY 2014

www.ti.com

Product Folder Links: TLC5973

8.4.2.4 GS Data Latch (GSLAT) Sequence

A GS data latch (GSLAT) sequence must be input after the 48-bit data for all cascaded devices are written.

When SDI is held low for the data latch hold time (tH1), the 48-bit shift register data in all devices are copied to

the GS data latch in each device. Furthermore, PWM control starts with the new GS data at the same time.

Figure 17 shows the GSLAT timing.

Figure 17. GS Data Latch Sequence (GSLAT)

GND

5.0 V

VLED

GND

CLK

Controller

GND

VCC

GND

Nth Device

VCC

GND

VCC

GND

VCC

GND

VCC

RVCC

SDI SDI SDI SDI

SDO SDO SDO SDO

0.1 F

VCC

N-1st Device2nd Device1st Device

RVCC RVCC RVCC

IREF IREF IREF IREF

MSB LSB

Data 0

for tCYCLE

Data 0

for tCYCLE

Data

0 or 1

Data

0 or 1

Data

0 or 1

Data

0 or 1

Data

0 or 1

Data

0 or 1

Bit 0Bit 11Bit 0Bit 11Bit 0Bit 11

Write Command Data, 12 Bits

(3AAh = 001110101010b) OUT0

GS Data, 12 Bits

OUT1

GS Data, 12 Bits

OUT2

GS Data, 12 Bits

Bit 0Bit 11

Data

1010

TLC5973

www.ti.com

SBVS225B –MARCH 2013–REVISED MAY 2014

Product Folder Links: TLC5973

8.5 Programming

8.5.1 Controlling Devices Connected in Series

The 12-bit write command and 36-bit grayscale (GS) data for OUT0 to OUT2 (for a total of 48 bits of data) must

be written to the device. Figure 18 shows the 48-bit data packet configuration. When multiple devices are

cascaded (as shown in Figure 19), Ntimes the packet must be written into each TLC5973 in order to control all

devices. There is no limit on how many devices can be cascaded, as long as proper VCC voltage is supplied.

The packet for all devices must be written again whenever any GS data changes.

Figure 18. 48-Bit Data Packet Configuration for One TLC5973

Figure 19. Cascade Connection of NTLC5973 Units (Internal Shunt Regulator Mode)

l TEXAS INSTRUMENTS

MSB LSB MSB LSB MSB LSB

EOS

EOS EOS

EOS

MSB LSB

GSLAT

MSB LSB

48-Bit Data Packet

for 1st Device

48-Bit Data Packet

for 2nd Device

48-Bit Data Packet

for Nth Device

Next Data Packet

for 1st Device

48-Bit Data Packet

for 2nd Device

48-Bit Data Packet

for Nth Device

48-Bit Data Packet

for Nth Device

48-Bit Data Packet

for Nth Device

PWM Control Starts

with new GS Data

V Power

LED

1st SDIDevice

1st SDODevice

N-2nd SDODevice

N-1st SDODevice

OUTn

For 3rd

Device

For 3rd

Device

For 3rd

Device

For

N-1th

For

N-1th

For

N-1st

TLC5973

SBVS225B –MARCH 2013–REVISED MAY 2014

www.ti.com

Product Folder Links: TLC5973

Programming (continued)

The function setting write procedure and display control is:

1. Power-up VCC (VLED); all OUTnare off because GS data are not written yet.

2. Write the 48-bit data packet (MSB-first) for the first device using tCYCLE and the data write sequences

illustrated in Figure 14 and Figure 15. The first 12 bits of the 48-bit data packet are used as the write

command. The write command must be 3AAh (001110101010b); otherwise, the 36-bit GS data in the 48-bit

shift register are not copied to the 36-bit GS data latch.

3. Execute one communication cycle EOS (refer to Figure 16) for the first device.

4. Write the 48-bit data packet for the second TLC5973 as described step 2. However, tCYCLE should be set to

the same timing as the first device.

5. Execute one communication cycle EOS for the second device.

6. Repeat steps 4 and 5 until all devices have GS data.

7. The number of total bits is 48 × N. After all data are written, execute a GSLAT sequence as described in

Figure 17 in order to copy the 36-bit LSBs in the 48-bit shift resister to the 36-bit GS data latch in each

device; PWM control starts with the written GS data at the same time.

Figure 20. Data Packet Input Order for NTLC5973 Units

‘5‘ TEXAS INSTRUMENTS 0mm 0mm

12-Bit Write

Command

Decoder

MSB

Write

Command

Bit 11

36 Bits

36---

LSB

---11

36 Bits

12 Bits

Write Command = 3AAh (001110101010b)

GS Data

Latch Pulse

(Internal)

Write

Command

Bit 0

--- 23

LSB

OUT0

GS Data

Bit 11

0---1112

24---35 ---

OUT0

GS Data

Bit 0

OUT1

GS Data

Bit 11

OUT1

GS Data

Bit 0

OUT2

GS Data

Bit 11

OUT2

GS Data

Bit 0

---

OUT0

GS Data

Bit 11

OUT0

GS Data

Bit 0

OUT1

GS Data

Bit 11

OUT1

GS Data

Bit 0

OUT2

GS Data

Bit 11

OUT2

GS Data

Bit 0

MSB

The internal latch pulse is generated after 8 t without SDI clocking.

CYCLES

Shift Data (Internal)

Shift Clock (Internal)

48-Bit Shift Register

36-Bit GS Data Latch

To Grayscale Timing

Control Circuit

TLC5973

www.ti.com

SBVS225B –MARCH 2013–REVISED MAY 2014

Product Folder Links: TLC5973

8.6 Register Maps

8.6.1 Register and Data Latch Configuration

The TLC5973 has a 48-bit shift register and a 36-bit data latch that stores GS data. When the internal GS data

latch pulse is generated and the data of the 12 MSBs in the shift register are 3AAh, the lower 36-bit data in the

48-bit shift register are copied into the 36-bit GS data latch. If the data of the 12 MSBs is not 3AAh, the 36-bit

data are not copied into the 36-bit GS data latch. Figure 21 shows the shift register and GS data latch

configurations. Table 3 shows the 48-bit shift register bit assignment.

Figure 21. Common Shift Register and Control Data Latches Configuration

Table 3. 48-Bit Shift Register Data Bit Assignment

BITS BIT NAME CONTROLLED CHANNEL/FUNCTIONS

0 to 11 GSOUT2 GS data bits 0 to 11 for OUT2

12 to 23 GSOUT1 GS data bits 0 to 11 for OUT1

24 to 35 GSOUT0 GS data bits 0 to 11 for OUT0

36 to 47 WRTCMD

Data write command (3AAh) for GS data.

The lower 36-bit GS data in the 48-bit shift register are copied to the GS data latch

when the internal GS latch is generated (when these data bits are 3AAh,

001110101010b).

l TEXAS INSTRUMENTS l l W" T T "H 7 § 7 % f' f' +7 +7 4 4

GND

VCC

Controller

OUT0

SDO

SDI

VCC

GND

IREF

OUT1

OUT2

Device

OUT0

SDO

SDI

VCC

GND

IREF

OUT1

OUT2

Device

RIREF RIREF

Power

Supply

(5 V)

TLC5973

SBVS225B –MARCH 2013–REVISED MAY 2014

www.ti.com

Product Folder Links: TLC5973

9 Applications and Implementation

9.1 Application Information

The device is a constant sink current LED driver. This device is typically used to minimize wiring cost in

applications and also provides no restrictions of cascading multiple devices in series. Furthermore, the device

maximum data transfer rate is 3 Mbps and can contribute high-frequency display data change rates. The

following design procedures can be used to maximize application design with minimal wiring cost. The device is

also a good choice for higher VCC power-supply voltage applications because of the internal shunt regulator

included in the device.

9.2 Typical Applications

9.2.1 No Internal Shunt Regulator Mode 1

This application does not use the shunt regulator. However, the device VCC and LED lamp anode voltage can

be supplied from the same power supply because only one LED lamp is connected in series.

Figure 22. No Internal Shunt Regulator Mode 1 Typical Application Circuit

9.2.1.1 Design Requirements

Table 4. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE

Input voltage range for VCC 3.0 V or LED forward voltage (VF) + 1 V to 5.5 V

SDI voltage range Low level = GND, high level = VCC

SDI data transfer rate 100 kbps to 3 Mbps

9.2.1.2 Detailed Design Procedure

The OUTn(n = 0 to 2) constant output current is set by an external resistor connected between the device IREF

and GND pins. Use Equation 1 to calculate the requirements for RIREF.

l TEXAS INSTRUMENTS . mmvw“-~M4 «Mu .44».merw-wruwk’w’vdwwwr‘4 win-m" M“ w»: .0 M, WM ‘ «w.» w . ,...~wu‘w m m... 1w «Mm w m“ MW»"Mm-Mm”muwmmuwmm.

VCC (2V/div)

VOUTn (2V/div, Blue LED Connected)

SDI (2V/div)

TLC5973

www.ti.com

SBVS225B –MARCH 2013–REVISED MAY 2014

Product Folder Links: TLC5973

9.2.1.3 Application Curve

One LED is connected to each output.

VCC = 5 V RIREF = 2.7 kΩSDI high = 5 V

GS data = 7FFh (50% on duty)

Figure 23. No Internal Shunt Regulator Mode 1 Waveform

l TEXAS INSTRUMENTS

SDO

GND

VCC

Controller

OUT0

SDO

SDI

VCC

IREF

OUT1

OUT2

Device

VLED

OUT0

SDI

VCCGND

IREF

OUT1

OUT2

Device

Optional

RIREF

LED

Lamp

Power

Supply

Device and

Controller

Power

Supply

RIREF

Optional

TLC5973

SBVS225B –MARCH 2013–REVISED MAY 2014

www.ti.com

Product Folder Links: TLC5973

9.2.2 No Internal Shunt Regulator Mode 2

This application does not use the shunt regulator. However, the device VCC and LED lamp anode voltage are

supplied from different power supplies.

Figure 24. No Internal Shunt Regulator Mode 2 Typical Application Circuit

9.2.2.1 Design Requirements

Table 5. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE

Input voltage range for VCC 3.0 V to 5.5 V

Input voltage range for LED lamp LED forward voltage (VF) × the number of LED lamps + 1 V;

maximum voltage is 24 V

SDI voltage range Low level = GND, high level = VCC

SDI data frequency 100 kbps to 3 Mbps

9.2.2.2 Detailed Design Procedure

The OUTn(n = 0 to 2) constant output current is set by an external resistor connected between the device IREF

and GND pins. Use Equation 1 to calculate the requirements for RIREF.

l TEXAS INSTRUMENTS wwwwawwmwrwmwm.,..,w.m~.w.mww. y.“ .yy....,,.,‘m .«v "um .. W... WM...”- www.m‘...» 'vr»mmm.nm AM Wm m A“ Mm. .. . AW “w. w Mm.“ w w. ww‘w wAlrwmwwwwmw-Wuw‘ﬂnll wwwmw

VCC (5V/div)

VOUTn (2V/div, Blue LED Connected)

SDI (2V/div)

VLED (5V/div)

TLC5973

www.ti.com

SBVS225B –MARCH 2013–REVISED MAY 2014

Product Folder Links: TLC5973

9.2.2.3 Application Curve

Six LEDs are connected in series to each output.

VCC = 3.3 V VLED = 21 V RIREF = 2.7 kΩ

SDI high = 3.3 V GS data = 7FFh (50% on duty)

Figure 25. No Internal Shunt Regulator Mode 2 Waveform

l TEXAS INSTRUMENTS 13mA 1“ mA

+5 V

SDO

GND

Controller

OUT0

SDO

SDI

VCC

IREF

OUT1

OUT2

2nd Device

VLED

OUT0

SDI

VCCGND

IREF

OUT1

OUT2

1st Device

CVCC

(0.1 F)m

RVCC

Power

Supply

(0.1 F)

VCC

RVCC

Optional

RIREF RIREF

< RVCC <

V (V) 5.9 V

LED

13 mA

V (V) 5.9 V

LED

11 mA

+5 V

SDO

GND

Controller

OUT0

SDO

SDI

VCC

IREF

OUT1

OUT2

Device

VLED

OUT0

SDI

VCCGND

IREF

OUT1

OUT2

Device

CVCC

RVCC

Power

Supply

CVCC

RVCC

Optional

RIREF RIREF

Optional

TLC5973

SBVS225B –MARCH 2013–REVISED MAY 2014

www.ti.com

Product Folder Links: TLC5973

9.2.3 Internal Shunt Regulator Mode

This application uses the shunt regulator. The device VCC and LED lamp anode voltage are supplied from the

same power supply. At least two LED lamps are connected in series.

Figure 26. Internal Shunt Regulator Mode Typical Application Circuit

9.2.3.1 Design Requirements

Table 6. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE

Input voltage range for VLED 6 V to 24 V

SDI voltage range Low level = GND, high level = 5.0 V to 6.0 V

SDI data transfer rate 100 kbps to 3 Mbps

9.2.3.2 Detailed Design Procedure

The TLC5973 internally integrates a shunt regulator to regulate VCC voltage. Refer to Figure 27 for an application

circuit that uses the internal shunt regulator through a resistor, RVCC. The recommended RVCC value can be

calculated by Equation 2.

(2)

Figure 27. Internal Shunt Regulator Mode Application Circuit

l TEXAS INSTRUMENTS WMMMWW MWVWMMﬁWNﬂ ,m ...., M‘V...ww.. a...“ w. .4, M...“ ,w “an W.~m..ﬂm M“. ‘4va hlwwnwﬂwwwuwmww ”W‘wwwrnm‘ vwwmy\ m m m 7 ‘57 WM.wWMWWMWWNWMMWMWMWM w w: .».;.....m...... “My MM”, "4“,...“ ”WWW. "W. mwvmw‘m» ,m» ham: 4 «Mam», «Mumn "ﬂaw-r.- < «m="" ”wnw="" wow»="" r="" mm-dwr’wmwmmmmhu="" «m.="" u.»="" w="" mm."="" .="" m="" .m="" um="" "nh="" ‘-="">

VCC (5V/div)

VOUTn (2V/div, Blue LED Connected)

SDI (2V/div)

VLED (5V/div)

VCC (5V/div, Shunt Regulator Voltage)

VOUTn (2V/div, Blue LED Connected)

SDI (2V/div)

VLED (5V/div)

TLC5973

www.ti.com

SBVS225B –MARCH 2013–REVISED MAY 2014

Product Folder Links: TLC5973

(1) RIREF is at 1.5 kΩ.

Table 7 shows the typical resistor value for several VLED voltages. Note that the CVCC value should be 0.1 μF.

Table 7. Resistor Example for Shunt Resistor versus LED Voltage(1)

VLED (V) RVCC (Ω) RESISTOR WATTAGE (W)

9 270 0.04

12 510 0.07

18 1000 0.15

24 1500 0.22

9.2.3.3 Application Curves

Six LEDs are connected in series to each output.

VLED = 21 V RIREF = 2.7 kΩRVCC = 1.2 kΩ

SDI high = 6 V GS data = 7FFh (50% on duty)

Figure 28. Internal Shunt Regulator Mode Waveform 1

VLED = 21 V RIREF = 2.7 kΩRVCC = 1.2 kΩ

SDI high = 6 V GS data = 7FFh (50% on duty)

Figure 29. Internal Shunt Regulator Mode Waveform 2

{if Tans INSTRUMENTS

Via

Bottom-Side PCB Pattern

Top-Side PCB Pattern

OUT0

OUT1

OUT2

GND

VCC

IREF

SDI

SDO

TLC5973

SBVS225B –MARCH 2013–REVISED MAY 2014

www.ti.com

Product Folder Links: TLC5973

10 Power Supply Recommendations

The power supply voltage should be well regulated. An electrolytic capacitor must be used to reduce the voltage

ripple to less than 5% of the input voltage.

11 Layout

11.1 Layout Guidelines

• The resistor used for the output current setting should be placed near the IREF and GND pins of the device.

• The decoupling capacitor and the shunt regulator resistor should be placed near the VCC pin of the device.

11.2 Layout Example

Figure 30. Layout Example

l TEXAS INSTRUMENTS

TLC5973

www.ti.com

SBVS225B –MARCH 2013–REVISED MAY 2014

Product Folder Links: TLC5973

12 Device and Documentation Support

12.1 Trademarks

EasySet is a trademark of Texas Instruments, Inc.

All other trademarks are the property of their respective owners.

12.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS Sample: Sample:

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TLC5973D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5973

TLC5973DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5973

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension desIgned Io eeeemmodaIe me component Iengm K0 Dlmenslun desIgned to accommodate me componem Ihlckness 7 w Overall with loe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TLC5973DR SOIC D 8 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLC5973DR SOIC D 8 2500 340.5 336.1 25.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 2

l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

TLC5973D D SOIC 8 75 507 8 3940 4.32

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 3

‘J

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

Yl“‘+

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Scheda tecnica TLC5973 di Texas Instruments

INFORMAZIONI

GUIDA

CONTATTI

SEGUICI