Scheda tecnica ADG528F di Analog Devices Inc.

ANALOG DEVICES
8-Channel Fault-Protected
Analog Multiplexer
ADG528F
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2001–2011 Analog Devices, Inc. All rights reserved.
FEATURES
Low on resistance (300 Ω typical)
Fast switching times
tON: 250 ns maximum
tOFF: 250 ns maximum
Low power dissipation (3.3 mW maximum)
Fault and overvoltage protection (−40 V to +55 V)
All switches off with power supply off
Analog output of on channel clamped within power
supplies if an overvoltage occurs
Latch-up proof construction
Break-before-make construction
TTL and CMOS compatible inputs
APPLICATIONS
Existing multiplexer applications (both fault-protected and
nonfault-protected)
New designs requiring multiplexer functions
FUNCTIONAL BLOCK DIAGRAM
S1
S8
A0
D
ADG528F
A1 A2 EN
1 OF 8
DECODER
W
R
RS
09655-001
Figure 1.
GENERAL DESCRIPTION
The ADG528F1 is a CMOS analog multiplexer, with the
comprising eight single channels. This multiplexer provides
fault protection. Using a series n-channel, p-channel, n-channel
MOSFET structure, both device and signal source protection is
provided in the event of an overvoltage or power loss. The
multiplexer can withstand continuous overvoltage inputs
from −40 V to +55 V. During fault conditions, the multiplexer
input (or output) appears as an open circuit and only a few
nanoamperes of leakage current will flow. This protects not
only the multiplexer and the circuitry driven by the multiplexer,
but also protects the sensors or signal sources that drive the
multiplexer.
The ADG528F switches one of eight inputs to a common output
as determined by the 3-bit binary address lines A0, A1, and A2.
The ADG528F has on-chip address and control latches that
facilitate microprocessor interfacing. An EN input on the device
is used to enable or disable the device. When disabled, all channels
are switched off.
PRODUCT HIGHLIGHTS
1. Fault protection.
The ADG528F can withstand continuous voltage inputs
from −40 V to +55 V. When a fault occurs due to the
power supplies being turned off, all the channels are turned
off and only a leakage current of a few nanoamperes flows.
2. On channel turns off while fault exists.
3. Low RON.
4. Fast switching times.
5. Break-before-make switching.
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
6. Trench isolation eliminates latch-up.
A dielectric trench separates the p-channel and n-channel
MOSFETs thereby preventing latch-up.
ADG528F
Rev. F | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Dual Supply ................................................................................... 3
Truth Table .................................................................................... 4
Timing Diagrams .......................................................................... 5
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions ..............................7
Typical Performance Characteristics ..............................................8
Terminology .................................................................................... 10
Theory of Operation ...................................................................... 11
Test Circuits ..................................................................................... 12
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
7/11—Rev. E to Rev. F
Deleted ADG508F/ADG509F .......................................... Universal
Changes to Table 3 ............................................................................ 6
Added Table 4 .................................................................................... 7
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 15
7/09—Rev. D to Rev. E
Updated Format .................................................................. Universal
Added TSSOP ..................................................................... Universal
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 18
4/01—Data Sheet Changed from Rev. C to Rev. D.
Changes to Ordering Guide ............................................................ 1
Changes to Specifications Table ...................................................... 2
Max Ratings Changed ...................................................................... 4
Deleted 16-Lead Cerdip from Outline Dimensions .................. 11
Deleted 18-Lead Cerdip from Outline Dimensions .................. 12
ADG528F
Rev. F | Page 3 of 16
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
B Version
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS + 3 V min
V
DD − 1.5 V max
RON 300 350 Ω typ −10 V ≤ VS ≤ +10 V, IS = 1 mA;
V
DD = +15 V ± 10%, VSS = −15 V ± 10%
400 Ω max −10 V ≤ VS ≤ +10 V, IS = 1 mA;
V
DD = +15 V ± 5%, VSS = −15 V ± 5%
RON Drift 0.6 %/°C typ VS = 0 V, IS = 1 mA
RON Match 5 % max VS = 0 V, IS = 1 mA
LEAKAGE CURRENTS
Source Off Leakage IS (Off) ±0.02 nA typ VD = ±10 V, VS = +10 V;
±1 ±50 nA max See Figure 19
Drain Off Leakage ID (Off) ±0.04 nA typ VD = ±10 V, VS = +10 V;
±1 ±60 nA max See Figure 20
Channel On Leakage ID, IS (On) ±0.04 nA typ VS = VD = ± 10 V;
±1 ±60 nA max See Figure 21
FAULT
Output Leakage Current ±0.02 nA typ VS = ±33 V, VD = 0 V, see Figure 20
(With Overvoltage) ±2 ±2 μA max
Input Leakage Current ±0.005 μA typ VS = ±25 V, VD = +10 V, see Figure 22
(With Overvoltage) ±2 μA max
Input Leakage Current ±0.001 μA typ VS = ±25 V, VD = VEN = A0, A1, A2 = 0 V
(With Power Supplies Off) ±2 μA max See Figure 23
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH ±1 μA max VIN = 0 or VDD
CIN, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS1
tTRANSITION 200 ns typ RL = 1 MΩ, CL = 35 pF;
300 400 ns max VS1 = ±10 V, VS8 = +10 V; see Figure 24
tOPEN 50 ns typ RL = 1 kΩ, CL = 35 pF;
25 10 ns min VS = 5 V; see Figure 25
tON (EN, WR) 200 ns typ RL = 1 kΩ, CL = 35 pF;
250 400 ns max VS = 5 V; see Figure 26
tOFF (EN, RS) 200 ns typ RL = 1 kΩ, CL = 35 pF;
tSETT, Settling Time 250 400 ns max VS = 5 V; see Figure 26
0.1% 1 μs typ RL = 1 kΩ, CL = 35 pF;
0.01% 2.5 μs typ VS = 5 V
tW, Write Pulse Width 100 120 ns min
tS, Address, Enable Setup Time 100 ns min
tH, Address, Enable Hold Time 10 ns min
tRS, Reset Pulse Width 100 ns min
ADG528F
Rev. F | Page 4 of 16
B Version
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
Charge Injection 4 pC typ VS = 0 V, RS = 0 Ω, CL= 1 nF; see Figure 29
Off Isolation 68 dB typ RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
50 dB min VS = 7 V rms; see Figure 30
CS (Off) 5 pF typ
CD (Off) 50 pF typ
POWER REQUIREMENTS
IDD 0.1 0.2 mA max VIN = 0 V or 5 V
ISS 0.1 0.1 mA max
1 Guaranteed by design, not subject to production test.
TRUTH TABLE
Table 2. ADG528F Truth Table1
A2 A1 A0 EN WR RS On Switch
X X X X 1 Retains previous switch condition
X X X X X 0 None (address and enable latches cleared)
X X X 0 0 1 None
0 0 0 1 0 1 1
0 0 1 1 0 1 2
0 1 0 1 0 1 3
0 1 1 1 0 1 4
1 0 0 1 0 1 5
1 0 1 1 0 1 6
1 1 0 1 0 1 7
1 1 1 1 0 1 8
1 X = don’t care.
ADG528F
Rev. F | Page 5 of 16
TIMING DIAGRAMS
Figure 2 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
therefore, while WR is held low, the latches are transparent
and the switches respond to the address and enable inputs.
This input data is latched on the rising edge of WR.
shows the reset pulse width, tRS, and the reset turnoff time, tOFF
(
Figure 3
RS). Note that all digital input signals rise and fall times are
measured from 10% to 90% of 3 V. tR = tF = 20 ns.
tW
50% 50%
tS
tH
0.8V
2V
3
V
WR
0V
3V
0V
A
0, A1, A2
EN
09655-002
Figure 2. Timing Sequence for Latching the Switch Address and Enable Inputs
t
RS
50% 50%
0.8V
OUT
3
V
RS
0V
V
OUT
SWITCH
OUTPUT
t
OFF
(RS)
0V
09655-003
Figure 3. Reset Pulse Width
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ADG528F
Rev. F | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Table 3.
Parameter Rating
VDD to VSS 44 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Digital Input, EN, Ax −0.3 V to VDD + 2 V or 20 mA,
whichever occurs first
VS, Analog Input Overvoltage with
Power On (VDD = +15 V, VSS = −15 V)
VSS − 25 V to VDD + 40 V
VS, Analog Input Overvoltage with
Power Off (VDD = 0 V, VSS = 0 V)
−40 V to +55 V
Continuous Current, S or D 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) 40 mA
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA, Thermal Impedance 90°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADG528F
Rev. F | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1201923
4
5
6
7
8
18
17
16
15
14
910 11 12 13
NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
EN
V
SS
S1
S2
S3
A2
GND
V
DD
S5
S6
A0
WR
NC
RS
A1
S4
D
NC
S8
S7
PIN 1
INDENTFIER
ADG528F
TOP VIEW
(Not to Scale)
09655-007
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 NC
No Connect. This pin is open.
2 WR Write. The WR signal latches the state of the address control lines and the enable line.
3 A0 Logic Control Input.
4 EN
Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
5 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
6 S1 Source Terminal 1. This pin can be an input or an output.
7 S2 Source Terminal 2. This pin can be an input or an output.
8 S3 Source Terminal 3. This pin can be an input or an output.
9 S4 Source Terminal 4. This pin can be an input or an output.
10 D Drain Terminal. This pin can be an input or an output.
11 NC
No Connect. This pin is open.
12 S8 Source Terminal 8. This pin can be an input or an output.
13 S7 Source Terminal 7. This pin can be an input or an output.
14 S6 Source Terminal 6. This pin can be an input or an output.
15 S5 Source Terminal 5. This pin can be an input or an output.
16 VDD Most Positive Power Supply Potential.
17 GND Ground (0 V) Reference.
18 A2 Logic Control Input.
19 A1 Logic Control Input.
20 RS Reset. The RS signal clears both the address and enable data in the latches resulting in no
output (all switches off).
ADG528F
Rev. F | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
2000
1000
0
15–15 –10 –5 0 5 10
500
1750
1500
1250
750
250
V
D
, V
S
(V)
R
ON
(Ω)
T
A
= 25°C
V
DD
= +5V
V
SS
= –5V
V
DD
= +10V
V
SS
= –10V
V
DD
= +15V
V
SS
= –15V
09655-008
2000
1000
0
15–15 –10 –5 0 5 10
500
1750
1500
1250
750
250
V
D
, V
S
(V)
R
ON
(Ω)
V
DD
= +15V
V
SS
= –15V
T
A
= 125°C
T
A
= 85°C
T
A
= 25°C
09655-011
Figure 5. On Resistance as a Function of VD (VS) Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures
1m
1µ
1p
–50 –30 –20 –10 0 10 20 30 40 50 60
–40
1n
100µ
10µ
10n
100n
10p
100p
V
IN
INPUT VOLTAGE (V)
I
S
INPUT LEAKAGE (A)
OPERATING RANGE
V
DD
= 0V
V
SS
= 0V
V
D
= 0V
09655-009
1m
1µ
1p
–50 –30 –20 –10 0 10 20 30 40 50 60
–40
1n
100µ
10µ
10n
100n
10p
100p
INPUT VOLTAGE (V)
I
S
INPUT LEAKAGE (A)
OPERATING RANGE
V
DD
= +15V
V
SS
= –15V
V
D
= 0V
09655-012
Figure 6. Input Leakage Current as a Function of VS (Power Supplies Off)
During Overvoltage Conditions
Figure 9. Input Leakage Current as a Function of VS (Power Supplies On)
During Overvoltage Conditions
0.3
0.2
–0.2
–14 –10 –6 –2 2 6 10 14
0.1
0
–0.1
V
S
,V
D
(V)
LEAKAGE CURRENTS (nA)
I
S
(OFF)
I
S
(OFF)
I
S
(ON)
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
09655-013
1m
1µ
1p
–50 –30 –20 –10 0 10 20 30 40 50 60
–40
1n
100µ
10µ
10n
100n
10p
100p
V
IN
INPUT VOLTAGE (V)
I
D
INPUT LEAKAGE (A)
OPERATING RANGE
V
DD
= +15V
V
SS
= –15V
V
D
= 0V
09655-010
Figure 7. Output Leakage Current as a Function of VS (Power Supplies On)
During Overvoltage Conditions
Figure 10. Leakage Currents as a Function of VD (VS)
ADG528F
Rev. F | Page 9 of 16
100
10
0.01
45 5525 65 75 85 95 10535
1
115 125
0.1
TEMPERATURE (°C)
LEAKAGE CURRENTS (nA)
V
DD
= +15V
V
SS
= –15V
V
D
= +10V
V
S
= –10V
I
S
(OFF)
I
D
(ON)
I
D
(OFF)
09655-014
Figure 11. Leakage Currents as a Function of Temperature
260
240
100
10 11 12 13 14 15
120
t
ON
(EN)
220
200
180
160
140
SWITCHING TIME (ns)
POWER SUPPLY (V)
V
IN
= 2V
t
TRANSITION
t
OFF
(EN)
09655-015
Figure 12. Switching Time vs. Power Supply
280
240
100
25 45 65 85 105 125
120
220
200
180
160
140
TEMPERATURE (°C)
SWITCHING TIME (ns)
260
V
DD
= +15V
V
SS
= –15V
V
IN
= +5V
t
ON
(EN)
t
TRANSITION
t
OFF
(EN)
09655-016
Figure 13. Switching Time vs. Temperature
ADG528F
Rev. F | Page 10 of 16
TERMINOLOGY
VDD
Most positive power supply potential.
VSS
Most negative power supply potential.
GND
Ground (0 V) reference.
RON
Ohmic resistance between D and S.
RON Drift
Change in RON when temperature changes by one degree
Celsius.
RON Match
Difference between the RON of any two channels.
IS (Off)
Source leakage current when the switch is off.
ID (Off)
Drain leakage current when the switch is off.
ID, IS (On)
Channel leakage current when the switch is on.
VD (VS)
Analog Voltage on Terminal D and Terminal S.
CS (Off)
Channel input capacitance for off condition.
CD (Off)
Channel output capacitance for off condition.
CD, CS (On)
On switch capacitance.
CIN
Digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
tOPEN
Off time measured between 80% points of both switches when
switching from one address state to another.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
Off Isolation
A measure of unwanted signal coupling through an off channel.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
IDD
Positive supply current.
ISS
Negative supply current.
“fill—11ml?” W fill—11ml?” H:
ADG528F
Rev. F | Page 11 of 16
THEORY OF OPERATION
The ADG528F multiplexer is capable of withstanding overvoltages
from −40 V to +55 V, irrespective of whether the power supplies
are present or not. Each channel of the multiplexer consists of an
n-channel MOSFET, a p-channel MOSFET, and an n-channel
MOSFET, connected in series. When the analog input exceeds the
power supplies, one of the MOSFETs will switch off, limiting the
current to submicroamp levels, thereby preventing the overvoltage
from damaging any circuitry following the multiplexer. Figure 14
illustrates the channel architecture that enables these multiplexers
to withstand continuous overvoltages.
When an analog input of VSS + 3 V to VDD − 1.5 V is applied
to the ADG528F, the multiplexer behaves as a standard multi-
plexer, with specifications similar to a standard multiplexer,
for example, the on-resistance is 400 Ω maximum. However,
when an overvoltage is applied to the device, one of the three
MOSFETs will turn off.
Figure 14 to Figure 17 show the conditions of the three MOSFETs
for the various overvoltage situations. When the analog input
applied to an on channel approaches the positive power supply
line, the n-channel MOSFET turns off because the voltage on
the analog input exceeds the difference between VDD and the
n-channel threshold voltage (VTN). When a voltage more nega-
tive than VSS is applied to the multiplexer, the p-channel
MOSFET will turn off because the analog input is more
negative than the difference between VSS and the p-channel
threshold voltage (VTP). Because VTN is nominally 1.5 V and
VTP is typically 3 V, the analog input range to the multiplexer is
limited to −12 V to +13.5 V when a ±15 V power supply is used.
When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will turn off when an overvoltage occurs.
Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches
on the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the series
will remain off because the gate to source voltage applied to this
MOSFET is negative.
During fault conditions, the leakage current into and out of
the ADG528F is limited to a few microamps. This protects the
multiplexer and succeeding circuitry from over stresses as well
as protecting the signal sources, which drive the multiplexer.
Also, the other channels of the multiplexer will be undisturbed
by the overvoltage and will continue to operate normally.
Q1 Q2 Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
OFF
V
DD
V
SS
09655-017
Figure 14. +55 V Overvoltage Input to the On Channel
Q1 Q2 Q3
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON p-CHANNEL
MOSFET IS
OFF
V
SS
V
DD
09655-018
Figure 15. −40 V Overvoltage on an Off Channel with
Multiplexer Power On
Q1 Q2 Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
OFF
09655-019
Figure 16. +55 V Overvoltage with Power Off
Q1 Q2 Q3
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON p-CHANNEL
MOSFET IS
OFF
09655-020
Figure 17. −40 V Overvoltage with Power Off
ADG528F
Rev. F | Page 12 of 16
TEST CIRCUITS
I
DS
S
R
ON
= V
1
/I
DS
V1
V
S
D
09655-021
Figure 18. On Resistance
S1
S2
S8
V
D
I
S
(OFF)
V
S
V
DD
V
SS
V
DD
V
SS
D
0.8VEN
A
09655-022
Figure 19. IS (Off)
S1
S2
S8
V
S
I
D
(OFF)
V
D
V
DD
V
SS
V
DD
V
SS
D
0.8VEN
A
09655-023
Figure 20. ID (Off)
S1
S2
S8
V
S
I
D
(ON)
V
D
V
DD
V
SS
V
DD
V
SS
D
2.4VEN
A
09655-025
Figure 21. ID (On)
S1
S2
S8
V
S
V
DD
V
SS
V
DD
V
SS
D
0.8VEN
A
09655-026
Figure 22. Input Leakage Current (with Overvoltage)
A2
0V
0
V
V
DD
V
SS
V
S
D
0
V
A1
A0
EN
RS
GND WR
ADG528F
S1
S8
A
09655-027
Figure 23. Input Leakage Current (with Power Supplies Off)
?
ADG528F
Rev. F | Page 13 of 16
A2
V
SS
V
DD
D
V
S1
V
IN
V
S8
V
OUT
A1
A0
EN
RS
GND WR
ADG528F
S1
S8
S2 TO S7
2.4V
50Ω
R
L
1MΩ
C
L
35pF
V
SS
V
DD
3V
50%
V
OUT
t
TRANSITION
90%
90%
t
TRANSITION
ADDRESS
DRIVE (V
IN
)50%
09655-024
Figure 24. Switching Time of Multiplexer, tTRANSITION
A2
V
SS
V
DD
D
V
S
V
IN
V
OUT
A1
A0
EN
RS
GND WR
ADG528F
S1
S8
S2 TO S7
2.4V
50Ω
R
L
1kΩ
C
L
35pF
V
SS
V
DD
ADDRESS
DRIVE (V
IN
)
3V
V
OUT
t
OPEN
80% 80%
09655-029
Figure 25. Break-Before-Make Delay, tOPEN
A2
V
SS
V
DD
D
V
S
V
IN
V
OUT
A1
A0
EN
RS
GND WR
ADG528F
S1
S2 TO S8
R
L
1kΩ
C
L
35pF
V
SS
V
DD
ENABLE
DRIVE (V
IN
)
3V
0V
0V
V
OUT
OUTPUT
t
ON
(EN)
t
OFF
(EN)
50%50%
0.9V
OUT
V
RS
09655-030
Figure 26. Enable Delay, tON (EN), tOFF (EN)
A2
V
SS
V
DD
D
V
S
V
RS
V
OUT
A1
A0
EN
2.4V
RS
GND
WR
ADG528F
S1
S2 TO S8
R
L
1kΩ
C
L
35pF
V
SS
V
DD
WR
3V
50%
0V
0V
V
OUT
OUTPUT
V
WR
t
ON
(WR)
0.2V
OUT
09655-031
Figure 27. Write Turn-On Time, tON (WR)
W n? 4:}:
ADG528F
Rev. F | Page 14 of 16
A2
V
DD
V
DD
V
SS
V
SS
D
V
S
V
IN
V
OUT
A1
A0
EN2.4V
RS
GND WR
ADG528F
S1
S2 TO S8
R
L
1kΩ
C
L
35pF
RS
3V
0V
50% 50%
0V
V
OUT
SWITCH
OUTPUT
t
RS
t
OFF
(RS)
0.8V
OUT
09655-032
Figure 28. Reset Turn-Off Time, tOFF (RS)
3V
V
OUT
LOGIC
INPUT (V
IN
)
Q
INJ
= C
L
× ∆V
OUT
0V
A2
V
OUT
D
A1
A0
EN
RS
GND WR
ADG528
2.4V
S
C
L
1nF
V
S
V
SS
V
SS
V
DD
V
DD
V
IN
R
S
∆V
OUT
09655-033
Figure 29. Charge Injection
A2
V
DD
V
DD
V
SS
V
SS
V
IN
DV
OUT
A1
A0
EN
.4V RS
GND WR
S1
S8
R
L
1kΩ
ADG528F
09655-034
Figure 30. Off Isolation
ADG528F
Rev. F | Page 15 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-047-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.020 (0.50)
R
BOTTOM
VIEW
(PINS UP)
0.021 (0.53)
0.013 (0.33) 0.330 (8.38)
0.290 (7.37)
0.032 (0.81)
0.026 (0.66)
0.056 (1.42)
0.042 (1.07) 0.20 (0.51)
MIN
0.120 (3.04)
0.090 (2.29)
3
4
19
18
8
9
14
13
TOP VIEW
(PINS DOWN)
0.395 (10.03)
0.385 (9.78) SQ
0.356 (9.04)
0.350 (8.89)SQ
0.048 (1.22 )
0.042 (1.07)
0.048 (1.22)
0.042 (1.07)
0.020
(0.51)
R
0.050
(1.27)
BSC
0.180 (4.57)
0.165 (4.19)
0.045 (1.14)
0.025 (0.64) R
PIN 1
IDENTIFIER
Figure 31. 20-Lead Plastic Leaded Chip Carrier [PLCC]
(P-20)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADG528FBP −40°C to +85°C 20-Lead PLCC P-20
ADG528FBPZ −40°C to +85°C 20-Lead PLCC P-20
1 Z = RoHS Compliant Part.
ANALOG DEVICES www.analng.cnm
ADG528F
Rev. F | Page 16 of 16
NOTES
©2001–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09655-0-7/11(F)