Scheda tecnica MT88L70 di Microchip Technology

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1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
• 2.7 - 3.6 volt operation
• Complete DTMF receiver
• Low power consumption
• Internal gain setting amplifier
• Adjustable guard time
• Central office quality
• Power-down mode
• Inhibit mode
• Functionally compatible with Zarlink’s MT8870D
Applications
• Paging systems
• Repeater systems/mobile radio
• Credit card systems
• Remote control
• Personal computers
• Telephone answering machine
Description
The MT88L70 is a complete 3 Volt, DTMF receiver
integrating both the bandsplit filter and digital decoder
functions. The filter section uses switched capacitor
techniques for high and low group filters; the decoder
uses digital counting techniques to detect and decode
all 16 DTMF tone-pairs into a 4-bit code. External
component count is minimized by on chip provision of
a differential input amplifier, clock oscillator and latched
three-state bus interface.
August 2005
Ordering Information
MT88L70AE 18 Pin PDIP Tubes
MT88L70AS 18 Pin SOIC Tubes
MT88L70AN 20 Pin SSOP Tubes
MT88L70ASR 18 Pin SOIC Tape & Reel
MT88L70ANR 20 Pin SSOP Tape & Reel
MT88L70AE1 18 Pin PDIP* Tubes
MT88L70AN1 20 Pin SSOP* Tubes
MT88L70ANR1 20 Pin SSOP* Tape & Reel
MT88L70AS1 18 Pin SOIC* Tubes
MT88L70ASR1 18 Pin SOIC* Tape & Reel
* Pb Free Matte Tin
-40°C to +85°C
MT88L70
3 Volt Integrated DTMF Receiver
Data Sheet
Figure 1 - Functional Block Diagram
PWDN
IN +
IN -
GS
OSC1 OSC2 St/GT ESt STD TOE
Q1
Q2
Q3
Q4
VDD VSS VRef INH
Bias
Circuit
Dial
Tone
Filter
High Group
Filter
Low Group
Filter
Digital
Detection
Algorithm
Code
Converter
and Latch
St
GT
Steering
Logic
Chip
Power
Chip
Bias
VRef
Buffer
Zero Crossing
Detectors
to all
Chip
Clocks
3333333333 KKKKKKKKKK 333333333 U KKKKKKKKK 20 PIN SSOP 1a PW PD‘P/SOIC
MT88L70 Data Sheet
2
Zarlink Semiconductor Inc.
Figure 2 - Pin Connections
Pin Description
Pin #
Name Description
18 20
11 IN+Non-Inverting Op-Amp (Input).
22 IN-Inverting Op-Amp (Input).
33 GSGain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
44 V
Ref Reference Voltage (Output). Nominally VDD/2 is used to bias inputs at mid-rail (see Figure 5
and Figure 6).
55 INHInhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C and
D. This pin input is internally pulled down.
6 6 PWDN Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This
pin input is internally pulled down.
78OSC1Clock (Input).
89OSC2Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2
completes the internal oscillator circuit.
910 V
SS Ground (Input). 0 V typical.
10 11 TOE Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is pulled
up internally.
11-
14
12-
15
Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
15 17 StD Delayed Steering (Output).Presents a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below VTSt.
16 18 ESt Early Steering (Output). Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to
a logic low.
1
2
3
4
5
6
7
8
910
18
17
16
15
14
13
12
11
IN+
IN-
GS
VRef
INH
PWDN
OSC1
OSC2
VSS
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
18 PIN PDIP/SOIC
1
2
3
4
5
6
7
8
9
10 11
12
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
INH
PWDN
NC
OSC1
OSC2
VSS
20 PIN SSOP
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
NC
MT88L70 Data Sheet
3
Zarlink Semiconductor Inc.
Functional Description
The MT88L70 monolithic DTMF receiver offers small size, low power consumption and high performance, with 3
volt operation. Its architecture consists of a bandsplit filter section, which separates the high and low group tones,
followed by a digital counting section which verifies the frequency and duration of the received tones before passing
the corresponding code to the output bus.
Filter Section
Separation of the low-group and high group tones is achieved by applying the DTMF signal to the inputs of two
sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group
frequencies. The filter section also incorporates notches at 350 and 440 Hz for exceptional dial tone rejection. Each
filter output is followed by a single order switched capacitor filter section which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of
unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the
incoming DTMF signals.
Decoder Section
Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the
incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm
protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency
deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the
detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry
specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition
will cause ESt to assume an inactive state (see “Steering Circuit”).
Steering Circuit
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character
recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt
causes vc (see Figure 3) to rise as the capacitor discharges. Provided signal condition is maintained (ESt remains
high) for the validation period (tGTP), vc reaches the threshold (VTSt) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1) into the output latch. At this point the GT output is activated and
drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the
output latch to settle, the delayed steering output flag (StD) goes high, signalling that a received tone pair has been
registered. The contents of the output latch are made available on the 4-bit output bus by raising the three state
control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between
signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal
interruptions (dropout) too short to be considered a valid pause. This facility, together with the capability of selecting
17 19 St/GT Steering Input/Guard time (Output) Bidirectional. A voltage greater than VTSt detected at
St causes the device to register the detected tone pair and update the output latch. A voltage
less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the
external steering time-constant; its state is a function of ESt and the voltage on St.
18 20 VDD Positive power supply (Input). +3 V typical.
7, 16 NC No Connection.
Pin Description
Pin #
Name Description
18 20
MT88L70 Data Sheet
4
Zarlink Semiconductor Inc.
the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system
requirements.
Table 1 - Functional Decode Table
L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE
X = DON‘T CARE
Guard Time Adjustment
In many situations not requiring selection of tone duration and interdigital pause, the simple steering circuit shown
in Figure 3 is applicable. Component values are chosen according to the formula:
tREC=tDP+tGTP
tID=tDA+tGTA
The value of tDP is a device parameter (see Figure 7) and tREC is the minimum signal duration to be recognized by
the receiver. A value for C of 0.1 µF is recommended for most applications, leaving R to be selected by the
designer.
Digit TOE INH ESt Q4Q3Q2Q1
ANYLXHZZZZ
1 HXH0001
2 HXH0010
3 HXH0011
4 HXH0100
5 HXH0101
6 HXH0110
7 HXH0111
8 HXH1000
9 HXH1001
0 HXH1010
* HXH1011
# HXH1100
A HLH1101
B HLH1110
C HLH1111
D HLH0000
AHHL
undetected, the output code
will remain the same as the
previous detected code
BHHL
CHHL
DHHL
[xii Edi
MT88L70 Data Sheet
5
Zarlink Semiconductor Inc.
Figure 3 - Basic Steering Circuit
Different steering arrangements may be used to select independently the guard times for tone present (tGTP) and
tone absent (tGTA). This may be necessary to meet system specifications which place both accept and reject limits
on both tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system
parameters such as talk off and noise immunity. Increasing tREC improves talk-off performance since it reduces the
probability that tones simulated by speech will maintain signal condition long enough to be registered. Alternatively,
a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure
4.
Power-down and Inhibit Mode
A logic high applied to pin 6 (PWDN) will power down the device to minimize the power consumption in a standby
mode. It stops the oscillator and the functions of the filters.
Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of tones representing
characters A, B, C, and D. The output code will remain the same as the previous detected code (see Table 1).
Figure 4 - Guard Time Adjustment
C
vc
VDD
St/GT
ESt
StD
MT88L70
R
tGTA=(RC)In(VDD/VTSt)
tGTP=(RC)In[VDD/(VDD-VTSt)]
VDD
VDD
St/GT
ESt
R1
C1
R2
VDD
St/GT
ESt
C1
R1R2
a) decreasing tGTP; (tGTP < tGTA)
b) decreasing tGTA; (tGTP > tGTA)
tGTA=(R1C1) In (VDD / VTSt)
tGTP=(RPC1) In [VDD / (VDD-VTSt)]
RP = (R1R2) / (R1 + R2)
tGTA=(RPC1) In (VDD / VTSt)
tGTP=(R1C1) In [VDD / (VDD-VTSt)]
RP = (R1R2) / (R1 + R2)
D—II—vvw
MT88L70 Data Sheet
6
Zarlink Semiconductor Inc.
Differential Input Configuration
The input arrangement of the MT88L70 provides a differential-input operational amplifier as well as a bias source
(VRef) which is used to bias the inputs at mid-rail. Provision is made for connection of a feedback resistor to the op-
amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in
Figure 6 with the op-amp connected for unity gain and VRef biasing the input at 1/2VDD. Figure 5 shows the
differential configuration, which permits the adjustment of gain with the feedback resistor R5.
Figure 5 - Differential Input Configuration
Crystal Oscillator
The internal clock circuit is completed with the addition of an external 3.579545 MHz crystal and is connected as
shown in Figure 6 (Single-ended Input Configuration).
C1R1
C2R4
IN+
IN-
R5
R2
R3
GS
VRef
+
-
MT88L70
DIFFERNTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60 kΩ, R3, = 37.5 kΩ
R3 = R2R5
R2 + R5
VOLTAGE GAIN (AV diff) = R5
R1
INPUT IMPEDANCE
(ZINDIFF) = 2 R12 + 1
ωC
2
All resistors are ± 1% tolerance.
All capacitors are ± 5% tolerance.
MT88L70 Data Sheet
7
Zarlink Semiconductor Inc.
Applications
A single-ended input configuration is shown in Figure 6. For applications with differential signal inputs the circuit
shown in Figure 5 may be used.
Figure 6 - Single-Ended Input Configuration
IN+
IN-
GS
VRef
INH
PDWN
OSC1
OSC2
VSS
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
DTMF
Input
C1
VDD
R1
R2
X-tal
MT88L70
C2
R3
NOTES:
R1, R2 = 100 kΩ ±1%
R3 = 300 kΩ ±1%
C1,C2 = 100 nF ±5%
X-tal = 3.579545 MHz ±0.1%
VDD = 3.0V + 20% / -10%
MT88L70 Data Sheet
8
Zarlink Semiconductor Inc.
† Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Derate above 75 °C at 16 mW / °C. All leads soldered to board.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Absolute Maximum Ratings†
Parameter Symbol Min. Max. Units
1 DC Power Supply Voltage VDD 7V
2 Voltage on any pin VIVSS-0.3 VDD+0.3 V
3 Current at any pin (other than supply) II10 mA
4 Storage temperature TSTG -65 +150 °C
5 Package power dissipation PD500 mW
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter Sym. Min. Typ.‡Max. Units Test Conditions
1 DC Power Supply Voltage VDD 2.7 3.0 3.6 V
2 Operating Temperature TO-40 +85 °C
3 Crystal/Clock Frequency fc 3.579545 MHz
4 Crystal/Clock Freq.Tolerance ∆fc ±0.1 %
DC Electrical Characteristics - VDD = 3.0 V+ 20%/-10%, VSS = 0 V, -40°C ≤ TO ≤ +85°C, unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1S
U
P
P
L
Y
Standby supply current IDDQ 110µA PWDN=VDD
2 Operating supply current IDD 2.0 5.5 mA
3 Power consumption PO6mWf
c=3.579545 MHz
4
I
N
P
U
T
S
High level input VIH 2.1 V VDD = 3.0 V
5 Low level input voltage VIL 0.9 V VDD = 3.0 V
6 Input leakage current IIH/IIL 0.05 5 µAV
IN = VSS or VDD
7 Pull up (source) current ISO 415µA TOE (pin 10) = 0,
VDD = 3.0 V
8 Pull down (sink) current ISI 15 40 µA INH = VDD, PWDN =
VDD, VDD = 3.0 V
9 Input impedance (IN+, IN-) RIN 10 MΩ@ 1 kHz
10 Steering threshold voltage VTSt 0.465VDD V
t Typmal figures are at 25 c and are for deswgn am only. nm guaranteed and not subject to pruduchun 155mg.
MT88L70 Data Sheet
9
Zarlink Semiconductor Inc.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
11
O
U
T
P
U
T
S
Low level output voltage VOL VSS+0.03 V No load
12 High level output voltage VOH VDD-0.03 V No load
13 Output low (sink) current IOL 1.5 8 mA VOUT = 0.4 V
14 Output high (source)
current
IOH 1.0 3.0 mA VOUT = 3.6 V,
VDD = 3.6 V
15 VRef output voltage VRef 0.512VDD V No load
16 VRef output resistance ROR 1kΩ
Operating Characteristics - VDD = 3.0 V+20%/-10%, VSS = 0 V, -40°C ≤ TO ≤ +85°C, unless otherwise stated.
Gain Setting Amplifier
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Input leakage current IIN 100 nA VSS ≤ VIN ≤ VDD
2 Input resistance RIN 10 MΩ
3 Input offset voltage VOS 25 mV
4 Power supply rejection PSRR 50 dB 1 kHz
5 Common mode rejection CMRR 40 dB VSS + 0.75 V ≤ VIN ≤
VDD-0.75
biased at VRef =1.5 V
6 DC open loop voltage gain AVOL 32 dB
7 Unity gain bandwidth fC0.30 MHz
8 Output voltage swing VO2.2 Vpp Load ≥ 100 kΩ to VSS @ GS
9 Maximum capacitive load (GS) CL100 pF
10 Resistive load (GS) RL50 kΩ
11 Common mode range VCM 1.5 Vpp No Load
DC Electrical Characteristics - VDD = 3.0 V+ 20%/-10%, VSS = 0 V, -40°C ≤ TO ≤ +85°C, unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
MT88L70 Data Sheet
10
Zarlink Semiconductor Inc.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES
1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.
2. Digit sequence consists of all DTMF tones.
3. Tone duration= 40 ms, tone pause= 40 ms.
4. Signal condition consists of nominal DTMF frequencies.
5. Both tones in composite signal have an equal amplitude.
6. Tone pair is deviated by ±1.5%± 2Hz.
7. Bandwidth limited (3 kHz) Gaussian noise.
8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2%.
9. For an error rate of better than 1 in 10,000.
10. Referenced to lowest level frequency component in DTMF signal.
11. Referenced to the minimum valid accept level.
12. Guaranteed by design and characterization.
AC Electrical Characteristics - VDD = 3.0 V +20%/-10%, VSS = 0 V, -40°C ≤ TO ≤ +85°C, using Test Circuit shown in Fig. 6.
Characteristics Sym Min. Typ‡Max Units Notes*
1 Valid input signal levels
(each tone of composite
signal)
-34
15.4
-4.0
489
dBm
mVRMS
1,2,3,5,6,9
Min @ VDD=3.6 V
Max @ VDD=2.7 V
2 Negative twist accept 8 dB 2,3,6,9,12
3 Positive twist accept 8 dB 2,3,6,9,12
4 Frequency deviation accept ±1.5% ± 2 Hz 2,3,5,9
5 Frequency deviation reject ±3.5% 2,3,5,9
6 Third zone tolerance -16 dB 2,3,4,5,9,10
7 Noise tolerance -12 dB 2,3,4,5,7,9,10
8 Dial zone tolerance +22 dB 2,3,4,5,8,9,11
MT88L70 Data Sheet
11
Zarlink Semiconductor Inc.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES:
1. Used for guard-time calculation purposes only and tested at -4 dBm.
2. These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums are
recommendations based upon network requirements.
3. With valid tone present at input, tPU equals time from PDWN going low until ESt going high.
AC Electrical Characteristics - VDD = 3.0 V+20%/-10%, VSS =0V, -40°C ≤ To ≤ +85°C, using Test Circuit shown in Figure 6.
Characteristics Sym. Min. Typ.‡Max. Units Conditions
1
T
I
M
I
N
G
Tone present detect time tDP 51114msNote 1
2 Tone absent detect time tDA 0.548.5msNote 1
3 Tone duration accept tREC 40 ms Note 2
4 Tone duration reject tREC 20 ms Note 2
5 Interdigit pause accept tID 40 ms Note 2
6 Interdigit pause reject tDO 20 ms Note 2
7
O
U
T
P
U
T
S
Propagation delay (St to Q) tPQ 11 µsTOE=V
DD
8 Propagation delay (St to StD) tPStD 20 µsTOE=VDD
9 Output data set up (Q to StD) tQStD 5.0 µsTOE=VDD
10 Propagation delay (TOE to Q ENABLE) tPTE 50 ns load of 10 kΩ,
50 pF
11 Propagation delay (TOE to Q DISABLE) tPTD 130 ns load of 10 kΩ,
50 pF
12 P
D
W
N
Power-up time tPU 30 ms Note 3
13 Power-down time tPD 20 ms
14
C
L
O
C
K
Crystal/clock frequency fC3.5759 3.5795 3.5831 MHz
15 Clock input rise time tLHCL 110 ns Ext. clock
16 Clock input fall time tHLCL 110 ns Ext. clock
17 Clock input duty cycle DCCL 40 50 60 % Ext. clock
18 Capacitive load (OSC2) CLO 15 pF
gr M N A 4‘ IT‘ ‘9 F a H ‘ewwwwww 1 T ‘9‘ a a a Dr A —>l‘\<—>
MT88L70 Data Sheet
12
Zarlink Semiconductor Inc.
Figure 7 - Timing Diagram
EXPLANATION OF EVENTS
A) TONE BURSTS DETECTED, TONE DURATION INVALID, OUTPUTS NOT UPDATED.
B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS.
C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT VALID
TONE.
D) OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE.
E) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY
HIGH IMPEDANCE).
F) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, OUTPUTS REMAIN LATCHED.
G) END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT
VALID TONE.
EXPLANATION OF SYMBOLS
Vin DTMF COMPOSITE INPUT SIGNAL.
ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
Q1-Q44-BIT DECODED TONE OUTPUT.
StD DELAYED STEERING OUTPUT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE
REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL.
TOE TONE OUTPUT ENABLE (INPUT). A LOW LEVEL SHIFTS Q1-Q4 TO ITS HIGH IMPEDANCE STATE.
tREC MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.
tREC MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.
tID MINIMUM TIME BETWEEN VALID DTMF SIGNALS.
tDO MAXIMUM ALLOWABLE DROP OUT DURING VALID DTMF SIGNAL.
tDP TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS.
tDA TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS.
tGTP GUARD TIME, TONE PRESENT.
tGTA GUARD TIME, TONE ABSENT.
Vin
ESt
St/GT
Q1-Q4
StD
TOE
EVENTS ABC
D
EFG
tREC tREC tID tDO
TONE #n TONE
#n + 1
TONE
#n + 1
tDP tDA
tGTP tGTA
tPQ tQStD
tPSrD
tPTD
tPTE
# n # (n + 1)
HIGH IMPEDANCE
DECODED TONE # (n-1)
VTSt
Control Dimensions Altern. Dimensions Symbol in millimetres in inches —. MlN Nominal MAX MlN Nominal MAX HHHHHHHHHH A 1.70 2.00 0.067 0.079 A1 0.05 0.20 0.002 0.008 A2 i.65 1.85 0.065 0.073 D 6.90 7.50 0. 0.295 E 7.40 8.20 0.29i 0.3 3 E‘ E1 5.00 5.60 0.i97 0.2 0 L 0.55 0.95 0.022 0.037 e 0.65 880. 0.026 880. b 0.22 0.38 0.009 0.0i5 c 0.09 0.25 0.004 0.0i0 _i 0 0' 8' 0' 8' A Pin features \\,l N 20 l Conforms to JEDEC MO—i50 AE lss. B This drawing supersedes:— A2 J] l l l iseating PM“ 4i8/E0/5i48i/002 (Swindon/Plymouth) Milli; t N J.L i. A visual index feature, e.g. a dot, must be located within the crassihotched area. 2. Controlling dimension are in millimeters. 3. Dimensions D and Ei do not include mould flash or protusion. Mould flash or protusion shall not exceed 0.20 mm per side. D and E1 ore maximum plastic body size dimensions including mould mismatch. 4. Dimension 0 does not include dambar protusion/intrusion. Allowable dambar protusion shall be O.i3> mm total in excess of b dimension. Dambor intrusion shall not reduce dimension b by more than 0.07 mm. ;l_t ”J_L © Zarlink Semiconductor 2002 All rights reserved Package Code D D ISSUE 1 2 3 Previous package codes Package Outline for 20 lead AC“ 201933 205234 212477 \ ZARLINK NP / N SSOP (5.3mm Body Width) SEMICONDUCTOR DATE 27FebQ7 255e098 3Apr02 APPRD GPDOO294
index Area N/2 [r Base Plane Sealing Plane Notes: Leodirame Material: Copper _ Leadirume finish: Snider Ploie Dimensions 0. D1 & E1 do not include mouid flash or protrusions. . Dimensions e_B & _eC are measured yv'i‘h me leads uneanslrained > . Canlralling armensrons are inches. Millimeler conversions are nol necessarily exact. End iecd at 4 corners DI (Full Leaa) Di (Half Lead) - _4’ FT: ii “ ._ a3 (Hall iead) L -i i._e at: 1. % 3. Dimensions E a eA are measured wiln ieaas eonslrained to be perpendicular m dalurn [:63 5 7 N is me maximum or lerrninol positions, —— a2 (Fuli lead) Miri Max Mm Max mm mm inche inches A 5.33 0.210 A1 0.38 0015 A2 2.92 4.95 0.115 0.195 b 0.36 0.56 0.014 0.022 b2 1.14 1.78 0.045 0.070 b3 n/o n/o n/o n/o c 0.20 0.36 0.008 0.014 D 22.35 23.37 0.880 0.920 01 0.13 0.005 E 7.62 8.26 0.300 0325 E1 6.10I 7.11 0.240|0.2eo e 2.54 BSC 0.100 BSC eA 7.62 BSC 0.300 880 eB 10.92 0.430 eC 0.00 1.52 0.000 0.060 L 2.92 3.81 0,115 0.150 N | 18 18 Conforms i0 Jedec MSnOOiAC Issue D This drawing supersedes:— Piyrrloum/Swiriduri drawing a; 418/ED/39502/OO4 (a) Zariirlk Semicundumur 2002 Aii rights reserved ISSUE 1 2 ACN 202563 212483 DATE 9Jun97 5Apr02 APPRD ‘ ZARUNK SEMICONDUCTOR Package Code D A Previous package codes DP/E Package Outline for 18 Lead PDiP GPDOO348
” e V Controi Dimensions Aitern, Dimensions —. Symbui in rniilimelres in inches P H H H H H H H H MiN Norninui MAX MIN Nominal MAx A 2.35 2.65 0.093 0.104 A1 O.iO 0.30 0.004 0.012 A5 51%: 31%;: 82%; 833% Index ared\ H H 10.00 1065 0.394 0.419 E 7.40 7.60 0,291 0299 L 0.40 1.27 0.016 0.050 '7 e 1. 7 BSC. 0. 50 1350. “e b 83% 8-9; 883% 33%? . 41 c , . , , PinitHjoHjjj_, 2. e 0' a— o- 8. ii. h 025 0. 5 7 0,0 0029 Pin feoiures C N 18 i | Conforms to JEDEC MseOisAB iss. c Fifi : :m :54" Notes: 1, The chomfer on the body is optional. if not present. a visuoi index feature, e.g. a dot, must be iocoted within the crossiholched oreo, 2. Controliing dimensions are in miilimelers 3, Dimension D do not include mouid flash, protusion or gate burrs. These shoii not exceed 0006” per side. 4, Dimension Ei do not inciude interiieod flash or protusion. These sholi not exceed 0010" per side. 5, Dimension b does not include dombar prolusion / intrusion. Ailowoble dombor protusion shdii be 0004" total in excess of b dimension. (9 ZariinkSemiconduflovZOUZNi ngms reseNed Package Code D C ISSUE 1 2 3 Previous package codes Package Outiine for ACN 5745 201940 212432 ‘ ZARLINK MP / S 18 ieod SOIC ‘ SEMICONDUCTOR H . we 7Apr95 27Feb9725Mor02 (0300 Body Width) mm GPDOOOi 4
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