Scheda tecnica PCA9614DP di NXP USA Inc.

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1. General description

The PCA9614 is a Fast-mode Plus (Fm+) SMBus/I2C-bus buffer that extends the normal

single-ended SMBus/I2C-bus through electrically noisy environments using a differential

SMBus/I2C-bus (dI2C) physical layer, which is transparent to the SMBus/I2C-bus protocol

layer. It consists of two single-ended to differential driver channels for the SCL (serial

clock), SDA (serial data).

The use of differential transmission lines between identical dI2C bus buffers removes

electrical noise and common-mode offsets that are present when signal lines must pass

between different voltage domains, are bundled with hostile signals, or run adjacent to

electrical noise sources, such as high energy power supplies and electric motors.

The SMBus/I2C-bus was conceived as a simple slow speed digital link for short runs,

typically on a single PCB or between adjacent PCBs with a common ground connection.

Applications that extend the bus length or run long cables require careful design to

preserve noise margin and reject interference.

The dI2C-bus buffers were designed to solve these problems and are ideally suited for

rugged high noise environments and/or longer cable applications, allow multiple slaves,

and operate at bus speeds up to 1 MHz clock rate. Cables can be extended to at least

three meters (3 m), or longer cable runs at lower clock speeds. The dI2C-bus buffers are

compatible with existing SMBus/I2C-bus devices and can drive Standard, Fast-mode, and

Fast-mode Plus devices on the single-ended side.

Signal direction is automatic and requires no external control. To prevent bus latch-up the

I2C-bus side employs static level offset. Take care when connecting the PCA9614 to other

SMBus/I2C-bus buffers that do not operate with other static level offset bus buffers.

These devices are a bridge between the normal 2-wire single-ended wired-OR

SMBus/I2C-bus and the 4-wire dI2C-bus.

The PCA9614 has two supply voltages, VDD(A) and VDD(B). VDD(A), the card side supply,

only serves as a reference and ranges from 2.3 V to 5.5 V. VDD(B), the line side supply,

serves as the majority supply for circuitry, and ranges from 3.0 V to 5.5 V.

PCA9614

2-channel multipoint Fast-mode Plus differential I2C-bus

buffer

Rev. 1 — 11 April 2014 Product data sheet

Product data sheet Rev. 1 — 11 April 2014 2 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

2. Features and benefits

New dI2C-bus buffers offer improved resistance to system noise and ground offset up

to 1⁄2 of supply voltage

2 channel dI2C (differential I2C) to Fm+ single-ended buffer operating up to 1 MHz with

30 mA SDA/SCL drive capability

Compatible with I2C-bus Standard/Fast-mode and SMBus, Fast-mode Plus up to

1MHz

Active HIGH (internal pull-up resistor) Enable disables devices to high-impedance

state

Single-ended I2C-bus on card side up to 540 pF

Differential I2C-bus on cable side supporting multi-drop bus

Maximum cable length: 3 m (approximately 10 feet) (longer at lower frequency)

dI2C output: 1.5 V differential output with nominal terminals

Differential line impedance (user defined): 100 nominal suggested

Receive input sensitivity: 200 mV

Hysteresis: 30 mV typical

Input impedance: high-impedance (1 M typical)

Receive input voltage range: 0.5 V to +5.5 V

Lock-up free operation

Supports arbitration and clock stretching across the dI2C-bus buffers

Powered-off and powering-up high-impedance I2C-bus pins

Operating supply voltage (VDD(A)) range of 2.3 V to 5.5 V with single-ended side 5.5 V

tolerant

Differential I2C-bus operating supply voltage (VDD(B)) range of 3.0 V to 5.5 V with

5.5 V tolerant. Best operation is at 5 V.

ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Package offering: TSSOP10

Fig 1. SMBus/I2C-bus translation to dI2C-bus and back to SMBus/I2C-bus

VDD(A)1

SCL

SDA

PCA9614

aaa-011060

dI2C-bus

(differential I2C-bus,

1 of 2 lines shown)

twisted-pair cable

single-ended

I2C-bus

PCA9614

SCL

SDA

GND1 GND2

VDD(A)2

single-ended

I2C-bus VDD(B)

VDD(B)

Product data sheet Rev. 1 — 11 April 2014 3 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

3. Applications

Monitor remote temperature/leak detectors in harsh environment

Control of power supplies in high noise environment

Transmission of I2C-bus between equipment cabinets

Commercial lighting and industrial heating/cooling control

Any application that requires long I2C-bus runs in electrically noisy environments

Any application with multiple power suppliers and the potential for ground offsets up to

2.5 V

4. Ordering information

4.1 Ordering options

Table 1. Ordering information

Type number Topside

marking Package

Name Description Version

PCA9614DP P9614 TSSOP10 plastic thin shrink small outline package; 10 leads;

body width 3 mm SOT552-1

Table 2. Ordering options

Type number Orderable

part number Package Packing method Minimum

order quantity Temperature range

PCA9614DP PCA9614DP,118 TSSOP10 Reel 13” Q1/T1

*standard mark SMD 2500 Tamb =40 C to +85 C

Product data sheet Rev. 1 — 11 April 2014 4 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

5. Functional diagram

Fig 2. Functional diagram of PCA9614

Fig 3. Differential output driver simplified circuit

DSDAP

DSDAM

SDA

DSCLP

DSCLM

SCL

VSS

PCA9614

VDD(A) VDD(B)

002aah586

VDD(A)

DSCLP, DSDAP

aaa-011989

DSCLM, DSDAM

jjjjj EEEEE

Product data sheet Rev. 1 — 11 April 2014 5 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 4. Pin configuration for TSSOP10

PCA9614DP

DD(A)

DD(B)

SDA DSDAM

EN DSDAP

SCL DSCLP

DSCLM

002aag406

Table 3. Pin description

Symbol Pin Description

VDD(A) 1I

2C-bus side power supply (2.3 V to 5.5 V)

SDA 2 card side open-drain serial data input/output

EN 3 enable input (active HIGH); internal pull-up resistor to VDD(A)

SCL 4 card side open-drain serial clock input/output

VSS 5 ground supply voltage (0 V)

DSCLM 6 line side differential open-drain clock minus input/output

DSCLP 7 line side differential open-drain clock plus input/output

DSDAP 8 line side differential open-drain data plus input/output

DSDAM 9 line side differential open-drain data minus input/output

VDD(B) 10 differential side power supply (3.0 V to 5.5 V)

FigureZ Figure 5

Product data sheet Rev. 1 — 11 April 2014 6 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

7. Functional description

Refer to Figure 2.

The PCA9614 is used at each node of the dI2C-bus signal path, to provide conversion

from the dI2C-bus signal format to conventional I2C-bus/SMBus, allowing the connection

of existing I2C-bus/SMBus devices as slaves or the bus master. Because the signal

voltages on the I2C-bus/SMBus bus side may be different from the dI2C-bus side, there

are two power supply pins and a common ground. Static offset is employed by the

I2C-bus/SMBus side to prevent bus latch up. Signal direction is determined by the

I2C-bus/SMBus bus protocol, and does not require a direction signal, as these bus buffers

automatically set signal flow direction. An enable pin (EN) is provided to disable the bus

buffer, and is useful for fault finding, power-up sequencing, or reconfiguration of a large

bus system by isolating sections not needed at all times.

Construction of the differential transmission line is not device-dependent. PCB traces,

open wiring, twisted-pair cables or a combination of these may be used. Twisted-pair

cables offer the best performance. A typical twisted-pair transmission line cable has a

characteristic impedance of ‘about 100 ’ and must be terminated at both ends in 100 

to prevent unwanted signal reflections. Multiple nodes (each using a dI2C-bus buffer) may

be connected at any point along this transmission line, however, the stub length degrades

the bus performance, and should therefore be minimized.

7.1 I2C-bus/SMBus side

The I2C-bus/SMBus side of the PCA9614 differential bus buffer is connected to other

I2C-bus/SMBus devices and requires pull-up resistors on each of the SCL and SDA

signals. The value of the resistor should be chosen based on the bus capacitance and

desired data speed, being careful not to overload the driver current rating of 3 mA for

Standard and Fast modes, 30 mA for Fast-mode Plus (Fm+). The I2C-bus/SMBus side of

the PCA9614 is powered from the VDD(A) supply pin.

7.2 dI2C-bus side differential pair

In previous I2C-bus/SMBus designs, the nodes (Master and one or more Slaves) are

connected by wired-OR in combination with a single pull-up resistor. This simple

arrangement is not suited for long distances more than one meter (1 m) or about

three feet (3 ft), due to ringing and reflections on the unterminated bus. The use of a

transmission line with correct termination eliminates this problem, and is further improved

by differential signaling used in the dI2C-bus scheme. Each node acts as both a driver and

a receiver to allow bidirectional signal flow, but not at the same time. Switching from

transmit to receive is done automatically.

The dI2C-bus side of the PCA9614 is powered from the VDD(B) supply pin. The dI2C-bus is

also biased to an idle state (D+ more positive than D) to be compatible with the

I2C-bus/SMBus wired-OR scheme, when not transmitting traffic (data). This allows every

node to receive broadcast messages from the Master, and return ACK/NACK and data in

response. Biasing is done with additional resistors, connected to VDD(B) and VSS (the local

ground), as shown in Figure 5. The transmission line is terminated in the characteristic

impedance of the cable, typically 100 . This is the value defined by three resistors, the

other two resistors providing the idle condition bias to the twisted pair.

Product data sheet Rev. 1 — 11 April 2014 7 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

7.2.1 Noise rejection

Impulse noise coupled into the I2C-bus/SMBus signals can prevent the I2C-bus/SMBus

bus from operating reliably. The hostile signals may appear on the SCL line, SDA line, or

both. Impulse noise may also enter the common ground connection, or be caused by

current in the ground path caused by DC power supplies, or other signals sharing the

common ground return path. This problem is removed by using a differential transmission

line, in place of the I2C-bus/SMBus signal path. The dI2C-bus receiver (at each dI2C-bus

node) subtracts the signals on the two differential lines (D+ and D), and eliminates any

common-mode noise that is coupled into the dI2C-bus. The receiver amplifies the signals

which are also attenuated by the bulk resistance of the transmission line cable

connection, and does not rely on a common ground connection at each node.

7.2.2 Rejection of ground offset voltage

Hostile signals interfere with the I2C-bus/SMBus bus through the common ground

connection between each node. Current in this ground path causes an offset that may

cause false data or push the I2C-bus/SMBus signals outside of an acceptable range.

Unwanted ground offset can be caused by heavy DC current in the ground path, or

injection of ground current from AC signals, either of which may show up as false signals.

Because the dI2C-bus node’s receiver responds only to the difference between the two

dI2C-bus transmission lines, common-mode signals are ignored. There is no need to have

a ground connection between each of the nodes, which may be powered locally. Nodes

may also be powered by extra conductors (for VDD and ground) run with the dI2C-bus

signals. Voltage offsets caused by DC current in these additional wires are ignored by the

dI2C-bus receiver, which subtracts the two differential signals (D+ and D).

7.3 EN pin

The EN pin places the PCA9614 in an idle state, effectively stopping transmission of

I2C-bus/SMBus traffic (data) over the dI2C-bus. An internal pull-up holds the device

enabled. The enable pin is used to isolate a badly behaved slave on power-up until after

the system power-up reset. It should never change state during an I2C-bus/SMBus

operation because disabling during a bus operation hangs the bus and enabling part way

through a bus cycle could confuse the I2C-bus/SMBus parts being enabled. The EN pin

should only change state when the global bus and the buffer port are in an idle state to

prevent system failures. The EN pin turns on or off both channels.

Fig 5. dI2C-bus terminations

DxxxP

DxxxM

aaa-011061

twisted-pair cable

DxxxP

DxxxM

Figure 6 Figure 8 (Figure 6

Product data sheet Rev. 1 — 11 April 2014 8 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

8. Application design-in information

8.1 I2C-bus

As with the standard I2C-bus system, pull-up resistors are required to provide the logic

HIGH levels on the single-ended buffered bus (standard open-drain configuration of the

I2C-bus). The size of these pull-up resistors depends on the system. The device is

designed to work with Standard-mode, Fast-mode and Fast-mode Plus I2C-bus devices in

addition to SMBus devices. Standard-mode and Fast-mode I2C-bus and SMBus devices

only specify 3 mA output drive; this limits the termination current to 3 mA in a generic

I2C-bus system where Standard-mode devices and multiple masters are possible. When

only Fast-mode Plus devices are used, then higher termination currents can be used due

to their 30 mA sink capability.

8.2 Differential I2C-bus application

See Figure 6 through Figure 8.

The simple application (Figure 6) shows an existing SMBus/I2C-bus being extended over

a section of dI2C-bus transmission line, containing a dedicated twisted pair for SCL and

SDA. At one end of the transmission line a resistor network (R1-R2-R1) terminates the

twisted-pair cable and biases D+ positive with respect to D. An identical resistor network

at the other end of the transmission line terminates the twisted-pair cable. DC power for

each end of the transmission line and the VDD(B) of each PCA9614 bus buffer can be from

separate and isolated power supplies, or use the same supply and ground run in separate

wires along the same path as the dI2C-bus signal twisted pairs.

Telecom category 5 (‘CAT 5’) data cable is well suited for this task, but loose wires may

also be used, with a reduction in performance. Assuming VDD(B) is 5 V, and using CAT 5

cable, R2 is 120 , R1 is 600 . The parallel combination yields a termination of 100  at

each end of the twisted pairs. Either side of the dI2C-bus buffer pair is connected to

standard SMBus/I2C buses, which require their own pull-up resistors to VDD(A) of the

PCA9614 bus buffers. VDD(A) and VDD(B) can be the same supply, however, making them

different voltages enables the PCA9614 bus buffers to level translate between the

SMBus/I2C-bus and dI2C-bus sections of the bus, or to have different supply voltages and

level translate at either end of the dI2C-bus and SMBus/I2C-bus system.

For example, the left-hand bus master (and local slave) may operate on a 3.3 V supply

and SMBus/I2C-bus while the dI2C-bus transmission lines are at 5 V, and the right-hand

slave is operated from a different 3.3 V supply and SMBus/I2C-bus, or even a different bus

voltage other than 3.3 V.

Depending upon the timing from the system master, clock toggle rates can vary from

10 kHz for the SMBus (or less for SMBus/I2C-bus protocol) up to 100 kHz (Standard

mode), 400 kHz (Fast mode), or up to 1 MHz (Fast-mode Plus).

The bus path is bidirectional. Assume that the left side SMBus/I2C-bus becomes active. A

START condition (SDA goes LOW while SDA is HIGH) is sent. This upsets the idle

condition on the dI2C-bus section of the bus, because D+ was more positive than D and

now they are reversed. The right side bus buffer sees the differential lines change polarity

and in turn pulls SDA LOW on the SMBus/I2C-bus side of the bus buffer, transmitting the

START condition to the slave on that section of the SMBus/I2C-bus.

Product data sheet Rev. 1 — 11 April 2014 9 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

If the data clocked out by the left side master contains a valid address of the right side

slave, that slave responds by pulling SDA LOW on the ninth clock. This condition is

transmitted across the dI2C-bus section that has now changed flow direction, and

received by the left side bus buffer (again, D+ was more positive than D and now they

are reversed).

This sequence continues until the master sends the STOP condition (SCL HIGH while

SDA goes HIGH), placing the active slave (on the right side) back to idle. When idle, the

normal SMBus/I2C-bus (both left and right sections) are pulled up by their respective

pull-ups. In turn, the dI2C-bus section of the bus rests with D+ more positive than D.

The idle condition can be changed by any node on either SMBus/I2C-bus section or an

additional dI2C-bus node, if present, on the dI2C-bus section of the system. This allows

the existing SMBus/I2C-bus protocol to operate transparently over a mix of SMBus/I2C

and dI2C bus segments.

Due to the SMBus/I2C-bus handshake protocol (ACK/NACK on the ninth clock pulse), the

direction of the SMBus/I2C-bus is reversed often. The ‘time of flight’ for the signals to pass

through each bus buffer and for the target slave to respond defines the maximum speed of

the bus, regardless of how fast the clock toggles. The dI2C-bus section of the bus requires

two additional PCA9614 bus buffers, further delaying the SMBus/I2C-bus traffic. If the

dI2C-bus transmission line section is made longer, the bus operates much slower,

regardless of the clock toggle speed.

It is not necessary to have a ground connection between each end of the dI2C section of

the bus. The dI2C-bus receiver responds to reversal of the polarity of the D+ and D

signals, and ignores the common-mode voltage that may be present.

Ideally, the common-mode voltage is the same at each end of the twisted pairs, and no

current flows along the twisted pair when the bus is idle, because the D+ and D dI2C-bus

drivers are both high-impedance, the bus is biased by R1-R2-R1 at each end. If the

common-mode voltage is not 0 V, current flows along the twisted pair, returning through

the common ground or common power supply connection if present.

If both ends of the twisted pair are powered by the same VDD(B) supply and one end is

remote, there is a common-mode offset between them. This is ignored by the dI2C-bus

receivers, which only respond to the difference between D+ and D.

However, a large common-mode offset voltage forces the D+ and D signals out of the

range of the receiver, and data are lost. The PCA9614 bus buffers use standard ESD

protection networks to protect the external pins, and therefore should not be biased above

or below the VDD(B) and VSS pins respectively. This limits the common-mode range to

approximately 0.5 VDD(B).

DC resistance of the transmission line attenuates the signals, more so over longer

distances. The loss of signal amplitude is made up by the gain of the dI2C-bus receiver.

There is a limit to how long the dI2C-bus section can be made, as it is necessary for the

driver to overcome the bias on the transmission line, in order to signal a polarity change

(D+ and D reversal) at the receiver end.

4: SEE :H:H:b<>

Product data sheet Rev. 1 — 11 April 2014 10 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

Fig 6. Typical application for PCA9614

VDD(B)1

PCA9614

SCL

SDA

SLAVE

MASTER

DSCLP

DSCLM

DSDAP

DSDAM

VSS1

002aag408

CARD

PCA9614

SCL

SDA

MASTER

SLAVE

CARD

VDD(A)1 VDD(A)2

VDD(B)2

VSS2

optional

MASTER MASTER MASTER

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Product data sheet Rev. 1 — 11 April 2014 11 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

Remark: Keep drops as short as possible.

Remark: There is only one ground pin on the PCA9614, so the single-ended I2C-bus signals that are not ground offset tolerant must be referenced to the ground pin on

the part. And any ground offset must be on the differential side where the differential input and output can tolerate a ground offset of up to 0.5 VDD(B).

Fig 7. PCA9614 application diagram; VDD and VSS are routed through the cable

DD(B)

PCA9614

SCL

SDA

SLAVE

MASTER

DSCLP

DSCLM

DSDAP

DSDAM

002aag409

CARD

PCA9614

SLAVE MASTER

CARD

PCA9614

SLAVE MASTER

CARD

optional

DD(B)

termination

DD(A)

SLAVE MASTER

CARD V

DD(A)

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

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Product data sheet Rev. 1 — 11 April 2014 12 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

Fig 8. PCA9614 application diagram; VDD and VSS are not routed through the cable

DD(B)

PCA9614

SCL

SDA

SLAVE

MASTER

DSCLP

DSCLM

DSDAP

DSDAM

002aag410

CARD

DD(B)

PCA9614

SLAVE MASTER

CARD

DD(A)

PCA9614

SLAVE MASTER

CARD V

DD(A)

PCA9614

SLAVE MASTER

CARD V

DD(A)

PCA9614

SLAVE MASTER

CARD V

DD(A)

PCA9614

SLAVE MASTER

CARD V

DD(A)

PCA9614

SLAVE MASTER

CARD V

DD(A)

PCA9614

SLAVE MASTER

CARD V

DD(A)

Product data sheet Rev. 1 — 11 April 2014 13 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

Fig 9. Differential bus waveform

aaa-011062

Fig 10. Single-ended bus waveform (master side of bus)

002aag415

9th clock pulse

acknowledge

SCL

SDA

VOL of master

VOL of PCA9614 (from slave)

Product data sheet Rev. 1 — 11 April 2014 14 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

9. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD(B) supply voltage port B differential bus; 3.0 V to 5.5 V 0.5 +6 V

VDD(A) supply voltage port A single-ended bus 0.5 +6 V

VO(dif) differential output voltage 0.5 +6 V

Vbus bus voltage voltage on I2C-bus B side, or enable (EN) 0.5 +6 V

II/O input/output current SDA, SCL, Dxxxx - 80 mA

IDD(B) supply current port B - 160 mA

Ptot total power dissipation - 100 mW

Tstg storage temperature 55 +125 C

Tamb ambient temperature operating in free air 40 +85 C

Tjjunction temperature - 125 C

Product data sheet Rev. 1 — 11 April 2014 15 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

10. Static characteristics

Table 5. Static characteristics

VDD(B) = 3.0 V to 5.5 V; VSS =0V; T

amb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD(B) supply voltage port B differential bus 3.0 - 5.5 V

VDD(A) supply voltage port A single-ended bus [1] 2.3 - 5.5 V

IDD(VDDA) supply current on pin VDD(A) --16A

IDDH(B) port B HIGH-level supply

current both channels HIGH; VDD(B) =5.5V;

SDAn = SCLn = VDD(A) =5.5V -0.71.4mA

IDDL(B) port B LOW-level supply

current both channels LOW; VDD(B) =5.5V;

SDA and SCL = VSS;

differential I/Os open

-11.7mA

driving termination; 2 channels - 70 91 mA

Input and output SDA and SCL

VIH HIGH-level input voltage 0.7 

VDD(A)

-5.5 V

VIL LOW-level input voltage 0.5 - +0.4 V

VIK input clamping voltage II=18 mA 1.5 - 0 V

ILI input leakage current VI=V

DD(A) --2A

IIL LOW-level input current SDA, SCL; VI=0.2V - - 12 A

VOL LOW-level output voltage IOL = 200 A or 30 mA 0.47 0.52 0.6 V

VOLVIL difference between LOW-level

output and LOW-level input

voltage

guaranteed by design - - 90 mV

ILOH HIGH-level output leakage

current VO=V

DD(A) --2A

Cio input/output capacitance VI=V

DD(A) or 0 V;

disabled or VDD(A) =0V -710pF

Input and output DSDAP/DSDAM and DSCLP/DSCLM

Vcm common-mode voltage 0 - VDD(B) V

ILI input leakage current VI=V

DD(B) --1A

IIL LOW-level input current VI=0.2V - - 1A

Vth(dif) differential receiver threshold

voltage 0VVcm VDD(B) 200 - +200 mV

VI(hys) hysteresis of input voltage receiver; 0 V Vcm VDD(B) -30- mV

Vo(dif)(p-p) peak-to-peak differential

output voltage single-ended input LOW

no load VDD(B) -- V

RL = 54  at VDD(B) =5V 5.0 1.5 1.0 V

Cio input/output capacitance VI=V

DD(B) or 0 V;

disabled or VDD(B) =0V -710pF

Typ, Figure 13 Figure 13 Figure 11 e: Figure 11 Figure 11 Figure 12 Figure 12 GEM

Product data sheet Rev. 1 — 11 April 2014 16 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

[1] LOW-level supply voltage.

11. Dynamic characteristics

[1] Times are specified with loads of 1.35 k pull-up resistance and 50 pF load capacitance on the A side, and 50  termination network

resistance and 50 pF load capacitance on the B side. Different load resistance and capacitance alters the RC time constant, thereby

changing the propagation delay and transition times.

[2] Pull-up voltages are VDD(A) on the A side and termination network on the B side.

[3] Typical values were measured with VDD(A) = 3.3 V at Tamb =25C, unless otherwise noted.

[4] The tPLH delay data from B side to A side is measured at 0 V differential on the B side to 0.5VDD(A) on the A side.

[5] Typical value measured with VDD(A) =3.3V at T

amb =25C.

[6] The proportional delay data from A side to B side is measured at 0.5VDD(A) on the A side to 0 V on the B side.

[7] The enable pin (EN) should only change state when the global bus and the repeater port are in an idle state.

Input EN

VIH HIGH-level input voltage 0.7VDD(A) -5.5 V

VIL LOW-level input voltage 0.5 - +0.3VDD(A) V

ILI input leakage current VI=V

DD(B) 1-+1 A

IIL(EN) LOW-level input current on

pin EN VI= 0.2 V, EN; VDD(A) =5.5V - 20 54 A

Ciinput capacitance VI=V

DD(A) -610pF

RPU pull-up resistance internal pull-up resistor connected to

VDD(A) rail -300- k

Table 5. Static characteristics …continued

VDD(B) = 3.0 V to 5.5 V; VSS =0V; T

amb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Table 6. Dynamic characteristics

VDD = 2.7 V to 5.5 V; VSS =0V; T

amb =





C to +85



C; unless otherwise specified.[1][2]

Symbol Parameter Conditions Min Typ[3] Max Unit

tPLH LOW to HIGH propagation delay single-ended side to differential side;

Figure 13

[4] 140 120 - ns

tPLH2 LOW to HIGH propagation delay 2 single-ended side to differential side;

Figure 13 --100ns

tPHL HIGH to LOW propagation delay single-ended side to differential side;

Figure 11

[5] --120ns

SRrrising slew rate differential side; Figure 11 --1V/ns

SRffalling slew rate differential side; Figure 11 [5] --1V/ns

tPLH LOW to HIGH propagation delay differential side to single-ended side;

Figure 12

[6] --150ns

tPHL HIGH to LOW propagation delay differential side to single-ended side;

Figure 12

[6] --150ns

SRffalling slew rate single-ended side; Figure 12 --0.1V/ns

ten enable time EN HIGH to enable [7] --200ns

tdis disable time EN LOW to disable [7] --200ns

Product data sheet Rev. 1 — 11 April 2014 17 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

11.1 AC waveforms

VDD(A) =3.0V.

SRf=0.6(Vhigh Vlow) / tTHL

SRr=0.6(Vhigh Vlow) / tTLH

VDD(A) =3.0V.

SRf=0.6´V

DD(A) / tTHL

Fig 11. Propagation delay and transition times;

single-ended side to differential side Fig 12. Propagation delay and transition times;

differential side to single-ended side

Fig 13. Propagation delay

002aag416

DD(A)

0.3 V

PLH

THL

0.5V

DD(A)

0.5V

DD(A)

input

output

20 %

0 V 0 V 80 %

20 %

80 %

PHL

TLH

−2.5 V

0.1 V

differential

voltage

input

output

80 % 80 %

0.5V

DD(A)

0.5V

DD(A)

20 %20 %

0 V 0 V

PHL

PLH

0.3 V

−0.3 V

DD(A)

THL

TLH

002aag417

differential

voltage

0.5 V

input

SDA, SCL

output

DSCLP/DSCLM,

DSDAP/DSDAM

tPLH2

0 V

002aag418

0.3 V

−2.5 V

0.5VDD(A)

tPLH

ﬂ;

Product data sheet Rev. 1 — 11 April 2014 18 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

12. Test information

RL = load resistor; 1.35 k on single-ended side.

RT = termination resistance should be equal to Zo of pulse generators.

Fig 14. Test circuit for differential outputs

RL = load resistor; 1.35 k on single-ended side.

CL = load capacitance includes jig and probe capacitance; 50 pF.

RT = termination resistance should be equal to Zo of pulse generators.

Fig 15. Test circuit for open-drain output

I2C-BUS

LEVEL SHIFTER

60 Ω

002aag419

VDD(B)

DUT

VDD(A)

PULSE

GENERATOR

300 Ω

VDD(A)

300 Ω

VDD(B)

DIFFERENTIAL

PROBE

DIFFERENTIAL

002aag420

VDD(A)

DUT

VDD(B)

we S©M

Product data sheet Rev. 1 — 11 April 2014 19 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

13. Package outline

Fig 16. Package outline SOT552-1 (TSSOP10)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.15 0.23

0.15 3.1

2.9 3.1

2.9 0.5 5.0

4.8 0.67

0.34 6°

0°

0.1 0.10.10.95

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.7

0.4

SOT552-1 99-07-29

03-02-18

0.25

10 6

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm SOT552-1

1.1

pin 1 index

Product data sheet Rev. 1 — 11 April 2014 20 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

14. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

14.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Figure 17 Table 7 8 Figure 17

Product data sheet Rev. 1 — 11 April 2014 21 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

14.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 17) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 7 and 8

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 17.

Table 7. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 8. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

mamum peak hamperature = MSL hymn damage \eve\ mmmum peak |emperature = mwmmum soldenng |emperamre

Product data sheet Rev. 1 — 11 April 2014 22 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

MSL: Moisture Sensitivity Level

Fig 17. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 1 — 11 April 2014 23 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

15. Soldering: PCB footprints

Fig 18. PCB footprint for SOT552-1 (TSSOP10); reflow soldering

sot552-1_fr

SOT552 -1

Footprint information for reflow soldering of TSSOP10 package

solder land

Dimensions in mm

occupied area

11-04-19

13-05-02

Hy HxGy P1

5.0 3.1 0.53.1 Issue date

Product data sheet Rev. 1 — 11 April 2014 24 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

16. Abbreviations

17. Revision history

Table 9. Abbreviations

Acronym Description

CDM Charged-Device Model

dI2C-bus differential Inter-Integrated Circuit bus

ESD ElectroStatic Discharge

HBM Human Body Model

I2C-bus Inter-Integrated Circuit bus

I/O Input/Output

LED Light Emitting Diode

SMBus System Management Bus

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9614 v.1 20140411 Product data sheet - -

Product data sheet Rev. 1 — 11 April 2014 25 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

18. Legal information

18.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

18.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

: hitE:I/www.nxg.com salesaddresses®nx9£0m

Product data sheet Rev. 1 — 11 April 2014 26 of 27

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

18.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP Semiconductors N.V.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PCA9614

2-channel multipoint Fm+ differential I2C-bus buffer

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 11 April 2014

Document identifier: PCA9614

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

20. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Functional description . . . . . . . . . . . . . . . . . . . 6

7.1 I2C-bus/SMBus side . . . . . . . . . . . . . . . . . . . . . 6

7.2 dI2C-bus side differential pair . . . . . . . . . . . . . . 6

7.2.1 Noise rejection . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.2.2 Rejection of ground offset voltage . . . . . . . . . . 7

7.3 EN pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

8 Application design-in information . . . . . . . . . . 8

8.1 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

8.2 Differential I2C-bus application . . . . . . . . . . . . . 8

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14

10 Static characteristics. . . . . . . . . . . . . . . . . . . . 15

11 Dynamic characteristics . . . . . . . . . . . . . . . . . 16

11.1 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . 17

12 Test information. . . . . . . . . . . . . . . . . . . . . . . . 18

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19

14 Soldering of SMD packages . . . . . . . . . . . . . . 20

14.1 Introduction to soldering . . . . . . . . . . . . . . . . . 20

14.2 Wave and reflow soldering . . . . . . . . . . . . . . . 20

14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 20

14.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 21

15 Soldering: PCB footprints. . . . . . . . . . . . . . . . 23

16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24

17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24

18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25

18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25

18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 25

18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26

19 Contact information. . . . . . . . . . . . . . . . . . . . . 26

20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Scheda tecnica PCA9614DP di NXP USA Inc.

INFORMAZIONI

GUIDA

CONTATTI

SEGUICI