Scheda tecnica ADuM130-31D,E di Analog Devices Inc.

u ANALOG DEVICES
3.0 kV RMS/3.75 kV RMS Triple-Channel
Digital Isolators
Data Sheet ADuM130D/ADuM130E/ADuM131D/ADuM131E
Rev. A Document Feedback
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FEATURES
High common-mode transient immunity: 100 kV/μs
High robustness to radiated and conducted noise
Low propagation delay: 13 ns maximum for 5 V operation,
15 ns maximum for 1.8 V operation
150 Mbps maximum guaranteed data rate
Safety and regulatory approvals (pending)
UL recognition
3000 V rms/3750 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 849 V peak
CQC certification per GB4943.1-2011
Backward compatibility
ADuM130E1/ADuM131E1 pin-compatible with
ADuM1300/ADuM1301
Low dynamic power consumption
1.8 V to 5 V level translation
High temperature operation: 125°C
Fail-safe high or low options
16-lead, RoHS compliant, SOIC package
APPLICATIONS
General-purpose multichannel isolation
Serial peripheral interface (SPI)/data converter isolation
Industrial field bus isolation
GENERAL DESCRIPTION
The ADuM130D/ADuM130E/ADuM131D/ADuM131E1 are
triple-channel digital isolators based on Analog Devices, Inc.,
iCoupler® technology. Combining high speed, complementary
metal-oxide semiconductor (CMOS) and monolithic air core
transformer technology, these isolation components provide
outstanding performance characteristics superior to alternatives
such as optocoupler devices and other integrated couplers. The
maximum propagation delay is 13 ns with a pulse width distortion
of less than 3 ns at 5 V operation. Channel matching is tight at
3.0 ns maximum.
The ADuM130D/ADuM130E/ADuM131D/ADuM131E data
channels are independent and are available in a variety of config-
urations with a withstand voltage rating of 3.0 kV rms or
3.75 kV rms (see the Ordering Guide). The devices operate with
the supply voltage on either side ranging from 1.8 V to 5 V, prov-
iding compatibility with lower voltage systems as well as enabling
voltage translation functionality across the isolation barrier.
FUNCTIONAL BLOCK DIAGRAMS
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
GND
1
V
IA
V
IB
V
IC
NIC
DISABLE
1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
NIC
NIC
GND
2
NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.
13348-001
16
15
14
13
12
11
10
1
2
3
4
5
6
7
98
ADuM130D
Figure 1. ADuM130D Functional Block Diagram
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.
16
15
14
13
12
11
10
1
2
3
4
5
6
7
98
ADuM130E
13348-002
GND
1
V
IA
V
IB
V
IC
NIC
NIC
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
NIC
V
E2
GND
2
Figure 2. ADuM130E Functional Block Diagram
ENCODE DECODE
ENCODE DECODE
DECODE ENCODE
V
DD1
GND
1
V
IA
V
IB
V
OC
NIC
DISABLE
1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
IC
NIC
DISABLE
2
GND
2
NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.
13348-101
16
15
14
13
12
11
10
1
2
3
4
5
6
7
98
ADuM131D
Figure 3. ADuM131D Functional Block Diagram
ENCODE DECODE
ENCODE DECODE
DECODE ENCODE
V
DD1
NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.
16
15
14
13
12
11
10
1
2
3
4
5
6
7
98
ADuM131E
GND
1
V
IA
V
IB
V
OC
V
E1
NIC
GND
1
V
DD2
GND
2
V
OA
V
OB
V
IC
NIC
V
E2
GND
2
13348-102
Figure 4. ADuM131E Functional Block Diagram
Unlike other optocoupler alternatives, dc correctness is ensured
in the absence of input logic transitions. Two different fail-safe
options are available, in which the outputs transition to a pre-
determined state when the input power supply is not applied or
the inputs are disabled. The ADuM130E1/ADuM131E1 are pin-
compatible with the ADuM1300/ADuM1301.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
ADuM130D/ADuM130E/ADuM131D/ADuM131E Data Sheet
Rev. A | Page 2 of 22
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3.3 V Operation ............................ 4
Electrical Characteristics—2.5 V Operation ............................ 6
Electrical Characteristics—1.8 V Operation ............................ 7
Insulation and Safety Related Specifications ............................ 9
Package Characteristics ............................................................... 9
Regulatory Information ............................................................. 10
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 11
Recommended Operating Conditions .................................... 12
Absolute Maximum Ratings ......................................................... 13
ESD Caution................................................................................ 13
Truth Tables................................................................................. 14
Pin Configurations and Function Descriptions ......................... 15
Typical Performance Characteristics ........................................... 17
Applications Information .............................................................. 18
Overview ..................................................................................... 18
Printed Circuit Board (PCB) Layout ....................................... 18
Propagation Delay Related Parameters ................................... 19
Jitter Measurement ..................................................................... 19
Insulation Lifetime ..................................................................... 19
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 22
REVISION HISTORY
11/15—Rev. 0 to Rev. A
Added 16-Lead, Narrow Body SOIC Package ................ Universal
Changes to Title, Features Section, and General Description
Section ................................................................................................ 1
Added Table 9; Renumbered Sequentially .................................... 9
Changes to Table 10 and Table 11 .................................................. 9
Added Table 12 ............................................................................... 10
Changes to Table 13 ........................................................................ 10
Changes to Table 15 Title ............................................................... 12
Added Figure 5; Renumbered Sequentially ................................ 12
Changes to Table 17 and Table 19 ................................................ 13
Added Table 18 ............................................................................... 13
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 22
7/15—Revision 0: Initial Version
Table L
Data Sheet ADuM130D/ADuM130E/ADuM131D/ADuM131E
Rev. A | Page 3 of 22
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. M inimum/maximum specifications apply over the entire recommended
operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
PW
6.6
ns
Within pulse width distortion (PWD) limit
Data Rate1 150 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 4.8 7.2 13 ns 50% input to 50% output
Pulse Width Distortion PWD 0.5 3 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 6.1 ns Between any two devices at the same
temperature, voltage, and load
Channel Matching
Codirectional tPSKCD 0.5 3.0 ns
Opposing Direction tPSKOD 0.5 3.0 ns
Jitter 630 ps p-p See the Jitter Measurement section
80
ps rms
See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx2 = −20 µA, VIx = VIxH3
VDDx − 0.4 VDDx −
0.2
V IOx2 = −4 mA, VIx = VIxH3
Logic Low VOL 0.0 0.1 V IOx2 = 20 µA, VIx = VIxL4
0.2 0.4 V IOx2 = 4 mA, VIx = VIxL4
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
VE2 Enable Input Pull-Up Current IPU −10 −3 µA VE2 = 0 V
DISABLE1 Input Pull-Down Current IPD 9 15 µA DISABLE1 = VDDx
Tristate Output Current per Channel IOZ −10 +0.01 +10 µA 0 V ≤ VOx ≤ VDDx
Quiescent Supply Current
ADuM130D/ADuM130E
IDD1 (Q) 1.35 2.6 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD2 (Q) 1.73 2.9 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD1 (Q) 9.7 15.2 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
I
DD2 (Q)
1.87
3.0
mA
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
ADuM131D/ADuM131E
IDD1 (Q) 1.62 2.7 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD2 (Q) 1.61 2.8 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD1 (Q) 7.4 11.4 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD2 (Q) 5.34 7.2 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
Dynamic Supply Current
Dynamic Input IDDI (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.02 mA/Mbps Inputs switching, 50% duty cycle
Undervoltage Lockout UVLO
Positive VDDx Threshold VDDxUV+ 1.6 V
Negative VDDx Threshold VDDxUV− 1.5 V
VDDx Hysteresis VDDxUVH 0.1 V
Table 3‘
ADuM130D/ADuM130E/ADuM131D/ADuM131E Data Sheet
Rev. A | Page 4 of 22
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient
Immunity7
|CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, or C.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 E0 refers to the ADuM130E0/ADuM131E0 models, D0 refers to the ADuM130D0/ADuM131D0 models, E1 refers to the ADuM130E1/ADuM131E1 models, and D1 refers
to the ADuM130D1/ADuM131D1 models. See the Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VOx > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 2. Total Supply Current vs. Data Throughput
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM130D/ADuM130E
Supply Current Side 1 IDD1 5.6 9.0 6.3 9.8 9.4 14.3 mA
Supply Current Side 2 IDD2 1.9 3.7 3.1 4.9 6.8 10 mA
ADuM131D/ADuM131E
Supply Current Side 1 IDD1 4.6 7.2 5.5 8.3 8.8 11.9 mA
Supply Current Side 2 IDD2 3.6 5.8 4.6 6.8 8.0 11.3 mA
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended
operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate1 150 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 4.8 6.8 14 ns 50% input to 50% output
Pulse Width Distortion PWD 0.7 3 ns |tPLH − tPHL|
Change vs. Temperature
1.5
ps/°C
Propagation Delay Skew tPSK 7.5 ns Between any two devices at the
same temperature, voltage, and
load
Channel Matching
Codirectional tPSKCD 0.7 3.0 ns
Opposing Direction
t
PSKOD
0.7
3.0
ns
Jitter 640 ps p-p See the Jitter Measurement section
75 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Data Sheet ADuM130D/ADuM130E/ADuM131D/ADuM131E
Rev. A | Page 5 of 22
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx2 = −20 µA, VIx = VIxH3
VDDx − 0.4 VDDx − 0.2 V IOx2 = −2 mA, VIx = VIxH3
Logic Low VOL 0.0 0.1 V IOx2 = 20 µA, VIx = VIxL4
0.2
0.4
V
I
Ox2
= 2 mA, V
Ix
= V
IxL4
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
VE2 Enable Input Pull-Up Current IPU −10 −3 µA VE2 = 0 V
DISABLE1 Input Pull-Down Current IPD 9 15 µA DISABLE1 = VDDx
Tristate Output Current per Channel IOZ −10 +0.01 +10 µA 0 V ≤ VOx ≤ VDDx
Quiescent Supply Current
ADuM130D/ADuM130E
IDD1 (Q) 1.25 2.5 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
I
DD2 (Q)
1.65
2.8
mA
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
IDD1 (Q) 9.57 15.0 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD2 (Q) 1.79 2.9 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
ADuM131D/ADuM131E
IDD1 (Q) 1.52 2.6 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
I
DD2 (Q)
1.52
2.6
mA
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
IDD1 (Q) 7.28 11.3 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD2 (Q) 5.24 7.1 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
Dynamic Supply Current
Dynamic Input IDDI (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Undervoltage Lockout UVLO
Positive VDDx Threshold VDDxUV+ 1.6 V
Negative VDDx Threshold VDDxUV− 1.5 V
VDDx Hysteresis VDDxUVH 0.1 V
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity7 |CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, or C.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 E0 refers to the ADuM130E0/ADuM131E0 models, D0 refers to the ADuM130D0/ADuM131D0 models, E1 refers to the ADuM130E1/ADuM131E1 models, and D1 refers
to the ADuM130D1/ADuM131D1 models. See the Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VOx > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 4. Total Supply Current vs. Data Throughput
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM130D/ADuM130E
Supply Current Side 1 IDD1 5.4 8.8 6.0 9.4 8.5 12.7 mA
Supply Current Side 2 IDD2 1.8 3.6 2.9 4.7 6.2 8.4 mA
ADuM131D/ADuM131E
Supply Current Side 1 IDD1 4.4 7.1 5.2 8.0 8.1 10.7 mA
Supply Current Side 2 IDD2 3.4 5.6 4.3 6.5 7.4 9.5 mA
Table 5‘
ADuM130D/ADuM130E/ADuM131D/ADuM131E Data Sheet
Rev. A | Page 6 of 22
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire recommended
operation range: 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate1 150 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 5.0 7.0 14 ns 50% input to 50% output
Pulse Width Distortion PWD 0.7 3 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 6.8 ns Between any two devices at the
same temperature, voltage, load
Channel Matching
Codirectional
t
PSKCD
0.7
3.0
ns
Opposing Direction tPSKOD 0.7 3.0 ns
Jitter 770 ps p-p See the Jitter Measurement section
160 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx2 = −20 µA, VIx = VIxH3
VDDx − 0.4 VDDx − 0.2 V IOx2 = −2 mA, VIx = VIxH3
Logic Low VOL 0.0 0.1 V IOx2 = 20 µA, VIx = VIxL4
0.2 0.4 V IOx2 = 2 mA, VIx = VIxL4
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
V
E2
Enable Input Pull-Up Current
I
PU
−10
−3
µA
V
E2
= 0 V
DISABLE1 Input Pull-Down Current IPD 9 15 µA DISABLE1 = VDDx
Tristate Output Current per Channel IOZ −10 +0.01 +10 µA 0 V ≤ VOx ≤ VDDx
Quiescent Supply Current
ADuM130D/ADuM130E
IDD1 (Q) 1.2 2.4 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD2 (Q) 1.61 2.7 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD1 (Q) 9.52 14.9 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD2 (Q) 1.76 2.8 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
ADuM131D/ADuM131E
IDD1 (Q) 1.47 2.5 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD2 (Q) 1.48 2.5 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD1 (Q) 7.23 11.2 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD2 (Q) 5.19 7.0 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
Dynamic Supply Current
Dynamic Input IDDI (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Undervoltage Lockout
Positive VDDx Threshold VDDxUV+ 1.6 V
Negative VDDx Threshold VDDxUV− 1.5 V
VDDx Hysteresis VDDxUVH 0.1 V
Data Sheet ADuM130D/ADuM130E/ADuM131D/ADuM131E
Rev. A | Page 7 of 22
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity7 |CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, or C.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 E0 refers to the ADuM130E0/ADuM131E0 models, D0 refers to the ADuM130D0/ADuM131D0 models, E1 refers to the ADuM130E1/ADuM131E1 models, and D1 refers
to the ADuM130D1/ADuM131D1 models. See the Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VOx > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 6. Total Supply Current vs. Data Throughput
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM130E/ADuM130D
Supply Current Side 1 IDD1 5.3 8.7 5.9 9.3 8.2 12.3 mA
Supply Current Side 2 IDD2 1.8 3.6 2.6 4.4 5.2 7.4 mA
ADuM131E/ADuM131D
Supply Current Side 1 IDD1 4.4 7.1 5.0 7.8 7.5 10.1 mA
Supply Current Side 2 IDD2 3.4 5.6 4.1 6.3 6.6 8.7 mA
ELECTRICAL CHARACTERISTICS—1.8 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 1.8 V. Minimum/maximum specifications apply over the entire recommended
operation range: 1.7 V ≤ VDD1 ≤ 1.9 V, 1.7 V ≤ VDD2 ≤ 1.9 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 7.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate
1
150
Mbps
Within PWD limit
Propagation Delay tPHL, tPLH 5.8 8.7 15 ns 50% input to 50% output
Pulse Width Distortion PWD 0.7 3 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 7.0 ns Between any two devices at the
same temperature, voltage, and
load
Channel Matching
Codirectional tPSKCD 0.7 3.0 ns
Opposing Direction tPSKOD 0.7 3.0 ns
Jitter 600 ps p-p See the Jitter Measurement section
90 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold
Logic High
V
IH
0.7 × V
DDx
V
Logic Low VIL 0.3 × VDDx V
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx2 = −20 µA, VIx = VIxH3
VDDx − 0.4 VDDx − 0.2 V IOx2 = −2 mA, VIx = VIxH3
ADuM130D/ADuM130E/ADuM131D/ADuM131E Data Sheet
Rev. A | Page 8 of 22
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Logic Low VOL 0.0 0.1 V IOx2 = 20 µA, VIx = VIxL4
0.2 0.4 V IOx2 = 2 mA, VIx = VIxL4
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
VE2 Enable Input Pull-Up Current IPU −10 −3 µA VE2 = 0 V
DISABLE
1
Input Pull-Down Current
I
PD
9
15
µA
DISABLE
1
= V
DDx
Tristate Output Current per Channel IOZ −10 +0.01 +10 µA 0 V ≤ VOx ≤ VDDx
Quiescent Supply Current
ADuM130D/ADuM130E
IDD1 (Q) 1.15 2.3 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD2 (Q) 1.58 2.6 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD1 (Q) 9.41 14.8 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD2 (Q) 1.72 2.7 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
ADuM131D/ADuM131E
IDD1 (Q) 1.42 2.4 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD2 (Q) 1.44 2.4 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD1 (Q) 7.15 11.1 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD2 (Q) 5.13 6.9 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
Dynamic Supply Current
Dynamic Input IDDI (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Undervoltage Lockout UVLO
Positive V
DDx
Threshold
V
DDxUV+
1.6
V
Negative VDDx Threshold VDDxUV− 1.5 V
VDDx Hysteresis VDDxUVH 0.1 V
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity7 |CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, or C.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 E0 refers to the ADuM130E0/ADuM131E0 models, D0 refers to the ADuM130D0/ADuM131D0 models, E1 refers to the ADuM130E1/ADuM131E1 models, and D1 refers
to the ADuM130D1/ADuM131D1 models. See the Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VOx > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 8. Total Supply Current vs. Data Throughput
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM130D/ADuM130E
Supply Current Side 1
I
DD1
5.2
8.6
5.8
9.3
8.1
12.2
mA
Supply Current Side 2 IDD2 1.7 3.5 2.5 4.3 5.2 7.3 mA
ADuM131D/ADuM131E
Supply Current Side 1 IDD1 4.3 7.0 4.9 7.7 7.26 10.0 mA
Supply Current Side 2 IDD2 3.3 5.5 4.0 6.2 6.5 8.6 mA
Table 9‘ R716 Narrow Body [501cm] Package
Data Sheet ADuM130D/ADuM130E/ADuM131D/ADuM131E
Rev. A | Page 9 of 22
INSULATION AND SAFETY RELATED SPECIFICATIONS
For additional information, see www.analog.com/icouplersafety.
Table 9. R-16 Narrow Body [SOIC_N] Package
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 3000 V rms 1-minute duration
Minimum External Air Gap (Clearance) L (I01) 4.0 mm min Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L (I02) 4.0 mm min Measured from input terminals to output terminals,
shortest distance path along body
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB) 4.5 mm min Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum Internal Gap (Internal Clearance) 25.5 μm min Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Material Group
II
Material Group (DIN VDE 0110, 1/89, Table 1)
Table 10. RW-16 Wide Body [SOIC_W] Package
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 3750 V rms 1-minute duration
Minimum External Air Gap (Clearance) L (I01) 7.8 mm min Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage)
L (I02)
7.8
mm min
Measured from input terminals to output terminals,
shortest distance path along body
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB) 8.1 mm min Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum Internal Gap (Internal Clearance)
25.5
μm min
Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Material Group II Material Group (DIN VDE 0110, 1/89, Table 1)
PACKAGE CHARACTERISTICS
Table 11.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)1 RI-O 1013 Ω
Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz
Input Capacitance2 CI 4.0 pF
IC Junction to Ambient Thermal Resistance
R-16 Narrow Body [SOIC_N] Package θJA 76 °C/W Thermocouple located at center of package underside
RW-16 Wide Body [SOIC_W] Package θJA 45 °C/W Thermocouple located at center of package underside
1 The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
Table 12. R716 Narrow Body [501cm Package
ADuM130D/ADuM130E/ADuM131D/ADuM131E Data Sheet
Rev. A | Page 10 of 22
REGULATORY INFORMATION
See Table 19 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-
isolation waveforms and insulation levels.
Table 12. R-16 Narrow Body [SOIC_N] Package
UL (Pending) CSA (Pending) VDE (Pending) CQC (Pending)
Recognized Under UL 1577
Component Recognition
Program1
Approved under CSA Component
Acceptance Notice 5A
Certified according to DIN V VDE V
0884-10 (VDE V 0884-10):2006-122
Certified under
CQC11-471543-2012
Single Protection, 3000 V rms
Isolation Voltage
CSA 60950-1-07+A1+A2 and IEC
60950-1, second edition, +A1+A2:
Reinforced insulation, VIORM =
565 V peak, VIOSM = 6000 V peak
GB4943.1-2011:
Double Protection, 3000 V rms
Isolation Voltage
Basic insulation at 400 V rms
(565 V peak)
Basic insulation, VIORM = 565 V peak,
VIOSM = 10 kV peak
Basic insulation at
770 V rms (1089 V peak)
Reinforced insulation at 200 V rms
(283 V peak)
Reinforced insulation at
385 V rms (545 V peak)
IEC 60601-1 Edition 3.1: Basic
insulation (one means of patient
protection (1 MOPP)), 250 V rms
(354 V peak)
Tropical climate, altitude
≤5000 m
CSA 61010-1-12 and IEC 61010-1
third edition:
Basic insulation at 300 V rms mains,
400 V rms secondary (565 V peak)
Reinforced insulation at 300 V rms
mains, 200 V secondary (282 V peak)
File E214100 File 205078 File 2471900-4880-0001 File (pending)
1 In accordance with UL 1577, each ADuM130D/ADuM130E/ADuM131D/ADuM131E in the R-16 narrow body [SOIC_N] package is proof tested by applying an insulation
test voltage ≥ 3600 V rms for 1 sec.
2 In accordance with DIN V VDE V 0884-10, each ADuM130D/ADuM130E/ADuM131D/ADuM131E in the R-16 narrow body [SOIC_N] package is proof tested by applying an
insulation test voltage ≥ 1059 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
Table 13. RW-16 Wide Body [SOIC_W] Package
UL (Pending) CSA (Pending) VDE (Pending) CQC (Pending)
Recognized Under UL 1577
Component Recognition
Program1
Approved under CSA Component
Acceptance Notice 5A
Certified according to DIN V VDE V
0884-10 (VDE V 0884-10):2006-122
Certified under
CQC11-471543-2012
Single Protection, 3750 V rms
Isolation Voltage
CSA 60950-1-07+A1+A2 and IEC 60950-1,
second edition, +A1+A2:
Reinforced insulation, VIORM =
849 V peak, VIOSM = 6000 V peak
GB4943.1-2011
Double Protection, 3750 V rms
Isolation Voltage
Basic insulation at 780 V rms
(1103 V peak)
Basic insulation, VIORM = 849 V peak,
VIOSM = 10 kV peak
Basic insulation at
780 V rms (1103 V peak)
Reinforced insulation at 390 V rms
(552 V peak)
Reinforced insulation at
390 V rms (552 V peak)
IEC 60601-1 Edition 3.1: basic insulation
(1 means of patient protection (MOPP)),
490 V rms (693 V peak)
Tropical climate,
altitude ≤5000 m
CSA 61010-1-12 and IEC 61010-1 third
edition:
Basic insulation at 300 V rms mains, 780 V
secondary (1103 V peak)
Reinforced insulation at 300 V rms mains,
390 V secondary (552 V peak)
File E214100 File 205078 File 2471900-4880-0001 File (pending)
1 In accordance with UL 1577, each ADuM130D/ADuM130E/ADuM131D/ADuM131E in the RW-16 wide body [SOIC_W] package is proof tested by applying an insulation
test voltage ≥ 4500 V rms for 1 sec.
2 In accordance with DIN V VDE V 0884-10, each ADuM130D/ADuM130E/ADuM131D/ADuM131E in the RW-16 wide body [SOIC_W] package is proof tested by applying an
insulation test voltage ≥ 1592 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
Table 14. R716 Narrow Body [501cm Package
Data Sheet ADuM130D/ADuM130E/ADuM131D/ADuM131E
Rev. A | Page 11 of 22
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance
of the safety data. The * marking on packages denotes DIN V VDE V 0884-10 approval.
Table 14. R-16 Narrow Body [SOIC_N] Package
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 600 V rms I to III
Climatic Classification 40/125/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 565 V peak
Input to Output Test Voltage, Method B1 VIORM × 1.875 = Vpd (m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Vpd (m) 1059 V peak
Input to Output Test Voltage, Method A Vpd (m)
After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
848 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
678 V peak
Highest Allowable Overvoltage VIOTM 4200 V peak
Surge Isolation Voltage Basic
V peak = 10 kV, 1.2 µs rise time, 50 µs,
50% fall time
V
IOSM
10000
V peak
Surge Isolation Voltage Reinforced V peak = 10 kV, 1.2 µs rise time, 50 µs,
50% fall time
VIOSM 6000 V peak
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 5)
Maximum Junction Temperature TS 150 °C
Total Power Dissipation at 25°C PS 1.64 W
Insulation Resistance at TS VIO = 500 V RS >109 Ω
3,0 S: ESE oz 5: flaw gaming ":8 a, mozgmgomfim
ADuM130D/ADuM130E/ADuM131D/ADuM131E Data Sheet
Rev. A | Page 12 of 22
Table 15. RW-16 Wide Body [SOIC_W] Package
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 600 V rms I to III
Climatic Classification 40/125/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 849 V peak
Input to Output Test Voltage, Method B1 VIORM × 1.875 = Vpd (m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Vpd (m) 1592 V peak
Input to Output Test Voltage, Method A Vpd (m)
After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
1274 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
1019 V peak
Highest Allowable Overvoltage VIOTM 5300 V peak
Surge Isolation Voltage
Basic VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 12,000 V peak
Reinforced VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 6000 V peak
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 6)
Maximum Junction Temperature
T
S
150
°C
Total Power Dissipation at 25°C PS 2.78 W
Insulation Resistance at TS VIO = 500 V RS >109 Ω
1.8
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
050 100 150 200
SAFE OPERATING P
VDD1
, P
VDDA
OR P
VDDB
POWER (W)
AMBIENT TEMPERATURE (°C)
13348-202
Figure 5. Thermal Derating Curve for R-16 Narrow Body [SOIC_N] Package,
Dependence of Safety Limiting Values with Ambient Temperature per
DIN V VDE V 0884-10
3.0
2.5
2.0
1.5
0.5
1.0
0020015010050
SAFE LIMITING POWER (W)
AMBIENT TEMPERATURE (°C)
13348-003
Figure 6. Thermal Derating Curve, Dependence of Safety Limiting Values
with Ambient Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 16.
Parameter Symbol Rating
Operating Temperature TA −40°C to +125°C
Supply Voltages VDD1, VDD2 1.7 V to 5.5 V
Input Signal Rise and Fall Times 1.0 ms
ESD CAUTION A M ESD (elemosmic dismarge) sansirive devicer Chavged dewces and mum boavds can discharge mmur detection Although mo product mum paremea m pm elavy pvmecnon mvcumy, damage may arm on devices subjeded ro moo enevgy ESD Theveiove, pvopev ESD pvetaunom should he Kaken ro avmd pElfurmanze degvadauon or ‘05: of funnmnalmy Table 18. Maximum Continuous Working Volmge R716 Narrow Body [squ] Package
Data Sheet ADuM130D/ADuM130E/ADuM131D/ADuM131E
Rev. A | Page 13 of 22
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 17.
Parameter Rating
Storage Temperature (TST) Range −65°C to +150°C
Ambient Operating Temperature
(TA) Range
−40°C to +125°C
Supply Voltages (VDD1, VDD2) −0.5 V to +7.0 V
Input Voltages (VIA, VIB, VIC, VE1, VE2,
DISABLE1, DISABLE2)
−0.5 V to VDDI1 + 0.5 V
Output Voltages (VOA, VOB, VOC) −0.5 V to VDDO2 + 0.5 V
Average Output Current per Pin3
Side 1 Output Current (IO1) −10 mA to +10 mA
Side 2 Output Current (IO2) −10 mA to +10 mA
Common-Mode Transients4 −150 kV/μs to +150 kV/μs
1 VDDI is the input side supply voltage.
2 VDDO is the output side supply voltage.
3 See Figure 5 for the R-16 narrow body [SOIC_N] package or Figure 6 for the
RW-16 wide body [SOIC_W] package for the maximum rated current values
for various ambient temperatures.
4 Refers to the common-mode transients across the insulation barrier.
Common-mode transients exceeding the absolute maximum ratings may
cause latch-up or permanent damage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Table 18. Maximum Continuous Working Voltage R-16 Narrow Body [SOIC_N] Package1
Parameter Rating Constraint2
AC Voltage
Bipolar Waveform
Basic Insulation 789 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation 403 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Unipolar Waveform
Basic Insulation 909 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation 469 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
DC Voltage
Basic Insulation 558 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation 285 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
2 Insulation lifetime for the specified test condition is greater than 50 years.
Table 19. Maximum Continuous Working Voltage RW-16 Wide Body [SOIC_W] Package1
Parameter Rating Constraint2
AC Voltage
Bipolar Waveform
Basic Insulation 849 V peak 50-year minimum insulation lifetime
Reinforced Insulation 768 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Unipolar Waveform
Basic Insulation 1698 V peak 50-year minimum insulation lifetime
Reinforced Insulation 768 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
DC Voltage
Basic Insulation
1092 V peak
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation 543 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
2 Insulation lifetime for the specified test condition is greater than 50 years.
ADuM130D/ADuM130E/ADuM131D/ADuM131E Data Sheet
Rev. A | Page 14 of 22
TRUTH TABLES
Table 20. ADuM130D/ADuM131D Truth Table (Positive Logic)
VIx Input1, 2 VDISABLEx Input1, 2 VDDI State2 V
DDO State2
Default Low (D0),
VOx Output1, 2, 3
Default High (D1),
VOx Output1, 2, 3 Test Conditions/Comments
L L or NC Powered Powered L L Normal operation
H L or NC Powered Powered H H Normal operation
X H Powered Powered L H Inputs disabled, fail-safe output
X4 X
4 Unpowered Powered L H Fail-safe output
X4 X
4 Powered Unpowered Indeterminate Indeterminate
1 L means low, H means high, X means don’t care, and NC means not connected.
2 VIx and VOx refer to the input and output signals of a given channel (A, B, or C). VDISABLEx refers to the input disable signal on the same side as the VIx inputs. VDDI and VDDO
refer to the supply voltages on the input and output sides of the given channel, respectively.
3 E0 refers to the ADuM130E0/ADuM131E0 models, D0 refers to the ADuM130D0/ADuM131D0 models, E1 refers to the ADuM130E1/ADuM131E1 models, and D1 refers
to the ADuM130D1/ADuM131D1 models. See the Ordering Guide section.
4 Input pins (VIx, DISABLE1, and DISABLE2) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection
circuitry.
Table 21. ADuM130E/ADuM131E Truth Table (Positive Logic)
VIx Input1, 2 VEx Input1, 2 V
DDI State2 V
DDO State2
Default Low (E0),
VOx Output1, 2, 3
Default High (E1),
VOx Output1, 2, 3 Test Conditions/Comments
L H or NC Powered Powered L L Normal operation
H H or NC Powered Powered H H Normal operation
X L Powered Powered Z Z Outputs disabled
L H or NC Unpowered Powered L H Fail-safe output
X4 L
4 Unpowered Powered Z Z Outputs disabled
X4 X
4 Powered Unpowered Indeterminate Indeterminate
1 L means low, H means high, X means don’t care, and NC means not connected, and Z means high impedance.
2 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and
VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.
3 E0 refers to the ADuM130E0/ADuM131E0 models, D0 refers to the ADuM130D0/ADuM131D0 models, E1 refers to the ADuM130E1/ADuM131E1 models, and D1 refers
to the ADuM130D1/ADuM131D1 models. See the Ordering Guide section.
4 Input pins (VIx, VE1, and VE2) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry.
33333333 EEEEEEEE a 5 33333333 EEEEEEEE ML Table 22. Pin Fundion Descriptions
Data Sheet ADuM130D/ADuM130E/ADuM131D/ADuM131E
Rev. A | Page 15 of 22
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
16
15
14
13
512
611
710
89
NIC = NO INTERNAL CONNECTION.
LEAVE THIS PIN FLOATING.
ADuM130D
TOP VIEW
(Not to Scale)
VDD1
GND1
VIA
VIB
VIC
NIC
DISABLE1
GND1
VDD2
GND2
VOA
VOB
VOC
NIC
NIC
GND2
13348-004
Figure 7. ADuM130D Pin Configuration
1
2
3
4
16
15
14
13
512
611
710
89
NIC = NO INTERNAL CONNECTION.
LEAVE THIS PIN FLOATING.
ADuM130E
TOP VIEW
(Not to Scale)
V
DD1
GND
1
V
IA
V
IB
V
IC
NIC
NIC
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
NIC
V
E2
GND
2
13348-005
Figure 8. ADuM130E Pin Configuration
Table 22. Pin Function Descriptions
Pin No. 1
ADuM130D
ADuM130E
Mnemonic
Description
1 1 VDD1 Supply Voltage for Isolator Side 1.
2, 8 2, 8 GND1 Ground 1. Ground reference for Isolator Side 1.
3 3 VIA Logic Input A.
4 4 VIB Logic Input B.
5 5 VIC Logic Input C.
6, 10, 11 6, 7, 11 NIC No Internal Connection. Leave these pins floating.
7 Not applicable DISABLE1 Input Disable 1. This pin disables the isolator inputs. Outputs take on the logic state
determined by the fail-safe option shown in the Ordering Guide.
9, 15 9, 15 GND2 Ground 2. Ground reference for Isolator Side 2.
Not applicable 10 VE2 Output Enable 2. Active high logic input. When VE2 is high or disconnected, the VOA, VOB,
and VOC outputs are enabled. When VE2 is low, the VOA, VOB, and VOC outputs are disabled
to the high-Z state.
12
12
V
OC
Logic Output C.
13 13 VOB Logic Output B.
14 14 VOA Logic Output A.
16 16 VDD2 Supply Voltage for Isolator Side 2.
1 Reference the AN-1109 Application Note for specific layout guidelines.
3333333] EEEEEEEE 33333333 EEEEEEEE
ADuM130D/ADuM130E/ADuM131D/ADuM131E Data Sheet
Rev. A | Page 16 of 22
1
2
3
4
16
15
14
13
512
6 11
710
8 9
NIC = NO INTERNAL CONNECTION.
LEAVE THIS PIN FLOATING.
ADuM131D
TOP VIEW
(Not to Scale)
VDD1
GND1
VIA
VIB
VOC
NIC
DISABLE1
GND1
VDD2
GND2
VOA
VOB
VIC
DISABLE2
NIC
GND2
13348-104
Figure 9. ADuM131D Pin Configuration
1
2
3
4
16
15
14
13
512
611
710
89
NIC = NO INTERNAL CONNECTION.
LEAVE THIS PIN FLOATING.
ADuM131E
TOP VIEW
(Not to Scale)
V
DD1
GND
1
V
IA
V
IB
V
OC
NIC
V
E1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
IC
NIC
V
E2
GND
2
13348-105
Figure 10. ADuM131E Pin Configuration
Table 23. Pin Function Descriptions
Pin No. 1
ADuM131D ADuM131E Mnemonic Description
1 1 VDD1 Supply Voltage for Isolator Side 1.
2, 8
2, 8
GND
1
Ground 1. Ground reference for Isolator Side 1.
3 3 VIA Logic Input A.
4 4 VIB Logic Input B.
5 5 VOC Logic Output C.
6, 11 6, 11 NIC No Internal Connection. Leave this pin floating.
7 Not applicable DISABLE1 Input Disable 1. This pin disables the isolator inputs. Outputs take on the logic state
determined by the fail-safe option shown in the Ordering Guide.
Not applicable 7 VE1 Output Enable 1. Active high logic input. When VE1 is high or disconnected, the VOC
output is enabled. When VE1 is low, the VOC output is disabled to the high-Z state.
9, 15 9, 15 GND2 Ground 2. Ground reference for Isolator Side 2.
10 Not applicable DISABLE2 Input Disable 2. This pin disables the isolator inputs. Outputs take on the logic state
determined by the fail-safe option shown in the Ordering Guide.
Not applicable 10 VE2 Output Enable 2. Active high logic input. When VE2 is high or disconnected, the VOA and
VOB outputs are enabled. When VE2 is low, the VOA and VOB outputs are disabled to the
high-Z state.
12 12 VIC Logic Input C.
13 13 VOB Logic Output B.
14 14 VOA Logic Output A.
16 16 VDD2 Supply Voltage for Isolator Side 2.
1 Reference the AN-1109 Application Note for specific layout guidelines.
// 1a _ i / , , , , , :. / .«s. .555 ELLE 3.5 Eummzu 3&3 1A 7:: a 233 225052.. 1G is. Eummzu 52:; _ 1A .2: ._ Eda 20:55.2; .1... £9.56 :3; _
Data Sheet ADuM130D/ADuM130E/ADuM131D/ADuM131E
Rev. A | Page 17 of 22
TYPICAL PERFORMANCE CHARACTERISTICS
IDD1 SUPPLY CURRENT (mA)
16
14
12
10
8
6
4
2
0
020 40 60 80
DATA RATE (Mbps)
100 120 140 160
5.0V
3.3V
2.5V
1.8V
13348-110
Figure 11. ADuM130D/ADuM130E IDD1 Supply Current vs. Data Rate at
Various Voltages
0
2
4
6
8
10
12
14
16
020 40 60 80 100 120 140 160
I
DD2
SUPPLY CURRENT (mA)
DATA RATE (Mbps)
5.0V
3.3V
2.5V
1.8V
13348-111
Figure 12. ADuM130D/ADuM130E IDD2 Supply Current vs. Data Rate at
Various Voltages
0
2
4
6
8
10
12
14
16
020 40 60 80 100 120 140 160
I
DD1 SUPPLY CURRENT (mA)
DATA RATE (Mbps)
5.0V
3.3V
2.5V
1.8V
13348-112
Figure 13. ADuM131D/ADuM131E IDD1 Supply Current vs. Data Rate at
Various Voltages
0
2
4
6
8
10
12
14
16
020 40 60 80 100 120 140 160
I
DD2
SUPPLY CURRENT (mA)
DATA RATE (Mbps)
5.0V
3.3V
2.5V
1.8V
13348-113
Figure 14. ADuM131D/ADuM131E IDD2 Supply Current vs. Data Rate at
Various Voltages
0
2
4
6
8
10
12
14
–40 –20 020 40 60 80 100 120 140
PROPAGATION DELAY (
t
PLH
) (ns)
TEMPERATURE (°C)
5.0V
3.3V
2.5V
1.8V
13348-114
Figure 15. Propagation Delay (tPLH) vs. Temperature at Various Voltages
0
2
4
6
8
10
12
14
–40 –20 020 40 60 80 100 120 140
PROPAGATION DELAY (
t
PHL
) (ns)
TEMPERATURE (°C)
5.0V
3.3V
2.5V
1.8V
13348-115
Figure 16. Propagation Delay( tPHL) vs. Temperature at Various Voltages
2:; 5:;
ADuM130D/ADuM130E/ADuM131D/ADuM131E Data Sheet
Rev. A | Page 18 of 22
APPLICATIONS INFORMATION
OVERVIEW
The ADuM130D/ADuM130E/ADuM131D/ADuM131E use a
high frequency carrier to transmit data across the isolation barrier
using iCoupler chip scale transformer coils separated by layers of
polyimide isolation. Using an on/off keying (OOK) technique
and the differential architecture shown in Figure 18 and Figure 19,
the ADuM130D/ADuM130E/ADuM131D/ADuM131E have very
low propagation delay and high speed. Internal regulators and
input/output design techniques allow logic and supply voltages
over a wide range from 1.7 V to 5.5 V, offering voltage translation
of 1.8 V, 2.5 V, 3.3 V, and 5 V logic. The architecture is designed
for high common-mode transient immunity and high immunity to
electrical noise and magnetic interference. Radiated emissions
are minimized with a spread spectrum OOK carrier and other
techniques.
Figure 18 illustrates the waveforms for models of the ADuM130D/
ADuM130E/ADuM131D/ADuM131E that have the condition of
the fail-safe output state equal to low, where the carrier waveform is
off when the input state is low. If the input side is off or not
operating, the fail-safe output state of low (the ADuM130D0,
ADuM131D0, ADuM130E0, and ADuM131E0 models) sets the
output to low. For the ADuM130D/ADuM130E/ADuM131D/
ADuM131E that have a fail-safe output state of high, Figure 19
illustrates the conditions where the carrier waveform is off
when the input state is high. When the input side is off or not
operating, the fail-safe output state of high (the ADuM130D1,
ADuM131D1, ADuM130E1, and ADuM131E1 models) sets the
output to high. See the Ordering Guide for the model numbers
that have the fail-safe output state of low or the fail-safe output
state of high.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADuM130D/ADuM130E/ADuM131D/ADuM131E digital
isolators require no external interface circuitry for the logic
interfaces. Power supply bypassing is strongly recommended at
the input and output supply pins (see Figure 17). Bypass capacitors
are most conveniently connected between Pin 1 and Pin 2 for
VDD1 and between Pin 15 and Pin 16 for VDD2. The recommended
bypass capacitor value is between 0.01 µF and 0.1 µF. The total
lead length between both ends of the capacitor and the input
power supply pin must not exceed 10 mm. Bypassing between
Pin 1 and Pin 8 and between Pin 9 and Pin 16 must also be
considered, unless the ground pair on each package side is
connected close to the package.
V
DD1
GND
1
V
IA
V
IB
V
IC
/V
OC
NIC
DISABLE
1
/V
E1
NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.
GND
1
V
DD2
GND
2
V
OA
V
OB
V
IC
/V
OC
NIC
DISABLE
2
/V
E2
GND
2
13348-010
Figure 17. Recommended PCB Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling that
does occur equally affects all pins on a given component side.
Failure to ensure this can cause voltage differentials between pins
exceeding the Absolute Maximum Ratings of the device, thereby
leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
TRANSMITTER
GND
1
GND
2
V
IN
V
OUT
RECEIVER
REGULATOR REGULATOR
13348-014
Figure 18. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State
TRANSMITTER
GND
1
GND
2
V
IN
V
OUT
RECEIVER
REGULATOR REGULATOR
13348-015
Figure 19. Operational Block Diagram of a Single Channel with a High Fail-Safe Output State
Data Sheet ADuM130D/ADuM130E/ADuM131D/ADuM131E
Rev. A | Page 19 of 22
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a Logic 0 output may differ from the propagation delay
to a Logic 1 output.
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
13348-011
Figure 20. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how accurately
the timing of the input signal is preserved.
Channel matching is the maximum amount the propagation
delay differs between channels within a single ADuM130D/
ADuM130E/ADuM131D/ADuM131E component.
Propagation delay skew is the maximum amount the propagation
delay differs between multiple ADuM130D/ADuM130E/
ADuM131D/ADuM131E components operating under the
same conditions.
JITTER MEASUREMENT
Figure 21 shows the eye diagram for the ADuM130D/ADuM130E/
ADuM131D/ADuM131E. The measurement was taken using an
Agilent 81110A pulse pattern generator at 150 Mbps with pseudo-
random bit sequences (PRBS), 2(n − 1), n = 14, for 5 V supplies.
Jitter was measured with the Tektronix Model 5104B oscilloscope,
at 1 GHz, 10 GSPS with the DPOJET jitter and eye diagram
analysis tools. The result shows a typical measurement on the
ADuM130D/ADuM130E/ADuM131D/ADuM131E with
630 ps p-p jitter.
105
0
1
2
3
4
VOLTAGE (V)
5
0
TIME (ns)
–5–10
13348-012
Figure 21. Eye Diagram
INSULATION LIFETIME
All insulation structures eventually break down when subjected to
voltage stress over a sufficiently long period. The rate of insulation
degradation is dependent on the characteristics of the voltage
waveform applied across the insulation as well as on the materials
and material interfaces.
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components that allows the components to be
categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in each
system level standard and is based on the total rms voltage across
the isolation, pollution degree, and material group. The material
group and creepage for the ADuM130D/ADuM130E/
ADuM131D/ADuM131E isolators are presented in Table 9.
Insulation Wear Out
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. It is the working voltage applicable
to tracking that is specified in most standards.
Testing and modeling have shown that the primary driver of
long-term degradation is displacement current in the polyimide
insulation causing incremental damage. The stress on the insula-
tion can be broken down into broad categories, such as dc stress,
which causes very little wear out because there is no displacement
current, and an ac component time varying voltage stress, which
causes wear out.
ADuM130D/ADuM130E/ADuM131D/ADuM131E Data Sheet
Rev. A | Page 20 of 22
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this reflects isolation from line
voltage. However, many practical applications have combinations
of 60 Hz ac and dc across the barrier as shown in Equation 1.
Because only the ac portion of the stress causes wear out, the
equation can be rearranged to solve for the ac rms voltage, as
shown in Equation 2. For insulation wear out with the polyimide
materials used in these products, the ac rms voltage determines
the product lifetime.
22
DCRMSACRMS
VVV +=
(1)
or
22
DCRMSRMSAC
VVV −=
(2)
where:
VAC RMS is the time varying portion of the working voltage.
VRMS is the total rms working voltage.
VDC is the dc offset of the working voltage.
Calculation and Use of Parameters Example
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 V ac rms and a 400 V dc bus voltage is present
on the other side of the isolation barrier. The isolator material is
polyimide. To establish the critical voltages in determining the
creepage, clearance, and lifetime of a device, see Figure 22 and
the following equations.
The working voltage across the barrier from Equation 1 is
22
DCRMSACRMS
VVV +=
22
400240 +=
RMS
V
VRMS = 466 V
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the
creepage required by a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
22
DCRMSRMSAC
VVV −=
22 400466 −=
RMSAC
V
VAC RMS = 240 V rms
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform is
not sinusoidal. The value is compared to the limits for working
voltage in Table 19 for the expected lifetime, less than a 60 Hz
sine wave, and it is well within the limit for a 50-year service life.
Note that the dc working voltage limit in Table 19 is set by the
creepage of the package as specified in IEC 60664-1. This value
can differ for specific system level standards.
ISOLATION VOLTAGE
TIME
V
AC RMS
V
RMS
V
DC
V
PEAK
13348-013
Figure 22. Critical Voltage Example
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Data Sheet ADuM130D/ADuM130E/ADuM131D/ADuM131E
Rev. A | Page 21 of 22
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AC
10.00 (0.3937)
9.80 (0.3858)
16 9
8
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
060606-A
45°
Figure 23. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-16)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 24. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ANALOG DEVICES www.ana|ug.cum
ADuM130D/ADuM130E/ADuM131D/ADuM131E Data Sheet
Rev. A | Page 22 of 22
ORDERING GUIDE
Model1
Temperature
Range
No. of
Inputs,
VDD1
Side
No. of
Inputs,
VDD2
Side
Withstand
Voltage
Rating
(kV rms)
Fail-Safe
Output
State
Input
Disable
Output
Enable
Package
Description
Package
Option
ADuM130D1BRZ −40°C to +125°C 3 0 3.0 High Yes No 16-Lead SOIC_N R-16
ADuM130D1BRZ-RL7 −40°C to +125°C 3 0 3.0 High Yes No 16-Lead SOIC_N R-16
ADuM130D0BRZ −40°C to +125°C 3 0 3.0 Low Yes No 16-Lead SOIC_N R-16
ADuM130D0BRZ-RL7 −40°C to +125°C 3 0 3.0 Low Yes No 16-Lead SOIC_N R-16
ADuM130E1BRZ −40°C to +125°C 3 0 3.0 High No Yes 16-Lead SOIC_N R-16
ADuM130E1BRZ-RL7 −40°C to +125°C 3 0 3.0 High No Yes 16-Lead SOIC_N R-16
ADuM130E0BRZ −40°C to +125°C 3 0 3.0 Low No Yes 16-Lead SOIC_N R-16
ADuM130E0BRZ-RL7 −40°C to +125°C 3 0 3.0 Low No Yes 16-Lead SOIC_N R-16
ADuM130D1BRWZ −40°C to +125°C 3 0 3.75 High Yes No 16-Lead SOIC_W RW-16
ADuM130D1BRWZ-RL −40°C to +125°C 3 0 3.75 High Yes No 16-Lead SOIC_W RW-16
ADuM130D0BRWZ −40°C to +125°C 3 0 3.75 Low Yes No 16-Lead SOIC_W RW-16
ADuM130D0BRWZ-RL −40°C to +125°C 3 0 3.75 Low Yes No 16-Lead SOIC_W RW-16
ADuM130E1BRWZ −40°C to +125°C 3 0 3.75 High No Yes 16-Lead SOIC_W RW-16
ADuM130E1BRWZ-RL −40°C to +125°C 3 0 3.75 High No Yes 16-Lead SOIC_W RW-16
ADuM130E0BRWZ −40°C to +125°C 3 0 3.75 Low No Yes 16-Lead SOIC_W RW-16
ADuM130E0BRWZ-RL −40°C to +125°C 3 0 3.75 Low No Yes 16-Lead SOIC_W RW-16
ADuM131D1BRZ −40°C to +125°C 2 1 3.0 High Yes No 16-Lead SOIC_N R-16
ADuM131D1BRZ-RL7 −40°C to +125°C 2 1 3.0 High Yes No 16-Lead SOIC_N R-16
ADuM131D0BRZ −40°C to +125°C 2 1 3.0 Low Yes No 16-Lead SOIC_N R-16
ADuM131D0BRZ-RL7 −40°C to +125°C 2 1 3.0 Low Yes No 16-Lead SOIC_N R-16
ADuM131E1BRZ −40°C to +125°C 2 1 3.0 High No Yes 16-Lead SOIC_N R-16
ADuM131E1BRZ-RL7 −40°C to +125°C 2 1 3.0 High No Yes 16-Lead SOIC_N R-16
ADuM131E0BRZ −40°C to +125°C 2 1 3.0 Low No Yes 16-Lead SOIC_N R-16
ADuM131E0BRZ-RL7 −40°C to +125°C 2 1 3.0 Low No Yes 16-Lead SOIC_N R-16
ADuM131D1BRWZ −40°C to +125°C 2 1 3.75 High Yes No 16-Lead SOIC_W RW-16
ADuM131D1BRWZ-RL −40°C to +125°C 2 1 3.75 High Yes No 16-Lead SOIC_W RW-16
ADuM131D0BRWZ −40°C to +125°C 2 1 3.75 Low Yes No 16-Lead SOIC_W RW-16
ADuM131D0BRWZ-RL −40°C to +125°C 2 1 3.75 Low Yes No 16-Lead SOIC_W RW-16
ADuM131E1BRWZ −40°C to +125°C 2 1 3.75 High No Yes 16-Lead SOIC_W RW-16
ADuM131E1BRWZ-RL −40°C to +125°C 2 1 3.75 High No Yes 16-Lead SOIC_W RW-16
ADuM131E0BRWZ −40°C to +125°C 2 1 3.75 Low No Yes 16-Lead SOIC_W RW-16
ADuM131E0BRWZ-RL −40°C to +125°C 2 1 3.75 Low No Yes 16-Lead SOIC_W RW-16
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D13348-0-11/15(A)