Scheda tecnica LTM2886 di Analog Devices Inc.

Commenti/errori della scheda tecnica

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LTM2886

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For more information www.linear.com/LTM2886

TYPICAL APPLICATION

FEATURES DESCRIPTION

SPI/Digital or I2C µModule

Isolator with Fixed ±5V and

Adjustable 5V Regulated Power

The LTM

2886 is a complete galvanic digital µModule

(micromodule) isolator. No external components are

required. A single 3.3V or 5V supply powers both sides

of the interface through an integrated, isolated DC/DC

converter. A logic supply pin allows easy interfacing with

different logic levels from 1.62V to 5.5V, independent of

the main supply.

Available options are compliant with SPI and I2C (master

mode only) specifications.

The isolated side includes fixed ±5V and 5V adjustable

power supplies, each capable of providing more than

100mA of load current. The 5V adjustable supply may be

programmed via an external voltage divider.

Coupled inductors and an isolation power transformer

provide 2500VRMS of isolation between the input and out-

put logic interface. This device is ideal for systems where

the ground loop is broken, allowing for a large common

mode voltage range. Communication is uninterrupted for

common mode transients greater than 30kV/μs.

L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of

Analog Devices, Inc. All other trademarks are the property of their respective owners.

Isolated 4MHz SPI Interface

APPLICATIONS

n 6-Channel Logic Isolator: 2500VRMS for 1 Minute

n UL-CSA Recognized File #E151738

n Isolated DC Power:

n 3V to 5V Adjustable at Up to 100mA

n ±5V Fixed at Up to 100mA

n No External Components Required

n SPI/Digital (LTM2886-S) or I2C (LTM2886-I) Options

n High Common Mode Transient Immunity: 30kV/μs

n High Speed Operation:

n 10MHz Digital Isolation

n 4MHz/8MHz SPI Isolation

n 400kHz I2C Isolation

n 3.3V (LTM2886-3) or 5V (LTM2886-5) Operation

n 1.62V to 5.5V Logic Supply

n ±10kV ESD HBM Across the Isolation Barrier

n Maximum Continuous Working Voltage: 560VPEAK

n Low Current Shutdown Mode (<10µA)

n Low Profile (15mm × 11.25mm × 3.42mm) BGA Package

n Isolated SPI or I2C Interfaces

n Industrial Systems

n Test and Measurement Equipment

n Breaking Ground Loops

LTM2886 Operating Through 50kV/µs CM Transients

2886 TA01a

CS CS2

LTM2886-5S

VCC

GND GND2

SDI

SDOE

SDI2

DO2

SCK SCK2

SDI

SCK

SDI

SCK

V–

AVCC2

V+

VCC2

SDO SDO2

SDO

DO1 I1

ISOLATION BARRIER

5V AT 100mA

–5V AT 100mA

20ns/DIV

5V/DIV

200V/DIV

SCK

SD0

SCK2 = SD02

2886 TA01b

REPETITIVE

COMMON MODE

TRANSIENTS

GND2 TO GND

LTM2886 TOP V‘EW TOP V‘EW

LTM2886

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LTM2886-I LTM2886-S

VCC

GNDDO1

GND2 GND2I1

BGA PACKAGE

32-PIN (15mm

11.25mm

3.42mm)

TOP VIEW

AVCC2

21 43 5 6 7 8

DNCDO2 SDASCL DI1 GND ON VL

DNCI2 SDA2SCL2 O1 VCC2 V–V+

TJMAX = 125°C, θJA = 25.5°C/W, θJC(BOTTOM) = 9.2°C/W,

θJC(TOP) = 16.6°C/W, θJBOARD = 9.9°C/W

θ VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g

VCC

GNDDO1

GND2 GND2I1

BGA PACKAGE

32-PIN (15mm

11.25mm

3.42mm)

TOP VIEW

AVCC2

21 43 5 6 7 8

DO2SDO SDISCK CS SDOE ON VL

I2SDO2 SDI2SCK2 CS2 VCC2 V–V+

TJMAX = 125°C, θJA = 25.5°C/W, θJC(BOTTOM) = 9.2°C/W,

θJC(TOP) = 16.6°C/W, θJBOARD = 9.9°C/W

θ VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g

ABSOLUTE MAXIMUM RATINGS

VCC to GND .................................................. –0.3V to 6V

VL to GND .................................................... –0.3V to 6V

VCC2, AVCC2 to GND2 ................................... –0.3V to 6V

V+ to GND2 .................................................. –0.3V to 6V

V– to GND2 .................................................. 0.3V to –6V

Logic Inputs

DI1, SCK, SDI, CS, SCL, SDA, SDOE,

ON to GND ..................................–0.3V to (VL + 0.3V)

I1, I2, SDA2,

SDO2 to GND2 ........................–0.3V to (VCC2 + 0.3V)

(Note 1)

PIN CONFIGURATION

Logic Outputs

DO1, DO2, SDO to GND ..............–0.3V to (VL + 0.3V)

O1, SCK2, SDI2, CS2,

SCL2 to GND2 ........................–0.3V to (VCC2 + 0.3V)

Operating Temperature Range (Note 4)

LTM2886C ............................................... 0°C to 70°C

LTM2886I ............................................–40°C to 85°C

LTM2886H ......................................... –40°C to 125°C

Maximum Internal Operating Temperature ............ 125°C

Storage Temperature Range .................. –55°C to 125°C

Peak Body Reflow Temperature ............................ 245°C

8888888

LTM2886

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For more information www.linear.com/LTM2886

LTM2886 C Y -3 I #PBF

LEAD FREE DESIGNATOR

PBF = Lead Free

LOGIC OPTION

I = Inter-IC (I2C) Bus

S = Serial Peripheral Interface (SPI) Bus

INPUT VOLTAGE RANGE

3 = 3V to 3.6V

5 = 4.5V to 5.5V

PACKAGE TYPE

Y = Ball Grid Array (BGA)

TEMPERATURE GRADE

C = Commercial Temperature Range (0°C to 70°C)

I = Industrial Temperature Range (–40°C to 85°C)

H = Automotive Temperature Range (–40°C to 125°C)

PRODUCT PART NUMBER

ORDER INFORMATION

PRODUCT SELECTION GUIDE

PART NUMBER

PAD OR BALL

FINISH

PART MARKING

PACKAGE

TYPE

MSL

RATING

INPUT VOLTAGE

RANGE

LOGIC

OPTION

TEMPERATURE

RANGE DEVICE FINISH CODE

LTM2886CY-3I#PBF

SAC305 (RoHS)

LTM2886Y-3I

e1 BGA 3

3V to 3.6V

I2C

0°C to 70°C

LTM2886IY-3I#PBF –40°C to 85°C

LTM2886HY-3I#PBF –40°C to 125°C

LTM2886CY-3S#PBF

LTM2886Y-3S SPI

0°C to 70°C

LTM2886IY-3S#PBF –40°C to 85°C

LTM2886HY-3S#PBF –40°C to 125°C

LTM2886CY-5I#PBF

LTM2886Y-5I

4.5V to 5.5V

I2C

0°C to 70°C

LTM2886IY-5I#PBF –40°C to 85°C

LTM2886HY-5I#PBF –40°C to 125°C

LTM2886CY-5S#PBF

LTM2886Y-5S SPI

0°C to 70°C

LTM2886IY-5S#PBF –40°C to 85°C

LTM2886HY-5S#PBF –40°C to 125°C

• Device temperature grade is indicated by a label on the

shipping container.

• Pad or ball finish code is per IPC/JEDEC J-STD-609.

• Terminal Finish Part Marking: www.linear.com/leadfree

• This product is not recommended for second side reflow. For

more information, go to www.linear.com/BGA-assy

• Recommended BGA PCB Assembly and Manufacturing Procedures: www.linear.

com/BGA-assy

• BGA Package and Tray Drawings: www.linear.com/packaging

• This product is moisture sensitive. For more information, go to:

www.linear.com/BGA-assy

http://www.linear.com/product/LTM2886#orderinfo

LTM2886

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For more information www.linear.com/LTM2886

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating

temperature range, otherwise specifications are at TA = 25°C. LTM2886-3 VCC = 3.3V, LTM2886-5 VCC = 5V, VL = 3.3V, and GND =

GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Supplies

VCC Input Supply Range LTM2886-3

LTM2886-5

4.5 3.3

53.6

5.5 V

VLLogic Supply Range LTM2886-S

LTM2886-I

1.62

55.5

5.5 V

ICC Input Supply Current ON = 0V

LTM2886-3, No Load

LTM2886-5, No Load

µA

ILLogic Supply Current ON = 0V

LTM2886-S, ON = VL

LTM2886-I, ON = VL

10 10

150

µA

Output Supplies

VCC2 Regulated Output Voltage No Load, AVCC2 OPEN l4.75 5 5.25 V

Output Voltage Operating Range (Note 2) 3 5.5 V

Line Regulation ILOAD = 1mA, MIN ≤ VCC ≤ MAX l2 7.5 mV

Load Regulation ILOAD = 1mA to 100mA l15 100 mV

ADJ Pin Voltage ILOAD = 1mA to 100mA l1.15 1.220 1.27 V

Voltage Ripple ILOAD = 100mA (Note 2) 1 mVRMS

Efficiency LTM2886-5, ILOAD = 100mA (Note 2) 61 %

ICC2 Output Short Circuit Current VCC2 = 0V 150 mA

Current Limit ΔVCC2 = –5% l90 mA

V+Regulated Output Voltage No Load l4.8 5 5.2 V

Line Regulation ILOAD = 1mA, MIN ≤ VCC ≤ MAX l2 7.5 mV

Load Regulation ILOAD = 1mA to 100mA l35 150 mV

Voltage Ripple ILOAD = 100mA (Note 2) 1 mVRMS

Efficiency LTM2886-5, ILOAD = 100mA (Note 2) 61 %

I+Output Short Circuit Current V+ = 0V 150 mA

Current Limit ΔV+ = –5% l90 mA

V–Regulated Output Voltage No Load l–4.8 –5 –5.2 V

Line Regulation ILOAD = –1mA, MIN ≤ VCC ≤ MAX l5 15 mV

Load Regulation ILOAD = 1mA to 100mA l35 150 mV

Voltage Ripple ILOAD = 100mA (Note 2) 1 mVRMS

Efficiency LTM2886-5, ILOAD = 100mA (Note 2) 61 %

I–Output Short-Circuit Current V– = 0V 150 mA

Current Limit ΔV– = 5% l90 mA

LTM2886

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ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Logic/SPI

VITH Input Threshold Voltage ON, DI1, SDOE, SCK, SDI, CS: 1.62V ≤ VL < 2.35V

ON, DI1, SDOE, SCK, SDI, CS: 2.35V ≤ VL

I1, I2, SDO2

0.25 • VL

0.33 • VL

0.33 • VCC2

0.75 • VL

0.67 • VL

0.67 • VCC2

IINL Input Current l±1 µA

VHYS Input Hysteresis 150 mV

VOH Output High Voltage DO1, DO2, SDO,

ILOAD = –1mA, 1.62V ≤ VL < 3V,

ILOAD = –4mA, 3V ≤ VL ≤ 5.5V

lVL – 0.4 V

O1, SCK2, SDI2, CS2, ILOAD = –4mA lVCC2 – 0.4 V

VOL Output Low Voltage DO1, DO2, SDO,

ILOAD = 1mA, 1.62V ≤ VL < 3V,

ILOAD = 4mA, 3V ≤ VL ≤ 5.5V

l0.4 V

O1, SCK2, SDI2, CS2, ILOAD = 4mA l0.4 V

ISC Short-Circuit Current 0V ≤ (DO1, DO2, SDO) ≤ VL

0V ≤ (O1, SCK2, SDI2, CS2) ≤ VCC2

±60 ±85 mA

I2C

VIL Low Level Input Voltage SCL, SDA

SDA2

0.3 • VL

0.3 • VCC2

VIH High Level Input Voltage SCL, SDA

SDA2

0.7 • VL

0.7 • VCC2

IINL Input Current SCL, SDA = VL or 0V

SDA2 = VCC2, SDA2 = VCC2 = 0V

±1

±1 µA

µA

VHYS Input Hysteresis SCL, SDA

SDA2 0.05 • VL

0.05 • VCC2

VOH Output High Voltage SCL2, ILOAD = –2mA

DO2, ILOAD = –2mA

VCC2 – 0.4

VL – 0.4 V

VOL Output Low Voltage SDA, ILOAD = 3mA

DO2, ILOAD = 2mA

SCL2, ILOAD = 2mA

SDA2, No Load, SDA = 0V, 4.5V ≤ VCC2 < 5.5V

SDA2, No Load, SDA = 0V, 3V ≤ VCC2 < 4.5V

0.3

0.4

0.45

0.55

CIN Input Pin Capacitance SCL, SDA, SDA2 (Note 2) l10 pF

CBBus Capacitive Load SCL2, Standard Speed (Note 2)

SCL2, Fast Speed

SDA, SDA2, SR ≥ 1V/µs, Standard Speed (Note 2)

SDA, SDA2, SR ≥ 1V/µs, Fast Speed

400

200

400

200

Minimum Bus Slew Rate SDA, SDA2 l1 V/µs

ISC Short-Circuit Current SDA2 = 0, SDA = VL

0V ≤ SCL2 ≤ VCC2

0V ≤ DO2 ≤ VL

SDA = 0, SDA2 = VCC2

SDA = VL, SDA2 = 0

±30

–1.8

100 mA

ESD (HBM) (Note 2)

Isolation Boundary (VCC2, V+, V–, GND2) to (VCC, VL, GND) ±10 kV

The l denotes the specifications which apply over the specified operating

temperature range, otherwise specifications are at TA = 25°C. LTM2886-3 VCC = 3.3V, LTM2886-5 VCC = 5V, VL = 3.3V, and GND =

GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.

LTM2886

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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Logic

Maximum Data Rate DI1 → O1, Ix → DOx, CL = 15pF (Note 3) l10 MHz

tPHL, tPLH Propagation Delay CL = 15pF (Figure 1) l35 60 100 ns

tRRise Time CL = 15pF (Figure 1)

LTM2886-I, DO2, CL = 15pF (Figure 1)

20 12.5

35 ns

tFFall Time CL = 15pF (Figure 1)

LTM2886-I, DO2, CL = 15pF (Figure 1)

20 12.5

35 ns

SPI

Maximum Data Rate Bidirectional Communication (Note 3)

Unidirectional Communication (Note 3)

8MHz

MHz

tPHL, tPLH Propagation Delay CL = 15pF (Figure 1) l35 60 100 ns

tPWU Output Pulse Width Uncertainty SDO, SDI2, CS2 (Note 2) ±50 ns

tRRise Time CL = 15pF (Figure 1) l3 12.5 ns

tFFall Time CL = 15pF (Figure 1) l3 12.5 ns

tPZH, tPZL Output Enable Time SDOE = ↓, RL = 1kΩ, CL = 15pF (Figure 2) l50 ns

tPHZ, tPLZ Output Disable Time SDOE = ↑, RL = 1kΩ, CL = 15pF (Figure 2) l50 ns

I2C

Maximum Data Rate (Note 3) l400 kHz

tPHL, tPLH Propagation Delay SCL → SCL2, CL = 15pF (Figure 1)

SDA → SDA2, RL = Open, CL = 15pF (Figure 3)

SDA2 → SDA, RL = 1.1kΩ, CL = 15pF (Figure 3)

150

300

225

250

500

tPWU Output Pulse Width Uncertainty SDA, SDA2 (Note 2) ±50 ns

tHD;DAT Data Hold Time (Note 2) 600 ns

tRRise Time SDA2, CL = 200pF (Figure 3)

SDA, RL = 1.1kΩ CL = 200pF (Figure 3)

SCL2, CL = 200pF (Figure 1)

40 300

250

tFFall Time SDA2, CL = 200pF (Figure 3)

SDA, RL = 1.1kΩ CL = 200pF (Figure 3)

SCL2, CL = 200pF (Figure 1)

40 250

250

tSP Pulse Width of Spikes Suppressed

by Input Filter

l0 50 ns

Power Supply

Power-Up Time ON = ↑ to VCC2 (Min)

ON = ↑ to V+ (Min)

ON = ↑ to V– (Min)

0.6

SWITCHING CHARACTERISTICS

The l denotes the specifications which apply over the specified operating

temperature range, otherwise specifications are at TA = 25°C. LTM2886-3 VCC = 3.3V, LTM2886-5 VCC = 5V, VL = 3.3V, and GND =

GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.

LTM2886 288573 :33 —=——— V/ \ \

LTM2886

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Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Guaranteed by design and not subject to production test.

Note 3: Maximum Data rate is guaranteed by other measured parameters

and is not tested directly.

Note 4: This Module includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above specified maximum operating junction

temperature may result in device degradation or failure.

Note 5: Device considered a 2-terminal device. Pin group A1 through B8

shorted together and pin group K1 through L8 shorted together.

Note 6: The rated dielectric insulation voltage should not be interpreted as

a continuous voltage rating.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VISO Rated Dielectric Insulation Voltage 1 Minute, Derived from 1 Second Test

1 Second (Notes 5, 6) 2500

3000 VRMS

VRMS

Common Mode Transient Immunity LTM2886-3 VCC = 3.3V, LTM2885-5 VCC = 5V,

VL = ON = 3.3V, VCM = 1kV, Δt = 33ns (Note 2) 30 kV/µs

VIORM Maximum Continuous Working Voltage (Notes 2, 5) 560

400

VPEAK,

VDC

VRMS

Partial Discharge VPD = 750VRMS (Note 5) 5 pC

CTI Comparative Tracking Index IEC 60112 (Note 2) 600 VRMS

Depth of Erosion IEC 60112 (Note 2) 0.017 mm

DTI Distance Through Insulation (Note 2) 0.06 mm

Input to Output Resistance (Notes 2, 5) 109Ω

Input to Output Capacitance (Notes 2, 5) 6 pF

Creepage Distance (Note 2) 9.5 mm

ISOLATION CHARACTERISTICS

TA = 25°C.

TYPICAL PERFORMANCE CHARACTERISTICS

Isolated Supplies

vs Equal Load Current

VCC Supply Current

vs Temperature

Isolated Supplies

vs Equal Load Current

TA = 25°C, LTM2886-3 VCC = 3.3V,

LTM2886-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.

TEMPERATURE (°C)

–50

SUPPLY CURRENT (mA)

10 500 100

2886 G01

12525–25 75

LTM2886-3

VCC = 3.3V

LTM2886-5

VCC = 5V

NO LOAD, REFRESH DATA ONLY

LOAD CURRENT (mA)

VOLTAGE (V)

5.50

4.25

4.50

4.75

5.00

5.25

4.00 5030 4010 20

2886 G02

VCC2

V+

|V–|

LTM2886-3

VCC = 3.3V

LOAD CURRENT (mA)

VOLTAGE (V)

5.50

4.50

4.25

4.75

5.00

5.25

4.00 604020

2886 G03

10080

LTM2886-5

VCC = 5V

VCC2

V+

|V–|

LTM2886 ___: $3,; \ ___: \ _—_: \ \ \ “x \ ~\ \__.__. \ \\ \\ / / 75/:1— :"/ ,\ I ,— ——"— -~~§ / ,w’ — \ //’ \\ 14,— \ r

LTM2886

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VCC2 Line Regulation

vs Load Current

V+ Line Regulation

vs Load Current

V– Line Regulation

vs Load Current

VCC2 Line Regulation

vs Load Current

V+ Line Regulation

vs Load Current

V– Line Regulation

vs Load Current

V+ Load Regulation

vs Temperature

V– Load Regulation

vs Temperature

VCC2 Load Regulation

vs Temperature

LOAD CURRENT (mA)

VCC2 VOLTAGE (V)

6.0

3.0

3.5

4.0

4.5

5.0

5.5

2.5 5025 75 100 125 150 175

2886 G04

200

VCC = 3V

VCC = 3.3V

VCC = 3.6V

LTM2886-3

LOAD CURRENT (mA)

V+ VOLTAGE (V)

6.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

755025 100

2886 G05

200175150125

VCC = 3V

VCC = 3.3V

VCC = 3.6V

LTM2886-3 6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

LOAD CURRENT (mA)

|V–| VOLTAGE (V)

150 17525 50 75 100 125

2886 G06

200

VCC = 3V

VCC = 3.3V

VCC = 3.6V

LTM2886-3

LOAD CURRENT (mA)

VCC2 VOLTAGE (V)

6.0

3.0

3.5

4.0

4.5

5.0

5.5

2.5 10050 150 200 250

2886 G07

300

VCC = 4.5V

VCC = 5V

VCC = 5.5V

LTM2886-5

LOAD CURRENT (mA)

V+ VOLTAGE (V)

6.0

3.0

3.5

4.0

4.5

5.0

5.5

2.5 10050 150

2886 G08

300250200

LTM2886-5

VCC = 4.5V

VCC = 5V

VCC = 5.5V

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

LOAD CURRENT (mA)

|V–| VOLTAGE (V)

20050 100 150 250

2886 G09

300

VCC = 4.5V

VCC = 5V

VCC = 5.5V

LTM2886-5

TEMPERATURE (°C)

–50

VCC2 VOLTAGE (V)

5.15

5.00

5.10

5.05

4.95

4.85

4.90

500 100

2886 G10

12525–25 75

ICC2 = 1mA

ICC2 = 100mA

LTM2886-3

VCC = 3.3V

TEMPERATURE (°C)

–50

V+ VOLTAGE (V)

5.15

5.00

5.10

5.05

4.95

4.85

4.90

500 100

2886 G11

12525–25 75

I+ = 1mA

I+ = 100mA

LTM2886-3

VCC = 3.3V

TEMPERATURE (°C)

–50

|V–| VOLTAGE (V)

5.15

5.00

5.10

5.05

4.95

4.85

4.90

500 100

2886 G12

12525–25 75

LTM2886-3

VCC = 3.3V

I– = 1mA

I– = 100mA

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, LTM2886-3 VCC = 3.3V,

LTM2886-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.

LTM2886 ‘\ \ \l | /

LTM2886

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TYPICAL PERFORMANCE CHARACTERISTICS

V– Load Regulation

vs Temperature

VCC2 Efficiency

VCC2 Voltage and ICC Current

vs Load Current

VCC2 Load Regulation

vs Temperature

V+ Load Regulation

vs Temperature

TA = 25°C, LTM2886-3 VCC = 3.3V,

LTM2886-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.

V+ Efficiency

TEMPERATURE (°C)

–50

VCC2 VOLTAGE (V)

5.15

5.05

5.10

5.00

4.85

4.90

4.95

500 100

2886 G13

12525–25 75

LTM2886-5

VCC = 5V

ICC2 = 1mA

ICC2 = 100mA

TEMPERATURE (°C)

–50

V+ VOLTAGE (V)

5.15

5.00

5.10

5.05

4.95

4.85

4.90

500 100

2886 G14

12525–25 75

I+ = 1mA

I+ = 100mA

LTM2886-5

VCC = 5V

TEMPERATURE (°C)

–50

|V–| VOLTAGE (V)

5.15

4.90

5.10

5.05

5.00

4.95

4.85 500 100

2886 G15

12525–25 75

I– = 1mA

I– = 100mA

LTM2886-5

VCC = 5V

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (W)

1.4

1.0

0.6

0.8

0.4

0.2

1.2

0.0

15010050 200 250

2886 G16

300

EFFICIENCY

POWER LOSS

LTM2886-3, VCC = 3.3V

LTM2886-5, VCC = 5V

LOAD CURRENT (mA)

VCC2 VOLTAGE (V)

ICC CURRENT (mA)

600

400

200

300

100

500

15050 100 200 250

2886 G17

300

VOLTAGE

ICC CURRENT

LTM2886-3, VCC = 3.3V

LTM2886-5, VCC = 5V

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (W)

1.4

1.2

0.8

0.4

0.6

0.2

1.0

0.0

10050 200150

2886 G18

300250

EFFICIENCY

POWER LOSS

LTM2886-3, VCC = 3.3V

LTM2886-5, VCC = 5V

V+ Voltage and ICC Current

vs Load Current

0 15010050 200 300250

LOAD CURRENT (mA)

V+ VOLTAGE (V)

ICC CURRENT (mA)

600

400

200

300

100

500

2886 G19

VOLTAGE

ICC CURRENT

LTM2886-3, VCC = 3.3V

LTM2886-5, VCC = 5V

LTM2886 “IO

LTM2886

2886fb

For more information www.linear.com/LTM2886

TYPICAL PERFORMANCE CHARACTERISTICS

V– Efficiency

V– Voltage and ICC Current

vs Load Current

VCC2 Transient Response

100mA Load Step

V+ Transient Response

100mA Load Step

V– Transient Response

100mA Load Step

TA = 25°C, LTM2886-3 VCC = 3.3V,

LTM2886-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.

VCC2 Ripple V+ Ripple V– Ripple

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (W)

1.4

1.0

0.8

0.2

0.6

0.4

1.2

0.0

200 25010050 150

2886 G20

300

LTM2886-3, VCC = 3.3V

LTM2886-5, VCC = 5V

EFFICIENCY

POWER LOSS

LOAD CURRENT (mA)

|V–| VOLTAGE (V)

ICC CURRENT (mA)

600

300

100

200

400

500

25020015010050

2886 G21

300

LTM2886-3, VCC = 3.3V

LTM2886-5, VCC = 5V

ICC CURRENT

VOLTAGE

100µs/DIV

0.5V/DIV

50mA/DIV

2886 G22

100µs/DIV

0.5V/DIV

50mA/DIV

2886 G23 100µs/DIV

0.5V/DIV

50mA/DIV

2886 G24

400ns/DIV 2886 G25

2mV/DIV

LOAD = 1mA

LOAD = 100mA

400ns/DIV 2886 G26

LOAD = 1mA

LOAD = 100mA

2mV/DIV

400ns/DIV 2886 G27

LOAD = 1mA

LOAD = 100mA

2mV/DIV

LTM2886 ING WPUT FALLING son son 2 E E ma E‘ L: 8 son 3 — LTMZsssrz v ciaav E —- LTMZBBS'S V E=5V a zoo ‘ ‘ ‘ > ma BASED ON THERMAL \MAGWG \ or DEMO cmcuw mm: vm, v‘ v’ EQUALLV LOADED n a 25 50 75 Inn 125 TEMPERATURE 1°C) ‘I‘I

LTM2886

2886fb

For more information www.linear.com/LTM2886

TYPICAL PERFORMANCE CHARACTERISTICS

VCC Supply Current

vs Single Channel Data Rate

Logic Input Threshold

vs VL Supply Voltage

Logic Output Voltage

vs Load Current

TA = 25°C, LTM2886-3 VCC = 3.3V,

LTM2886-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.

VCC2 Noise V+ Noise V– Noise

Isolated Supply Efficiency with

Equal Load Current

Power On Sequence

Derating for 125°C Maximum

Internal Operating Temperature

1ms/DIV

2mV/DIV

2886 G28

LOAD = 100mA

1ms/DIV 2886 G29

2mV/DIV

LOAD = 100mA

1ms/DIV

2mV/DIV

2886 G30

LOAD = 100mA

DATA RATE (Hz)

VCC CURRENT (mA)

10 100k10k 1M

2886 G31

100M10M

VCC = 5VCL = 1nF

CL = 330pF

CL = 100pF

CL = 20pF

VL SUPPLY VOLTAGE (V)

THRESHOLD VOLTAGE (V)

3.5

2.5

0.5

1.0

2.0

3.0

1.5

04 52

2886 G32

INPUT RISING

INPUT FALLING

|LOAD CURRENT| (mA)

OUTPUT VOLTAGE (V)

021 3

2886 G33

10987654

VL = 5.5V

VL = 3.3V

VL = 1.62V

100µs/DIV

2.5V/DIV

1V/DIV

V–

VCC2

V+

2886 G34

LTM2886-5, VL = 5V

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (W)

1.4

0.2

0.4

0.6

1.0

0.8

1.2

0.0

50 6010 20 30 40 70 80 90

2886 G35

100

EFFICIENCY

POWER LOSS

LTM2886-3, VCC = 3.3V

LTM2886-5, VCC = 5V

BASED ON THERMAL IMAGING

OF DEMO CIRCUIT 1790A

CC2

, V

–

EQUALLY LOADED

LTM2886-3, VCC = 3.3V

LTM2886-5, VCC = 5V

TEMPERATURE (°C)

100

125

100

200

300

400

500

600

SUPPLY CURRENT (mA)

2886 G36

LTM2886 12

LTM2886

2886fb

For more information www.linear.com/LTM2886

PIN FUNCTIONS

Logic Side

DO2 (A1): Digital Output, Referenced to VL and GND. Logic

output connected to I2 through isolation barrier. Under

the condition of an isolation communication failure this

output is in a high impedance state.

DNC (A2): Do Not Connect. Pin connected internally.

SCL (A3): Serial I2C Clock Input, Referenced to VL and

GND. Logic input connected to isolated side SCL2 pin

through isolation barrier. Clock is unidirectional from logic

to isolated side. Do not float.

SDA (A4): Serial I2C Data Pin, Referenced to VL and GND.

Bidirectional logic pin connected to isolated side SDA2 pin

through isolation barrier. Under the condition of an isola-

tion communication failure this pin is in a high impedance

state. Do not float.

DI1 (A5): Digital Input, Referenced to VL and GND. Logic input

connected to O1 through isolation barrier. The logic state on

DI1 translates to the same logic state on O1. Do not float.

GND (A6, B2 to B6): Circuit Ground.

ON (A7): Enable, Referenced to VL and GND. Enables

power and data communication through the isolation

barrier. If ON is high the part is enabled and power and

communications are functional to the isolated side. If ON

is low the logic side is held in reset, all digital outputs

are in a high impedance state, and the isolated side is

unpowered. Do not float.

VL (A8): Logic Supply. Interface supply voltage for pins

DI1, SCL, SDA, DO1, DO2, and ON. Operating voltage is

1.62V to 5.5V. Internally bypassed with 1µF.

DO1 (B1): Digital Output, Referenced to VL and GND. Logic

output connected to I1 through isolation barrier. Under

the condition of an isolation communication failure this

output is in a high impedance state.

VCC (B7 to B8): Supply Voltage. Operating voltage is 3V

to 3.6V for LTM2886-3 and 4.5V to 5.5V for LTM2886-5.

Internally bypassed with 2.2µF.

Isolated Side

I2 (L1): Digital Input, Referenced to VCC2 and GND2.

Logic input connected to DO2 through isolation barrier.

The logic state on I2 translates to the same logic state on

DO2. Do not float.

DNC (L2): Do Not Connect. Pin connected internally.

SCL2 (L3): Serial I2C Clock Output, Referenced to VCC2

and GND2. Logic output connected to logic side SCL pin

through isolation barrier. Clock is unidirectional from logic

to isolated side. SCL2 has a push-pull output stage, do not

connect an external pull-up device. Under the condition

of an isolation communication failure this output defaults

to a high state.

SDA2 (L4): Serial I2C Data Pin, Referenced to VCC2 and

GND2. Bidirectional logic pin connected to logic side SDA

pin through isolation barrier. Output is biased high by a

1.8mA current source. Do not connect an external pull-

up device to SDA2. Under the condition of an isolation

communication failure this output defaults to a high state.

O1 (L5): Digital Output, Referenced to VCC2 and GND2.

Logic output connected to DI1 through isolation barrier.

Under the condition of an isolation communication failure

O1 defaults to a high state.

VCC2 (L6): 3V to 5.5V Adjustable Isolated Supply Voltage.

Internally generated from VCC by an isolated DC/DC con-

verter and regulated to 5V with no external components.

Internally bypassed with 2.2µF.

V– (L7): –5V Nominal Isolated Supply Voltage. Internally

generated from VCC by an isolated DC/DC converter and

regulated to –5V with no external components. Internally

bypassed with 2.2µF.

V+ (L8): 5V Nominal Isolated Supply Voltage. Internally

generated from VCC by an isolated DC/DC converter and

regulated to 5V with no external components. Internally

bypassed with 2.2µF.

I1 (K1): Digital Input, Referenced to VCC2 and GND2.

Logic input connected to DO1 through isolation barrier.

The logic state on I1 translates to the same logic state on

DO1. Do not float.

GND2 (K2 to K5, K7, K8): Isolated Ground.

AVCC2 (K6): 5V Nominal Isolated Supply Voltage Adjust.

The adjust pin voltage is 1.22V referenced to GND2. See

Applications Information section for details.

(LTM2886-I)

LTM2886 13

LTM2886

2886fb

For more information www.linear.com/LTM2886

PIN FUNCTIONS

Logic Side

SDO (A1): Serial SPI Digital Output, Referenced to VL

and GND. Logic output connected to isolated side SDO2

pin through isolation barrier. Under the condition of an

isolation communication failure this output is in a high

impedance state.

DO2 (A2): Digital Output, Referenced to VL and GND. Logic

output connected to I2 through isolation barrier. Under

the condition of an isolation communication failure this

output is in a high impedance state.

SCK (A3): Serial SPI Clock Input, Referenced to VL and

GND. Logic input connected to isolated side SCK2 pin

through isolation barrier. Do not float.

SDI (A4): Serial SPI Data Input, Referenced to VL and GND.

Logic input connected to isolated side SDI2 pin through

isolation barrier. Do not float.

CS (A5): Serial SPI Chip Select, Referenced to VL and GND.

Logic input connected to isolated side CS2 pin through

isolation barrier. Do not float.

SDOE (A6): Serial SPI Data Output Enable, Referenced to

VL and GND. A logic high on SDOE places the logic side

SDO pin in a high impedance state, a logic low enables

the output. Do not float.

ON (A7): Enable, Referenced to VL and GND. Enables power

and data communication through the isolation barrier. If ON

is high the part is enabled and power and communications

are functional to the isolated side. If ON is low the logic side

is held in reset, all digital outputs are in a high impedance

state, and the isolated side is unpowered. Do not float.

VL (A8): Logic Supply. Interface supply voltage for pins

SDI, SCK, SDO, SDOE, DO1, DO2, CS, and ON. Operating

voltage is 1.62V to 5.5V. Internally bypassed with 1µF.

DO1 (B1): Digital Output, Referenced to VL and GND. Logic

output connected to I1 through isolation barrier. Under

the condition of an isolation communication failure this

output is in a high impedance state.

GND (B2 to B6): Circuit Ground.

VCC (B7 to B8): Supply Voltage. Operating voltage is 3V

to 3.6V for LTM2886-3 and 4.5V to 5.5V for LTM2886-5.

Internally bypassed with 2.2µF.

Isolated Side

SDO2 (L1): Serial SPI Digital Input, Referenced to VCC2

and GND2. Logic input connected to logic side SDO pin

through isolation barrier. Do not float.

I2 (L2): Digital Input, Referenced to VCC2 and GND2.

Logic input connected to DO2 through isolation barrier.

The logic state on I2 translates to the same logic state on

DO2. Do not float.

SCK2 (L3): Serial SPI Clock Output, Referenced to VCC2

and GND2. Logic output connected to logic side SCK pin

through isolation barrier. Under the condition of an isolation

communication failure this output defaults to a low state.

SDI2 (L4): Serial SPI Data Output, Referenced to VCC2

and GND2. Logic output connected to logic side SDI pin

through isolation barrier. Under the condition of an isolation

communication failure this output defaults to a low state.

CS2 (L5): Serial SPI Chip Select, Referenced to VCC2 and

GND2. Logic output connected to logic side CS pin through

isolation barrier. Under the condition of an isolation com-

munication failure this output defaults to a high state.

VCC2 (L6): 3V to 5.5V Adjustable Isolated Supply Voltage.

Internally generated from VCC by an isolated DC/DC con-

verter and regulated to 5V with no external components.

Internally bypassed with 2.2µF.

V– (L7): –5V Nominal Isolated Supply Voltage. Internally

generated from VCC by an isolated DC/DC converter and

regulated to –5V with no external components. Internally

bypassed with 2.2µF.

V+ (L8): 5V Nominal Isolated Supply Voltage. Internally

generated from VCC by an isolated DC/DC converter and

regulated to 5V with no external components. Internally

bypassed with 2.2µF.

I1 (K1): Digital Input, Referenced to VCC2 and GND2.

Logic input connected to DO1 through isolation barrier.

The logic state on I1 translates to the same logic state on

DO1. Do not float.

GND2 (K2 to K5, K7, K8): Isolated Ground.

AVCC2 (K6): 5V Nominal Isolated Supply Voltage Adjust.

The adjust pin voltage is 1.22V Referenced to GND2. See

Applications Information section for details.

(LTM2886-S)

LTM2886 14

LTM2886

2886fb

For more information www.linear.com/LTM2886

BLOCK DIAGRAMS

(LTM2886-I)

2886 BD

1µF

2.2µF

VCC

VCC2

CC2

VL2.2µF

GND

SDA

DI1

DO2

DO1

SCL

V–

V+

SCL2

SDA2

GND2

DC/DC

CONVERTER

ISOLATED

COMMUNI-

CATIONS

INTERFACE

ISOLATED

COMMUNI-

CATIONS

INTERFACE

REG

2.2µF

REG

LTM2886 15

LTM2886

2886fb

For more information www.linear.com/LTM2886

(LTM2886-S)

2886 BDa

1µF

2.2µF

VCC

VCC2

CC2

VL2.2µF

GND

SDOE

DO2

SDI

SDO

DO1

SCK

CS2

V–

V+

SDO2

SCK2

SDI2

GND2

DC/DC

CONVERTER

ISOLATED

COMMUNI-

CATIONS

INTERFACE

ISOLATED

COMMUNI-

CATIONS

INTERFACE

REG

2.2µF

REG

8888888 16

LTM2886

2886fb

For more information www.linear.com/LTM2886

TEST CIRCUITS

INPUT

OUTPUT

CLtPLH tPHL

tRtF

90%

10%

90%

½VCC2

½VL

VOL

VOH

INPUT

OUTPUT

INPUT

OUTPUT

2886 F01

tPLH tPHL

tRtF

90%

10%

90%

½VL

½VCC2

VCC2

VOL

VOH

INPUT

OUTPUT

Figure 1. Logic Timing Measurements

Figure 2. Logic Enable/Disable Time

Figure 3. I2C Timing Measurements

2886 F02

SDOE

tPZH

tPZL

tPHZ

tPLZ

VOL + 0.5V

VOH – 0.5V

½VL

VOH

VOL

SDO

SDOE

½VL

SDO

OR 0V

VCC2

SDO2

tPHL tPLH

tFtR

30%

½VL70%

70%

30%

VOL

VOH

SDA

SDA2

VOL

VOH

SDA

SDA2

2886 F03

½VCC2

tPHL tPLH

tFtR

30%

½VCC2 70%

70%

30%

½VL

VCC2

SDA2

SDA

SDA2

LTM2886 3V T!) 3 6V LTMzaaera 17

LTM2886

2886fb

For more information www.linear.com/LTM2886

APPLICATIONS INFORMATION

Overview

The LTM2886 digital µModule isolator provides a

galvanically-isolated robust logic interface, powered by

an integrated, regulated DC/DC converter, complete with

decoupling capacitors. The LTM2886 is ideal for use in

networks where grounds can take on different voltages.

Isolation in the LTM2886 blocks high voltage differences,

eliminates ground loops and is extremely tolerant of com-

mon mode transients between ground planes. Error-free

operation is maintained through common mode events

greater than 30kV/μs providing excellent noise isolation.

Isolator µModule Technology

The LTM2886 utilizes isolator µModule technology to

translate signals and power across an isolation barrier.

Signals on either side of the barrier are encoded into

pulses and translated across the isolation boundary using

coreless transformers formed in the µModule substrate.

This system, complete with data refresh, error checking,

safe shutdown on fail, and extremely high common mode

immunity, provides a robust solution for bidirectional signal

isolation. The µModule technology provides the means to

combine the isolated signaling with multiple regulators and

a powerful isolated DC/DC converter in one small package.

DC/DC Converter

The LTM2886 contains a fully integrated DC/DC converter,

including the transformer, so that no external components

are necessary. The logic side contains a full-bridge driver,

running at 1.6MHz, and is AC-coupled to a single trans-

former primary. A series DC blocking capacitor prevents

transformer saturation due to driver duty cycle imbal-

ance. The transformer scales the primary voltage, and is

rectified by a voltage quadrupler

. This topology eliminates

transformer saturation caused by secondary imbalances.

The quadrupler is grounded in the middle producing sym-

metrical positive and negative voltage rails. The positive

rail is post regulated with two low dropout regulators

(LDOs) producing VCC2 and V+, the negative rail also has

an LDO producing V–.

Each voltage rail is capable of producing 100mA of output

current, total output power capability is approximately 1W.

All voltage rails are bypassed with 2.2µF ceramic capacitors.

VL Logic Supply

A separate logic supply pin VL allows the LTM2886 to in-

terface with any logic signal from 1.62V to 5.5V as shown

in Figure 4. Simply connect the desired logic supply to VL.

There is no interdependency between VCC and VL; they

may simultaneously operate at any voltage within their

specified operating ranges and sequence in any order. VL

is bypassed internally by a 1µF capacitor.

Hot-Plugging Safely

Caution must be exercised in applications where power is

plugged into the LTM2886’s power supplies, VCC or VL,

due to the integrated ceramic decoupling capacitors. The

parasitic cable inductance along with the high Q char-

acteristics of ceramic capacitors can cause substantial

ringing which could exceed the maximum voltage ratings

and damage the LTM2886. Refer to Linear Technology Ap-

plication Note 88, entitled Ceramic Input Capacitors Can

Cause Overvoltage Transients for a detailed discussion

and mitigation of this phenomenon.

2886 F04

DI1 O1

LTM2886-I

ANY VOLTAGE FROM

1.62V TO 5.5V

3V TO 3.6V LTM2886-3

4.5V TO 5.5V LTM2886-5

EXTERNAL

DEVICE

VCC

GND GND2

SDA SDA2

SCL SCL2

V–

AVCC2

V+

VCC2

DO2 I2

DO1 I1

ISOLATION BARRIER

Figure 4. VCC and VL Are Independent

LTM2886 18

LTM2886

2886fb

For more information www.linear.com/LTM2886

APPLICATIONS INFORMATION

Figure 5. Adjustable Voltage Rails

Isolated Supply Adjustable Operation

The VCC2 isolated power rail is nominally 5V, but may be

overdriven by adding two external resistors. The unadjusted

output voltage represents the maximum for guaranteed

performance. Figure 5 illustrates configuration for VCC2

= 3.3V, V+ and V– are fixed at 5V and –5V respectively.

Channel Timing Uncertainty

Multiple channels are supported across the isolation bound-

ary by encoding and decoding of the inputs and outputs.

Up to three signals in each direction are assembled as a

packet and transferred across the isolation barrier. The

time required to transfer all 3 bits is 100ns maximum,

and sets the limit for how often a signal can change on

the opposite side of the barrier. Encoding transmission is

independent for each data direction. The technique used

assigns SCK or SCL on the logic side, and SDO2 or I2 on

the isolated side, the highest priority such that there is

no jitter on the associated output channels, only delay.

This preemptive scheme will produce a certain amount of

uncertainty on the other isolation channels. The resulting

pulse width uncertainty on these low priority channels is

typically ±6ns, but may vary up to ±50ns if the low priority

channels are not encoded within the same high priority

serial packet.

Serial Peripheral Interface (SPI) Bus

The LTM2886-S provides a SPI compatible isolated inter-

face. The maximum data rate is a function of the inherent

channel propagation delays, channel to channel pulse

width uncertainty, and data direction requirements. Chan-

nel timing is detailed in Figures 6 through 9 and Tables

2 and 3. The SPI protocol supports four unique timing

configurations defined by the clock polarity (CPOL) and

clock phase (CPHA) summarized in Table 1.

Table 1. SPI Mode

CPOL CPHA DATA TO (CLOCK) RELATIONSHIP

0 0 Sample (Rising) Set-Up (Falling)

0 1 Set-Up (Rising) Sample (Falling)

1 0 Sample (Falling) Set-Up (Rising)

1 1 Set-Up (Falling) Sample (Rising)

The maximum data rate for bidirectional communication

is 4MHz, based on a synchronous system, as detailed in

the timing waveforms. Slightly higher data rates may be

achieved by skewing the clock duty cycle and minimiz-

ing the SDO to SCK set-up time, however the clock rate

is still dominated by the system propagation delays. A

discussion of the critical timing paths relative to Figures 6

and 7 follows.

The output adjustment range for VCC2 is 3V to 5.5V. VCC2

output voltage is calculated by:

VCC2 = 1.22V(1 + R2/R1)

The value of R1 should be no greater than 24.9k to mini-

mize errors in the output voltage caused by the AVCC2 pin

bias current.

Operation at low output voltages may result in thermal

shutdown due to low dropout regulator power dissipation.

42.2k

24.9k

2886 F05

SDOE

CS2

LTM2886-5S

VCC

GND GND2

SDI SDI2

SCK SCK2

V–

AVCC2

V+

VCC2

SDO

DO2

SDO2

DO1 I1

ISOLATION BARRIER

3.3V

–5V

LTM2886 19

LTM2886

2886fb

For more information www.linear.com/LTM2886

• CS to SCK (master sample SDO, 1st SDO valid)

t0 → t1 ≈50ns, CS to CS2 propagation delay

t1 → t1+ Isolated slave device propagation

(response time), asserts SDO2

t1 → t3 ≈50ns, SDO2 to SDO propagation delay

t3 → t5 Set-up time for master SDO to SCK

• SDI to SCK (master data write to slave)

t2 → t4 ≈50ns, SDI to SDI2 propagation delay

t5 → t6 ≈50ns, SCK to SCK2 propagation delay

t2 → t5 ≥50ns, SDI to SCK, separate packet

non-zero set-up time

t4 → t6 ≥50ns, SDI2 to SCK2, separate packet

non-zero set-up time

• SDO to SCK (master sample SDO, subsequent

SDO valid)

t8 set-up data transition SDI and SCK

t8 → t10 ≈50ns, SDI to SDI2 and SCK to SCK2

propagation delay

APPLICATIONS INFORMATION

t10 SDO2 data transition in response to SCK2

t10 → t11 ≈50ns, SDO2 to SDO propagation delay

t11 → t12 Set-up time for master SDO to SCK

Maximum data rate for single direction communication,

master to slave, is 8MHz, limited by the systems encod-

ing/decoding scheme or propagation delay. Timing details

for both variations of clock phase are shown in Figures 8

and 9 and Table 3.

Additional requirements to insure maximum data rate are:

• CS is transmitted prior to (asynchronous) or within

the same (synchronous) data packet as SDI

• SDI and SCK set-up data transition occur within the

same data packet. Referencing Figure 6, SDI can pre-

cede SCK by up to 13ns (t7 → t8) or lag SCK by 3ns

(t8 → t9) and not violate this requirement. Similarly in

Figure 8, SDI can precede SCK by up to 13ns (t4 → t5)

or lag SCK by 3ns (t5 → t6).

LTM2886

2886fb

For more information www.linear.com/LTM2886

Figure 7. SPI Timing, Bidirectional, CPHA = 1

2886 F07

SDO2

SDO

SCK2 (CPOL = 1)

SCK (CPOL = 1)

SCK2 (CPOL = 0)

SCK (CPOL = 0)

SDI2

SDI

CS2

CS = SDOE

CPHA = 1

t0t1t2t3t4t5t6t7t8

t9t10 t11 t12 t13 t14 t15 t16 t17 t18

INVALID

APPLICATIONS INFORMATION

Figure 6. SPI Timing, Bidirectional, CPHA = 0

2886 F06

SDO2

SDO

SCK2 (CPOL = 1)

SCK (CPOL = 1)

SCK2 (CPOL = 0)

SCK (CPOL = 0)

SDI2

SDI

CS2

CS = SDOE

CPHA = 0

t0t1t2t3t4t5t6t7t8

t9t10 t11 t12 t13 t14 t15 t17 t18

INVALID

LTM2886 21

LTM2886

2886fb

For more information www.linear.com/LTM2886

Figure 8. SPI Timing, Unidirectional, CPHA = 0

2886 F08

SCK2 (CPOL = 1)

SCK (CPOL = 1)

SCK2 (CPOL = 0)

SCK (CPOL = 0)

SDI2

SDI

CS2

CS = SDOE

CPHA = 0

t0t1t2t3t4t5t7

t8t11 t12

APPLICATIONS INFORMATION

Figure 9. SPI Timing, Unidirectional, CPHA = 1

2886 F09

SCK2 (CPOL = 1)

SCK (CPOL = 1)

SCK2 (CPOL = 0)

SCK (CPOL = 0)

SDI2

SDI

CS2

CS = SDOE

CPHA = 1

t0t1t2t3t4t5t7

t8t11

t10 t12

LTM2886

2886fb

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Table 2. Bidirectional SPI Timing Event Description

TIME CPHA EVENT DESCRIPTION

t00, 1 Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. Logic side slave data output

enabled, initial data is not equivalent to slave device data output

t0 to t1, t17 to t18 0, 1 Propagation delay chip select, logic to isolated side, 50ns typical

t10, 1 Slave device chip select output data enable

t20 Start of data transmission, data set-up

1 Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge

t1 to t30, 1 Propagation delay of slave data, isolated to logic side, 50ns typical

t30, 1 Slave data output valid, logic side

t2 to t40 Propagation delay of data, logic side to isolated side

1 Propagation delay of data and clock, logic side to isolated side

t50, 1 Logic side data sample time, half clock period delay from data set-up transition

t5 to t60, 1 Propagation delay of clock, logic to isolated side

t60, 1 Isolated side data sample time

t80, 1 Synchronous data and clock transition, logic side

t7 to t80, 1 Data to clock delay, must be ≤13ns

t8 to t90, 1 Clock to data delay, must be ≤3ns

t8 to t10 0, 1 Propagation delay clock and data, logic to isolated side

t10, t14 0, 1 Slave device data transition

t10 to t11, t14 to t15 0, 1 Propagation delay slave data, isolated to logic side

t11 to t12 0, 1 Slave data output to sample clock set-up time

t13 0 Last data and clock transition logic side

1 Last sample clock transition logic side

t13 to t14 0 Propagation delay data and clock, logic to isolated side

1 Propagation delay clock, logic to isolated side

t15 0 Last slave data output transition logic side

1 Last slave data output and data transition, logic side

t15 to t16 1 Propagation delay data, logic to isolated side

t17 0, 1 Asynchronous chip select transition, end of transmission. Disable slave data output logic side

t18 0, 1 Chip select transition isolated side, slave data output disabled

APPLICATIONS INFORMATION

Inter-IC Communication (I2C) Bus

The LTM2886-I provides an I2C compatible isolated in-

terface. Clock (SCL) is unidirectional, supporting master

mode only, and data (SDA) is bidirectional. The maximum

data rate is 400kHz which supports fast-mode I2C. Timing

is detailed in Figure 10. The data rate is limited by the slave

acknowledge setup time (tSU;ACK), consisting of the I2C

standard minimum setup time (tSU;DAT) of 100ns, maximum

clock propagation delay of 225ns, glitch filter and isolated

data delay of 500ns maximum, and the combined isolated

and logic data fall time of 300ns at maximum bus loading.

The total setup time reduces the I2C data hold time (tHD;DAT)

to a maximum of 175ns, guaranteeing sufficient data setup

time (tSU;ACK).

The isolated side bidirectional serial data pin, SDA2,

simplified schematic is shown in Figure 11. An internal

1.8mA current source provides a pull-up for SDA2. Do not

connect any other pull-up device to SDA2. This current

source is sufficient to satisfy the system requirements for

bus capacitances greater than 200pF in FAST mode and

greater than 400pF in STANDARD mode.

LTM2886 _\ 23

LTM2886

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APPLICATIONS INFORMATION

Table 3. Unidirectional SPI Timing Event Description

TIME CPHA EVENT DESCRIPTION

t00, 1 Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns

t0 to t10, 1 Propagation delay chip select, logic to isolated side

t20 Start of data transmission, data set-up

1 Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge

t2 to t30 Propagation delay of data, logic side to isolated side

1 Propagation delay of data and clock, logic side to isolated side

t30, 1 Logic side data sample time, half clock period delay from data set-up transition

t3 to t50, 1 Clock propagation delay, clock and data transition

t4 to t50, 1 Data to clock delay, must be ≤13ns

t5 to t60, 1 Clock to data delay, must be ≤3ns

t5 to t70, 1 Data and clock propagation delay

t80 Last clock and data transition

1 Last clock transition

t8 to t90 Clock and data propagation delay

1 Clock propagation delay

t9 to t10 1 Data propagation delay

t11 0, 1 Asynchronous chip select transition, end of transmission

t12 0, 1 Chip select transition isolated side

Figure 11. Isolated SDA2 Pin Schematic

Figure 10. I2C Timing Diagram

2886 F11

SDA2

1.8mA

FROM

LOGIC

SIDE

LOGIC

SIDE

GLITCH FILTER

2886 F10

SDA

189

SDA2

SCL

SCL2

START tPROP tSU;DAT tHD;DAT tSU;ACK

SLAVE ACK

STOP

Additional proprietary circuitry monitors the slew rate on

the SDA and SDA2 signals to manage directional control

across the isolation barrier. Slew rates on both pins must

be greater than 1V/µs for proper operation.

The logic side bidirectional serial data pin, SDA, requires a

pull-up resistor or current source connected to VL. Follow

the requirements in Figures 12 and 13 for the appropri-

ate pull-up resistor on SDA that satisfies the desired rise

time specifications and VOL maximum limits for FAST and

STANDARD modes. The resistance curves represent the

maximum resistance boundary; any value may be used

to the left of the appropriate curve.

LTM2886 ZZuH Eu 3 ”Fllllxlll

LTM2886

2886fb

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APPLICATIONS INFORMATION

The isolated side clock pin, SCL2, has a weak push-pull

output driver; do not connect an external pull-up device.

SCL2 is compatible with I2C devices without clock stretch-

ing. On lightly loaded connections, a 100pF capacitor

from SCL2 to GND2 or RC lowpass filter (R = 500Ω,

C = 100pF) can be used to increase the rise and fall times

and minimize noise.

Some consideration must be given to signal coupling

between SCL2 and SDA2. Separate these signals on

a printed circuit board or route with ground between.

If these signals are wired off board, twist SCL2 with VCC2

and/or GND2 and SDA2 with GND2 and/or VCC2, do not

twist SCL2 and SDA2 together. If coupling between SCL2

and SDA2 is unavoidable, place the aforementioned RC

filter at the SCL2 pin to reduce noise injection onto SDA2.

Low Noise Applications

For precision analog applications the V+ and V– power

rails may be filtered to improve the noise performance.

Figure 14 shows the recommended component values to

reduce noise at high frequencies. The selected inductor

should be chosen such that the parasitic capacitance is

low enough to keep the self resonant frequency greater

than 10MHz. The plots of Figures 15 and 16 show the high

frequency noise improvement for the V+ rail, the improve-

ment on the V– rail will be nearly equivalent.

Some applications may require the noise performance be

improved in the 100Hz to 10kHz region. An additional LC

filter stage may be added between the LTM2886 and the

high frequency filter to lower the noise corner frequency.

Using an inductance of 330µH and capacitance of 680µF

reduces the noise corner to approximately 340Hz. The

RMS noise at a bandwidth of 340Hz is approximately 22µV.

Figure 12. Maximum Standard Speed Pull-Up Resistance on SDA

Figure 13. Maximum Fast Speed Pull-Up Resistance on SDA

Figure 14. Filtered Voltage Rails for Low Noise Applications

CBUS (pF)

RPULL_UP (kΩ)

0100

2886 F12

1000

VL = 3V

VL = 3.3V

VL = 3.6V

VL = 4.5V TO 5.5V

CBUS (pF)

RPULL_UP (kΩ)

0100

2886 F13

1000

VL = 3V

VL = 3.3V

VL = 3.6V

VL = 4.5V TO 5.5V

CS2

LTM2886-5S

VCC

GND

SDI SDI2

SDOE

SCK

DO2

SCK2

V–

AVCC2

V+

VCC2

SDO SDO2

DO1 I1

GND2

22µH

FILTERED V

–

2886 F15

10µF10µF

22µH

LTM2886 Aggy E29 353 was: SEE mg? >528 358% $5: Eats 25

LTM2886

2886fb

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APPLICATIONS INFORMATION

Figure 15. V+ Output Noise Spectral Density Without Filter

Figure 16. V+ Output Noise Spectral Density With Filter

RF, Magnetic Field Immunity

The isolator µModule technology used within the LTM2886

has been independently evaluated, and successfully passed

the RF and magnetic field immunity testing requirements

per European Standard EN 55024, in accordance with the

following test standards:

EN 61000-4-3 Radiated, Radio-Frequency,

Electromagnetic Field Immunity

EN 61000-4-8 Power Frequency Magnetic Field

Immunity

EN 61000-4-9 Pulsed Magnetic Field Immunity

Tests were performed using an unshielded test card de-

signed per the data sheet PCB layout recommendations.

Specific limits per test are detailed in Table 5.

Table 4. EMC Immunity Tests

TEST FREQUENCY FIELD STRENGTH

EN 61000-4-3 Annex D 80MHz to 1GHz 10V/m

1.4MHz to 2GHz 3V/m

2GHz to 2.7GHz 1V/m

EN 61000-4-8 Level 4 50Hz and 60Hz 30A/m

EN 61000-4-8 Level 5 60Hz 100A/m*

EN 61000-4-9 Level 5 Pulse 1000A/m

*non IEC method

PCB Layout

The high integration of the LTM2886 makes PCB layout

very simple. However, to optimize its electrical isolation

characteristics, EMI, and thermal performance, some

layout considerations are necessary.

• Under heavily loaded conditions VCC and GND current

can exceed 300mA. Sufficient copper must be used

on the PCB to insure resistive losses do not cause the

supply voltage to drop below the minimum allowed

level. Similarly, the VCC2 and GND2 conductors must

be sized to support any external load current. These

heavy copper traces will also help to reduce thermal

stress and improve the thermal conductivity.

• Input and output supply decoupling is not required,

since these components are integrated within the

package. An additional bulk capacitor with a value of

6.8µF to 22µF is recommended. The high ESR of this

capacitor reduces board resonances and minimizes

voltage spikes caused by hot plugging of the supply

voltage. For EMI sensitive applications, an additional

low ESL ceramic capacitor of 1µF to 4.7µF, placed as

close to the power and ground terminals as possible,

is recommended. Alternatively, a number of smaller

value parallel capacitors may be used to reduce ESL

and achieve the same net capacitance.

• Do not place copper on the PCB between the inner

columns of pads. This area must remain open to

withstand the rated isolation voltage.

• The use of solid ground planes for GND and GND2

is recommended for non-EMI critical applications to

optimize signal fidelity, thermal performance, and to

minimize RF emissions due to uncoupled PCB trace

FREQUENCY (kHz)

0.01 0.1 1

OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)

0.1

0.01 10 100 1000

2886 F15

10000

NO LOAD

LOAD = 50Ω

LTM2886-5

FREQUENCY (kHz)

0.01 0.1 1

OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)

0.1

0.01 10 100 1000

2886 F16

10000

LTM2886-5

LOAD = 50Ω

NO LOAD

LTM2886 SPI/DIGITAL 0R 12C DEMO CIRCUIT 17am»- ”MODULE 150mm, LON Em LTMEBBBCY- - ON J1 .‘ W R3 CED 2 RS #3 % I ‘ C1 H5 ‘ I OFF I w : ‘ ‘ R4 H1 H2 LM> .zv-3.sv LeraEsCY—J i i .5v-S.5v LeraEsCY—S ‘33 5‘ INPUT CONNECTOR OUTPUT CONNECTOR LTMEEBEiI LTMEEBEiS Lmeassﬂ LTMEBBE’S ch CND ch CND v7 w v7 w ch CND ch CND vccz CNDz vcce mm on 50;: csa SDI some 01 5012 C523 DNC SCL DOE scx SCLE DNC scxz 12 001 D02 DO1 SDO 12 11 SD02 11 (7Llnw (ma) HEISZE LTC CONFIDENTIQt recwomev ww- \ meat-GUM FOR CUSTOMER USE ONLY

LTM2886

2886fb

For more information www.linear.com/LTM2886

APPLICATIONS INFORMATION

Figure 17. LTM2886 Low EMI Demo Board Layout

conduction. The drawback of using ground planes,

where EMI is of concern, is the creation of a dipole

antenna structure which can radiate differential volt-

ages formed between GND and GND2. If ground planes

are used it is recommended to minimize their area,

and use contiguous planes as any openings or splits

can exacerbate RF emissions.

• For large ground planes a small capacitance (≤330pF)

from GND to GND2, either discrete or embedded

within the substrate, provides a low impedance cur-

rent return path for the module parasitic capacitance,

minimizing any high frequency differential voltages and

substantially reducing radiated emissions. Discrete

capacitance will not be as effective due to parasitic

ESL. In addition, voltage rating, leakage, and clear-

ance must be considered for component selection.

Embedding the capacitance within the PCB substrate

provides a near ideal capacitor and eliminates com-

ponent selection issues; however, the PCB must be

four layers. Care must be exercised in applying either

technique to ensure the voltage rating of the barrier

is not compromised.

• In applications without an embedded PCB substrate

capacitance a slot may be added between the logic

side and isolated side device pins. The slot extends

the creepage path between terminals on the PCB side,

and may reduce leakage caused by PCB contamination.

The slot should be placed in the middle of the device

and extend beyond the package perimeter.

The PCB layout in Figures 17 and 18 shows the low EMI

demo board for the LTM2886. The demo board uses a

combination of EMI mitigation techniques, including both

embedded PCB bridge capacitance and discrete GND to

GND2 capacitors. Two safety rated type Y2 capacitors are

used in series, manufactured by MuRata, part number

GA342QR7GF471KW01L. The embedded capacitor ef-

fectively suppresses emissions above 400MHz, whereas

the discrete capacitors are more effective below 400MHz.

EMI performance is shown in Figure 19, measured using

a Gigahertz Transverse Electromagnetic (GTEM) cell and

method detailed in IEC 61000-4-20, Testing and Measure-

ment Techniques – Emission and Immunity Testing in

ransverse Electromagnetic Waveguides.

LTM2886 . 0006.th 00000 .laooaogmg I00 . . 000.6:0Z .0000 5 v3»: Geese D0003“ 27

LTM2886

2886fb

For more information www.linear.com/LTM2886

Top Layer Inner Layer 2

Inner Layer 1 Bottom Layer

Figure 18. LTM2886 Low EMI Demo Board Layout (DC1790A)

APPLICATIONS INFORMATION

LTM2886

2886fb

For more information www.linear.com/LTM2886

LTM2886-5I

1µF

SCL

µC

SDA

VCC

GND

VREF

LTC2301, ADC

SDA

VDD GND

AD0

AD1

REFC

GND IN–

IN+

GND

SCL

ADC

DAC

3 4

REF

LTC2631A-LM12, DAC

CA0 R_SEL

SCL

SDA

VOUT

GND VCC

0.1µF

1µF

1.7k 1.7k ON

DI1

DNC

VCC

GND

SDA SDA2

GND

SCL

DNC

SCL2

V–

AVCC2

V+

–5V

1.25V

2.5V F.S.

4V F.S.

2.5V

VCC2

DO2 I2

DO1 I1

GND2

–

6±5V

OUT

0.1µF

–5V

0.1µF

–

1/2 LTC2055

LT1991

G = 4

–

1/2 LTC2055

1µF

10µF

0.1µF

0.1µF 5V

RA1, 10k

VISHAY, OSOPTA1002AT1

±5V

2886 F20

–5V

0.1µF

–

LT1218L

Figure 20. Isolated I2C 12-Bit, ±5V Analog Input and Output

TYPICAL APPLICATIONS

APPLICATIONS INFORMATION

Figure 19. LTM2886 Low EMI Demo Board Emissions

FREQUENCY (MHz)

–30

dBµV/m

–20

600 700 800 900

2886 F19

–10

100 200 300 400 500

1000

DETECTOR = QuasiPeak

RBW = 120kHz

VBW = 300kHz

SWEEP TIME = 17s

# OF POINTS = 501

DC1790A-A

DC1790A-B

CISPR 22 CLASS B LIMIT

LTM2886 LTMzaaﬁras 29

LTM2886

2886fb

For more information www.linear.com/LTM2886

TYPICAL APPLICATIONS

Figure 21. Isolated SPI Device Expansion

2886 F21

CS2

LTM2886-3S

VCC

GND

SDI SDI2

SDOE

SCK

DO2

SCK2

V–

AVCC2

V+

VCC2

SDO SDO2

CSA

MOSI

SCK

CSB

MISO

DO1 I1

GND2

74LVC1G123

Rx/Cx Cx

CLR

3.3V

1µF

1nF

µC

CSA

CSB

MISO

VCC

GND

MOSI

SCK

CSA

CSB

MOSI

SCK

10k

Figure 22. Isolated I2C Buffer with Dual Outputs

2886 F22

DI1

DNC

VCC

GND

SDA SDA2

GND

SCL

ENABLE

SDA

SCLIN

ALERT

READY

DNC

SCL2

V–

AVCC2

V+

VCC2

DO2 I2

DO1 I1

GND2

10k

ALERT1

LTC4305

SCLIN

ALERT2

SCL2 SCL2

ALERT

SDAIN

SDA2 SDA2

GND

VCC

ADR0

ENABLE

SDA1 SDA1

SCL1 SCL1

READY

ADR2

ADR1

10k

LTM2886-5I

10k 10k

0.01µF

10k 10k 10k 10k 10k 10k

LTM2886 LTMzaaerss 30

LTM2886

2886fb

For more information www.linear.com/LTM2886

TYPICAL APPLICATIONS

Figure 23. 16-Channel Isolated Temperature to Frequency Converter

2886 F23

CS2

LTM2886-5S

VCC

GND

SDI SDI2

SDOE

SCK

DO2

SCK2

V–

AVCC2

V+

VCC2

SDO SDO2

DO1 I1

GND2

1µF

µC

VCC

GND

DG4051A

NTC THERMISTORS, MURATA NTSD1WD104, 100k

VCC X0

BX3

–t°

GND

ENABLE

VEE X6

SET

LTC1799

OUT V+

DIV

GND

3.01k

SET

LTC1799

TEMPERATURE (°C) FREQUENCY (kHz)

–40

–30

–20

–10

100

110

120

1.23

1.46

1.87

2.58

3.77

5.67

8.64

13.09

19.53

28.47

40.65

55.87

74.45

96.08

119.83

144.73

169.36

OUT V+

DIV

GND

3.01k

–t°

DG4051A

VCC X0

BX3

–t°

GND

ENABLE

VEE X6

–t°

LTM2886 """" \RF7509 I I 31

LTM2886

2886fb

For more information www.linear.com/LTM2886

2886 F24

CS2

LTM2886-5S

VCC

GND

SDI SDI2

SDOE

SCK

DO2

SCK2

V–

AVCC2

V+

VCC2

SDO SDO2

DO1 I1

–5V UV

5V ENABLE

5V UV

–5V ENABLE

SWITCHED 5V

SWITCHED –5V

SWITCHED 5V

5V UV

GND2

LTC2902

CRT

COMP3 COMP2

COMP1

COMP4

V1 V4

VREF

VPG

RDIS

RST

T0 GND

0.1µF

10k

84.5k

9.53k

93.1k

20k

76.8k

100k

IRF7509

IRLML2402

IRF7509

100k

TYPICAL APPLICATIONS

Figure 24. Digitally Switched Triple Power Supply with Undervoltage Monitor

LTM2886

2886fb

For more information www.linear.com/LTM2886

TYPICAL APPLICATIONS

Figure 25. Quad 16-Bit ±5V Output Range DAC

–5V

2886 F25

LTM2886-3S

3.3V

1µF

SCKµC

MOSI

VCC

GND

VOUTC

LTC2654-L16

SDO

CS VOUTA

SDI

SCK

VOUTB

CLR VOUTD

REFLO

VCC REFOUT

LDAC REFC

GND

PORSEL

12 16

0.1µF

CS2

VCC

GND

SDI SDI2

SDOE

SCK

DO2

SCK2

V–

AVCC2

V+

–5V

VCC2

SDO

MISO SDO2

DO1 I1

GND2

–

6±5V OUTA

0.1µF

–5V

0.1µF

LTC2054

6±5V OUTB

0.1µF

–

LT1991

G = 4

–5V

6±5V OUTC

0.1µF

–

LT1991

G = 4

–5V

±5V OUTD

0.1µF

–

LT1991

G = 4

0.1µF

LT1991

G = 4

1.25V

LTM2886 LTMZBBGrﬁ‘ 33

LTM2886

2886fb

For more information www.linear.com/LTM2886

TYPICAL APPLICATIONS

Figure 26. –48V, 200W Hot Swap Controller with Isolated I2C Interface

2886 F26

LTM2886-5I

1µF

SCL

µC SDA

VCC

GND

10k

DI1

DNC

VCC

GND

SDA SDA2

GND

SCL

DNC

SCL2

V–

AVCC2

V+

VCC2

DO2 I2

DO1 I1

GND2 VEE

VEE

VOUT

SDAI

LTC4261CGN

UVL FLTIN

UVH

ADIN2

SCL

OV SDAO

ALERT

TMR

ADR0

PGI

ADR1

24 ADIN

PGI0

PWRGD2

–48V RTN

–48V INPUT

IRF1310NS

PWRGD1

VEE

SENSE

GATE

INTVCC

VIN

DRAIN

RAMP

10nF

100V

0.1µF47nF

100nF 220nF1µF

0.1µF

330µF

100V

16.9k

11.8k

453k 1k, ×4 IN SERIES

1/4W EACH

47nF 10Ω

10k 402k

0.008Ω

10k

LTM2886 LTMZESEH‘

LTM2886

2886fb

For more information www.linear.com/LTM2886

Figure 27. 12-Cell Battery Stack Monitor with Isolated SPI Interface and Low Power Shutdown

TYPICAL APPLICATIONS

CS2

LTM2886-3S

VCC

GND

SDI SDI2

SCK

DO2

SCK2

V–

AVCC2

V+

VCC2

SDO SDO2

DO1 I1

GND2

SCKO

LTC6803-1

VMODE

CSI CSO

SDO

SDI

SDOI

SCKI V+

C12

S12

WDT

GPIO2

GPIO1 C11

S11

1µF

µC

MISO

VCC

GND

3.3V

MOSI

SCK

S10

VREF

TOS

C10

VREG C9

VTEMP2

VTEMP1 S8

V–

C1 S6

S3 C4

1µF

100k

3.3k

3.3k 3.3k 3.3k

SDOE

2886 F27

74LVC3G07

LTM2886-3I

3.3V

1µF

SCL

µC SDA

VCC

GND

10k

DI1

DNC

VCC

GND

SDA SDA2

GND

SCL

DNC

SCL2

V–

AVCC2

V+

VCC2

DO2 I2

DO1 I1

GND2

LTC4151

SHDN

ADIN

SDA

SCL

GND

ADR0

ADR1

48V

SENSE–

SENSE+VIN

VOUT

1.37k

0.02Ω

100k AT 25°C, 1%

VISHAY 2381 6154.104

NADIN IS THE DIGITAL CODE MEASURED

BY THE ADC AT THE ADIN PIN

LN N

ADIN

()

,°=

+−











−−°<

3950

8 965 1000 1

273 40 <<°150 C

2886 F28

Figure 28. Isolated I2C Voltage, Current and Temperature Power Supply Monitor

LTM2886 LTMzaaarsl 35

LTM2886

2886fb

For more information www.linear.com/LTM2886

TYPICAL APPLICATIONS

LTM2886-5I

SHUTDOWN

ENABLE

SDA

SCLIN

INTERRUPT

10k

100k

42.2k

24.9k

DI1

DNC

VCC

GND

SDA SDA2

GND

SCL

DNC

SCL2

V–

AVCC2

V+

VCC2

DO2 I2

DO1 I1

GND2

1/4 LTC4266

PHY

(NETWORK

PHYSICAL

LAYER

CHIP)

RESET

INT

DETECT

BYP

SDAIN

SCL

AD0

AD1

AD2

AD3

SDAOUT

AUTO

SHDN1 VDD

DGND AGND VEE SENSE GATE OUT

Q1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10T

FB1, FB2: TDK MPZ2012S601A

T1: PULSE H609NL OR COILCRAFT ETH1-230LD

2886 F29

1µFSMAJ58A

–48V

0.1µF

0.22µF

0.25Ω

S1B

CMPD3003

FB2

RJ45

CONNECTOR

FB1

•

75Ω 75Ω

10nF 10nF

•

75Ω 75Ω

10nF 10nF

1nF

Figure 29. One Complete Isolated Powered Ethernet Port

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LTM2886

2886fb

For more information www.linear.com/LTM2886

PACKAGE DESCRIPTION

BGA Package

32-Lead (15mm × 11.25mm × 3.42mm)

(Reference LTC DWG # 05-08-1851 Rev D)

5. PRIMARY DATUM -Z- IS SEATING PLANE

6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994

2. ALL DIMENSIONS ARE IN MILLIMETERS

BALL DESIGNATION PER JESD MS-028 AND JEP95

DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,

BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.

THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR

MARKED FEATURE

PACKAGE TOP VIEW

PIN “A1”

CORNER

aaa Z

PACKAGE BOTTOM VIEW

SEE NOTES

SUGGESTED PCB LAYOUT

TOP VIEW

BGA 32 1112 REV D

LTMXXXXXX

µModule

TRAY PIN 1

BEVEL PACKAGE IN TRAY LOADING ORIENTATION

COMPONENT

PIN “A1”

DETAIL A

PIN 1

0.000

0.635

1.905

3.175

4.445

6.350

5.080

0.000

DETAIL A

Øb (32 PLACES)

2 14 35678

DETAIL B

SUBSTRATE

0.27 – 0.37

2.45 – 2.55

// bbb Z

ccc Z

DETAIL B

PACKAGE SIDE VIEW

MOLD

CAP

MX YZddd

MZeee

0.630 ±0.025 Ø 32x

SYMBOL

aaa

bbb

ccc

ddd

eee

MIN

3.22

0.50

2.72

0.60

NOM

3.42

0.60

2.82

0.75

0.63

15.0

11.25

1.27

12.70

8.89

MAX

3.62

0.70

2.92

0.90

0.66

0.15

0.10

0.20

0.30

0.15

NOTES

DIMENSIONS

TOTAL NUMBER OF BALLS: 32

BGA Package

32-Lead (15mm × 11.25mm × 3.42mm)

(Reference LTC DWG # 05-08-1851 Rev D)

SEE NOTES

Please refer to http://www.linear.com/product/LTM2886#packaging for the most recent package drawings.

LTM2886 37

LTM2886

2886fb

For more information www.linear.com/LTM2886

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 03/17 Added UL-CSA File Number 1

B 07/17 Changed MIN limits for tPWU (SPI and I2C)

Changed MAX limits for Power-Up Time

LTM2886 LTMzaaerss 38 L7LJHEN2 \ ﬂag:

LTM2886

2886fb

For more information www.linear.com/LTM2886

 LINEAR TECHNOLOGY CORPORATION 2016

LT 0717 REV B • PRINTED IN USA

www.linear.com/LTM2886

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TYPICAL APPLICATION

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Allows for Parallel Communication Battery Stack Topologies

14-Bit Isolated High Speed Bipolar ADC

CS2

LTM2886-3S

VCC

GND

SDI SDI2

SDOE

SCK

3.3V

DO2

SCK2

V–

AVCC2

V+

VCC2

SDO SDO2

DO1 I1

GND2

10µF 0.1µF 10µF 0.1µF

1µF

µC

MISO

VCC

GND

SCK

2886 TA03

AGND

LTC1417, ADC ±2.048V INPUT RANGE

DGND

BUSY VREF

CONVST

REFC

SHDN ECLK

SCLK

VDD AIN+

VSS AIN–

CLKO

DOUT

+ +

10µF 0.1µF

1µF

Scheda tecnica LTM2886 di Analog Devices Inc.

INFORMAZIONI

GUIDA

CONTATTI

SEGUICI