Scheda tecnica SN74LVC2G240 di Texas Instruments

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Seemechanicaldrawingsfordimensions.
DCTPACKAGE
(TOP VIEW)
DCUPACKAGE
(TOP VIEW)
1VCC
8
1OE
27
1A 2OE
3 6
2Y 1Y
45
GND 2A
3 6 1Y2Y
8
1VCC
1OE
5
GND 42A
272OE
1A
GND 5
42A
361Y2Y
272OE1A
8VCC
1
1OE
YZP PACKAGE
(BOTTOMVIEW)
SN74LVC2G240
www.ti.com
SCES208I –APRIL 1999–REVISED NOVEMBER 2013
Dual Buffer Driver With 3-State Outputs
Check for Samples: SN74LVC2G240
1FEATURES DESCRIPTION
This dual buffer driver is designed for 1.65-V to 5.5-V
2• Available in the Texas Instruments NanoFree™ VCC operation.
Package The SN74LVC2G240 device is designed specifically
• Supports 5-V VCC Operation to improve the performance and density of 3-state
• Inputs Accept Voltages to 5.5 V memory address drivers, clock drivers, and bus-
• Max tpd of 4.6 ns at 3.3 V oriented receivers and transmitters.
• Low Power Consumption, 10-µA Max ICC NanoFree™ package technology is a major
• ±24-mA Output Drive at 3.3 V breakthrough in IC packaging concepts, using the die
as the package.
• Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA= 25°C This device is organized as two 1-bit buffers/drivers
• Typical VOHV (Output VOH Undershoot) with separate output-enable (OE) inputs. When OE is
low, the device passes data from the A input to the Y
>2 V at VCC = 3.3 V, TA= 25°C output. When OE is high, the outputs are in the high-
• Ioff Supports Live Insertion, Partial-Power- impedance state.
Down Mode, and Back-Drive Protection To ensure the high-impedance state during power up
• Can Be Used as a Down Translator to or power down, OE should be tied to VCC through a
Translate Inputs From a Max of 5.5 V Down to pullup resistor; the minimum value of the resistor is
the VCC Level determined by the current-sinking capability of the
• Latch-Up Performance Exceeds 100 mA Per driver.
JESD 78, Class II This device is fully specified for partial-power-down
• ESD Protection Exceeds JESD 22 applications using Ioff. The Ioff circuitry disables the
– 2000-V Human-Body Model (A114-A) outputs, preventing damaging current backflow
through the device when it is powered down.
– 1000-V Charged-Device Model (C101)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
l TEXAS INSTRUMENTS IUE 1A7 V ZUE 2A7 V
1
2
7
53
6
1A 1Y
2A 2Y
1OE
2OE
SN74LVC2G240
SCES208I –APRIL 1999–REVISED NOVEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Function Table
(Each Buffer)
INPUTS OUTPUT
Y
OE A
L H L
L L H
H X Z
Logic Diagram (Positive Logic)
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
VIInput voltage range(2) –0.5 6.5 V
VOVoltage range applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V
VOVoltage range applied to any output in the high or low state(2)(3) –0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
DCT package 220
θJA Package thermal impedance(4) DCU package 227 °C/W
YZP package 102
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G240
l TEXAS INSTRUMENTS
SN74LVC2G240
www.ti.com
SCES208I –APRIL 1999–REVISED NOVEMBER 2013
Recommended Operating Conditions(1)
MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VIInput voltage 0 5.5 V
High or low state 0 VCC
VOOutput voltage V
3-state 0 5.5
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V –24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V 24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
Δt/Δv Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 5
TAOperating free-air temperature –40 125 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: SN74LVC2G240
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SN74LVC2G240
SCES208I –APRIL 1999–REVISED NOVEMBER 2013
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
–40°C to 85°C –40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP(1) MAX MIN TYP(1) MAX
1.65 V
IOH = –100 µA to VCC – 0.1 VCC – 0.1
5.5 V
IOH = –4 mA 1.65 V 1.2 1.2
VOH V
IOH = –8 mA 2.3 V 1.9 1.9
IOH = –16 mA 2.4 2.4
3 V
IOH = –24 mA 2.3 2.3
IOH = –32 mA 4.5 V 3.8 3.8
1.65 V
IOL = 100 µA to 0.1 0.1
5.5 V
IOL = 4 mA 1.65 V 0.45 0.45
VOL V
IOL = 8 mA 2.3 V 0.3 0.3
IOL = 16 mA 0.4 0.4
3 V
IOL = 24 mA 0.55 0.55
IOL = 32 mA 4.5 V 0.55 0.75
A or OE 0 to
IIVI= 5.5 V or GND ±5 ±5 µA
inputs 5.5 V
Ioff VIor VO= 5.5 V 0 ±10 ±10 µA
IOZ VO= 0 to 5.5 V 3.6 V 10 10 µA
1.65 V
ICC VI= 5.5 V or GND, IO= 0 to 10 10 µA
5.5 V
One input at VCC – 0.6 3 V to
ΔICC Other inputs at VCC or GND 500 500 µA
V, 5.5 V
CiVI= VCC or GND 3.3 V 4 pF
CoVO= VCC or GND 3.3 V 6 pF
(1) All typical values are at VCC = 3.3 V, TA= 25°C.
4Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G240
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SN74LVC2G240
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SCES208I –APRIL 1999–REVISED NOVEMBER 2013
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC2G240
–40°C to 85°C
FROM TO
PARAMETER VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 2.0 11.3 1.4 5.5 1.1 4.6 1.0 4.0 ns
ten OE Y 2.7 11.7 1.9 6.6 1.4 5.4 1.1 5.0 ns
tdis OE Y 1.7 12.8 0.8 5.7 1.2 5.5 0.5 4.2 ns
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC2G240
–40°C to 85°C
FROM TO
PARAMETER VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 2.0 13.7 1.4 6.8 1.1 5.8 1.0 5.0 ns
ten OE Y 2.7 14.3 1.9 8.0 1.4 6.6 1.1 6.0 ns
tdis OE Y 1.7 15.3 0.8 7.5 1.2 6.8 0.5 5.4 ns
Operating Characteristics
TA= 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
TEST
PARAMETER UNIT
CONDITIONS TYP TYP TYP TYP
Power dissipation Outputs enabled 15 17
Cpd capacitance f = 10 MHz pF
Outputs disabled 1 1 2 3
per buffer driver
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: SN74LVC2G240
‘5‘ TEXAS INSTRUMENTS A 3 I fl 3+3 3.133 3.1 W33 *3 31 3m
th
tsu
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
VLOAD
Open
GND
RL
DataInput
TimingInput
0V
0V
0V
tW
Input
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Output
TEST S1
t /t
PLH PHL Open
Output
Control
VM
VMVM
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
1kW
500 W
500 W
500 W
VCC RL
2× VCC
2× VCC
6V
2× VCC
VLOAD CL
30pF
30pF
50pF
50pF
0.15V
0.15V
0.3V
0.3V
VD
3V
VI
VCC/2
VCC/2
1.5V
VCC/2
VM
£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
RL
t /t
r f
VCC
VCC
VCC
VLOAD
t /t
PLZ PZL
GND
t /t
PHZ PZH
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGEWAVEFORMS
PULSEDURATION
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VI
VI
VI
VM
VM
V /2
LOAD
tPZL tPLZ
tPHZ
tPZH
V – V
OH D
V +V
OL D
VM
VMVM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLH
tPHL
SN74LVC2G240
SCES208I –APRIL 1999–REVISED NOVEMBER 2013
www.ti.com
Parameter Measurement Information
Figure 1. Load Circuit and Voltage Waveforms
6Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G240
l TEXAS INSTRUMENTS
SN74LVC2G240
www.ti.com
SCES208I –APRIL 1999–REVISED NOVEMBER 2013
REVISION HISTORY
Changes from Revision H (February 2007) to Revision I Page
• Updated document to new TI data sheet format. ................................................................................................................. 1
• Removed ordering information. ............................................................................................................................................ 1
• Updated Features. ................................................................................................................................................................ 1
• Added ESD warning. ............................................................................................................................................................ 2
• Updated operating temperature range. ................................................................................................................................. 3
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: SN74LVC2G240
I TEXAS INSTRUMENTS mp mP mum if? mP Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
74LVC2G240DCURG4 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C40R
SN74LVC2G240DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C40
(R, Z)
SN74LVC2G240DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C40J, C40Q, C40R)
SN74LVC2G240YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 (CK7, CKN)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter AD Dimension designed to accommodate the component Width Bo Dimension deSigned to accommodate the component iengtn K0 Dimension designed to accommodate the component thickness 7 w OveraH Wiotn ot the carrier tape i P1 Pitch between successive cawty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprocketHotes ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrants
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
74LVC2G240DCURG4 VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74LVC2G240DCTR SM8 DCT 8 3000 177.8 12.4 3.45 4.4 1.45 4.0 12.0 Q3
SN74LVC2G240DCTR SM8 DCT 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 Q3
SN74LVC2G240DCUR VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74LVC2G240DCUR VSSOP DCU 8 3000 178.0 9.0 2.25 3.35 1.05 4.0 8.0 Q3
SN74LVC2G240DCUR VSSOP DCU 8 3000 178.0 9.5 2.25 3.35 1.05 4.0 8.0 Q3
SN74LVC2G240YZPR DSBGA YZP 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 27-May-2021
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
74LVC2G240DCURG4 VSSOP DCU 8 3000 202.0 201.0 28.0
SN74LVC2G240DCTR SM8 DCT 8 3000 183.0 183.0 20.0
SN74LVC2G240DCTR SM8 DCT 8 3000 182.0 182.0 20.0
SN74LVC2G240DCUR VSSOP DCU 8 3000 202.0 201.0 28.0
SN74LVC2G240DCUR VSSOP DCU 8 3000 180.0 180.0 18.0
SN74LVC2G240DCUR VSSOP DCU 8 3000 202.0 201.0 28.0
SN74LVC2G240YZPR DSBGA YZP 8 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 27-May-2021
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
4.25
3.75 TYP
1.3
1.0
6X 0.65
8X 0.30
0.15
2X
1.95
(0.15) TYP
0 - 8 0.1
0.0
0.25
GAGE PLANE
0.6
0.2
A
3.15
2.75
NOTE 3
B2.9
2.7
NOTE 4
4220784/C 06/2021
SSOP - 1.3 mm max heightDCT0008A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
18
0.13 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 3.500
J
www.ti.com
EXAMPLE BOARD LAYOUT
(3.8)
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
8X (1.1)
8X (0.4)
6X (0.65)
(R0.05)
TYP
4220784/C 06/2021
SSOP - 1.3 mm max heightDCT0008A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
1
45
8
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(3.8)
6X (0.65)
8X (0.4)
8X (1.1)
4220784/C 06/2021
SSOP - 1.3 mm max heightDCT0008A
SMALL OUTLINE PACKAGE
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
MECHANICAL DATA DCU (R—PDSO—GB) PLASTIC SMALL—OUTLINE PACKAGE (DIE DOWN) F Wngiw 31117 0,15 \0M 7 7,40 310 2,20 3,00 i Gage Pm J i 3W1 / __'—_“ NDEX AREA 1 99 Do $1212]: : Q% J L W 4200503” z7/05 NOTES, A AH Hnec' dimensmrs in m'hmekers B Tris drawing is sum 0 Change mm: malice, 0 Body dimCHSiOnS do mi inciudc mom flash or oromsm Moid tics» and pvctrusmn srai not cxcccd o it) 30V m D FuHs wiwu JEDEC M0457 vuiiuliovi CA ‘4‘ TEXAS INSTRUMENTS www.(i. com
LAND PATTERN DATA DCU (S—PDSO—G8) PLASTIC SMALL OUTLINE PACKAGE (DH-Z DOWN) Example Board Layout (Nate 0,5) l ihi' 6x 0,5 I 3,1 ( 8% ‘\ / + 0,3 Exampie /Soider Mask Opening \ Pad Geometry Exampie Stencii Design (Nate D) 8x 0,25 —‘ |——‘ Er Eflfii- Bx 0,75 7 ‘|———'- 6x 0,5 HHH%- meow/c 04/12 NOTES: Au Pom .m Ali iinear dimensions are in miiiimeters‘ This drawing is subject to change without notice. Publication iPC—735I is recommended for aiternate designs. Laser cutting aperture5 with trupezoidai wails and also rounding corners wiil ciier better paste reiease. Customers should Contact their haard assembly site for stencii design recommendations. Refer to iFC—7525 for other slencii recommendations. Custamers shauid Contact their board fabrication site for saider mask toierances between and around signai pads. {I} Tums INSTRUMENTS www.li.com
WT
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PACKAGE OUTLINE
C
0.5 MAX
0.19
0.15
1.5
TYP
0.5 TYP
8X 0.25
0.21
0.5
TYP
B E A
D
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
BALL A1
CORNER
SEATING PLANE
BALL TYP 0.05 C
B
1 2
0.015 C A B
SYMM
SYMM
C
A
D
SCALE 8.000
D: Max =
E: Max =
1.919 mm, Min =
0.918 mm, Min =
1.858 mm
0.857 mm
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EXAMPLE BOARD LAYOUT
8X ( 0.23) (0.5) TYP
(0.5) TYP
( 0.23)
METAL
0.05 MAX ( 0.23)
SOLDER MASK
OPENING
0.05 MIN
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
12
A
B
C
D
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
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EXAMPLE STENCIL DESIGN
(0.5)
TYP
(0.5) TYP
8X ( 0.25) (R0.05) TYP
METAL
TYP
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
12
A
B
C
D
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