Scheda tecnica TPS53126 di Texas Instruments

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SW1
DRVL1
DRVH1
VBST1
EN1
VFB2
VO2
VO1
VFB1
GND
TRIP2
VREG5
TRIP1
PGND1
3
24
8
21
22
23
15
9 16
18
19
20
5
7
1
10
11
VIN
TEST2
DRVH2
VBST2
EN2 PGND2
DRVL2
SW2 13
14
12
V5FILT
17
TEST1
6
2
4PGND
PGND
SGND
PGND
SGND
Input Voltage
4.5V to 24V
R1
13kW
R2
10kW
R5
10kW
R4
3.52kW
VO1
1.8V/4A
C2
0.1 Fm
Q1
FDS8878 C3
10 Fm
C1
22 F 4m ´
C4
22 F 4m ´
Q2
FDS8690
R3
3.3kW
L1
SPM6530T
1.5 Hm
C7
4.7 Fm
C8
1 Fm
C9
10 Fm
R6
4.3kW
Q4
FDS8690
C6
10 Fm
VO2
1.05V/4A
C5
0.1 FmQ3
FDS8878
L2
SPM6530T
1.5 Hm
TPS53126
PW
(TSSOP)
DRVH2
VBST2
EN2
SW1
DRVL1
DRVH1
VBST1
EN1
VFB2
VO2
VO1
VFB1
GND
PGND2 PGND1
DRVL2
SW2
Input Voltage
PGND
PGND
PGND
SGND
24
22
23
19
20
21
13 14 15 16 17 18
8
9
10
11
12
7
12
3
4
5
6
PGND
SGND
TEST1
TEST2
TRIP2
V5FI LT
VREG5
VIN
TRI P1
4.5V to 24V C9
10 Fm
C4
22 F 4m ´
C1
22 F 4m ´
VO2
1.05V/4A
C6
10 Fm
Q3
FDS8878
L2
SPM6530T
1.5 Hm
Q4
FDS8690
C5
0.1 Fm
R4
3.52kW
R5
10kW
R2
10kW
R1
13kW
R6
3.3kWC8
1 Fm
C7
4.7 Fm
R3
4.7kW
VO1
1.8V/4A
C3
10 Fm
Q1
FDS8878
L1
SPM6530T
1.5 Hm
Q2
FDS8690
C2
0.1 Fm
PowerPAD
TPS53126
RGE
(QFN)
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TPS53126
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TPS53126 Dual Synchronous Step-down Controller For Low Voltage Power Rails
1 Features 3 Description
The TPS53126 is a dual, adaptive on-time, D-
1• D-CAP2™ Mode Control CAP2™ mode synchronous Buck controller. The
– Fast Transient Response TPS53126 enables system designers to complete the
– No External Parts Required For Loop suite of various end equipment's power bus
Compensation regulators with a cost effective, low external
component count, and low standby current solution.
– Compatible with Ceramic Output Capacitors The main control loop for the TPS53126 uses the D-
• High Initial Reference Accuracy (±1%) CAP2™ mode control which provides a very fast
• Low Output Ripple transient response with no external components. The
TPS53126 also has a proprietary circuit that enables
• Wide Input Voltage Range: 4.5 V to 24 V the device to adapt to both low equivalent series
• Output Voltage Range: 0.76 V to 5.5 V resistance (ESR) output capacitors, such as
• Low-Side RDS(on) Loss-Less Current Sensing POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors. The device provides convenient and
• Adaptive Gate Drivers with Integrated Boost Diode efficient operation with input voltages from 4.5 V to 24
• Internal 1.2 ms Voltage-Servo Soft Start V and output voltages from 0.76 V to 5.5 V.
• Pre-Biased Soft Start The TPS53126 is available in 4mm x 4mm 24 pin
• Selectable Switching Frequency: 350 kHz / 700 VQFN (RGE) or 24 pin TSSOP (PW) packages and is
kHz specified from –40°C to 85°C ambient temperature
• Cycle-by-Cycle Over-Current Limiting Control range.
• 30 mV to 300 mV OCP Threshold Voltage Device Information(1)
• Thermally Compensated OCP by 4000 ppm/C° at PART NUMBER PACKAGE BODY SIZE (NOM)
ITRIP TPS53126 VQFN (24) 4.00 mm x 4.00 mm
TPS53126 TSSOP (24) 7.80 mm x 4.40 mm
2 Applications
(1) For all available packages, see the orderable addendum at
• Point-of-Load Regulation in Low Power Systems the end of the datasheet.
for Wide Range of Applications
– Digital TV Power Supply
– Networking Home Terminal
– Digital Set Top Box (STB)
– DVD Player/Recorder
– Gaming Consoles and Other
4 Simplified Schematics
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
8.2 Functional Block Diagram....................................... 10
1 Features.................................................................. 18.3 Feature Description................................................. 11
2 Applications ........................................................... 18.4 Device Functional Modes........................................ 13
3 Description ............................................................. 19 Application and Implementation ........................ 14
4 Simplified Schematics........................................... 19.1 Application Information............................................ 14
5 Revision History..................................................... 29.2 350 kHz Operation Application .............................. 14
6 Pin Configurations and Functions....................... 39.3 700 Khz Operation Application ............................... 19
7 Specifications......................................................... 410 Power Supply Recommendations ..................... 21
7.1 Absolute Maximum Ratings ...................................... 411 Layout................................................................... 21
7.2 Handling Ratings....................................................... 411.1 Layout Guidelines ................................................. 21
7.3 Recommended Operating Conditions...................... 411.2 Layout Example .................................................... 21
7.4 Thermal Information.................................................. 512 Device and Documentation Support ................. 23
7.5 Electrical Characteristics.......................................... 512.1 Trademarks........................................................... 23
7.6 Timing Requirements................................................ 612.2 Electrostatic Discharge Caution............................ 23
7.7 Switching Characteristics.......................................... 612.3 Glossary................................................................ 23
7.8 Typical Characteristics.............................................. 713 Mechanical, Packaging, and Orderable
8 Detailed Description............................................ 10 Information ........................................................... 23
8.1 Overview ................................................................. 10
5 Revision History
Changes from Revision A (July 2013) to Revision B Page
• Changed the datasheet to the new TI standard format ......................................................................................................... 1
• Replaced QFN and TSSOP schematics ............................................................................................................................... 1
• Changed VVREG5 MIN from 4.8 V to 4.6 V ............................................................................................................................. 5
• Changed RDRVL Source, IDRVLx = –100 mA MAX from 8 Ωto 12 Ω........................................................................................ 5
• Added Design Parameter and Detailed Design Procedure sections ................................................................................... 19
Changes from Original (May 2009) to Revision A Page
• Changed Equation 1............................................................................................................................................................. 12
• Changed Equation 13........................................................................................................................................................... 16
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*9 TEXAS INSTRUMENTS 5201 Hu E>mo H U mmnmn \\\\\\\\\ n
TRIP1
VIN
VO1
VFB1
GND
TEST1
VREG5
V5FILT
TEST2
TRIP2
VFB2
VO2
EN1
VBST1
DRVH1
SW1
DRVL1
PGND1
EN2
VBST2
DRVH2
SW2
DRVL2
PGND2
15
14
13
24
23
22
21
20
19
1
2
3
4
5
7
8
9
10
11
12
18
17
16
6
1
2
3
4
5
6
7
11
8
12
9
10
24
23
22
21
20
19
18
14
17
13
16
15
VBST1
EN1
VO1
VFB1
GND
TEST1
VFB2
VO2
EN2
VBST2
DRVH1 SW1
DRVL1
PGND1
TRIP1
VIN
VREG5
V5FILT
TEST2
TRIP2
PGND2
DRVL2
SW2
DRVH2
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6 Pin Configurations and Functions
24 Pin VQFN 24 Pin TSSOP
RGE Package PW Package
(Top View) (Top View)
Pin Functions
PIN
I/O DESCRIPTION
VQFN 24 TSSOP 24
NAME NUMBER NUMBER
Supply input for high-side NFET driver (Boost Terminal). Bypass to SWx with a high-
VBST1, 23, 8 2, 11 I quality 0.1μF ceramic capacitor. An external schottky diode can be added if forward drop
VBST2 is critical to drive the high-side FET.
EN1, EN2 24, 7 3, 10 I Channel 1 and channel 2 high level enable pins.
Output voltage inputs for on-time adjustment and output discharge. Connect directly to the
VO1, VO2 1, 6 4, 9 I output voltage.
VFB1, 2, 5 5, 8 I D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
VFB2
GND 3 6 I Signal ground pin. Connect to PGND1, PGND2 and system ground at a single point.
DRVH1, High-side MOSFET gate driver outputs. SWx referenced drivers switch between SWx
22, 9 1, 12 O
DRVH2 (OFF) and VBSTx (ON).
SW1, SW2 21, 10 24, 13 I/O Switch node connections for both the high-side drivers and the current comparators.
DRVL1, Low-side MOSFET gate driver outputs. PGND referenced drivers switch between PGNDx
20, 11 23, 14 O
DRVL2 (OFF) and VREG5 (ON).
PGND1, Power ground connections for both the low-side drivers and the current comparators.
19, 12 22, 15 I/O
PGND2 Connect PGND1, PGND2 and GND strongly together near the IC.
TRIP1, Over current trip point programming pin. Connect to GND with a resistor to GND to set
18, 13 21, 16 I
TRIP2 threshold for low-side RDS(on) current limit.
VIN 17 20 I Supply Input for 5V linear regulator.
5V supply input for the entire control circuit except the MOSFET drivers. Bypass to GND
V5FILT 15 18 I with a minimum 1.0μF, high-quality ceramic capacitor. V5FILT is connected to VREG5 via
an internal 10Ωresistor.
Output of 5V linear regulator and supply for MOSFET drivers. Bypass to GND with a
VREG5 16 19 O minimum 4.7μF high-quality ceramic capacitor. VREG5 is connected to V5FILT via an
internal 10Ωresistor.
TEST1 4 7 O Test interface pin, not used during application. Connect directly to GND.
Frequency select pin. Connect to GND for 350kHz switching. Connect to V5FILT for
TEST2 14 17 I 700kHz switching.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN, EN1, EN2 –0.3 26
VBST1, VBST2 –0.3 32
VBST1, VBST2 (wrt SWx) –0.3 6
Input voltage V
V5FILT, VFB1, VFB2, TRIP1, TRIP2, VO1, VO2, TEST1, –0.3 6
TEST2
SW1, SW2 –2 26
DRVH1, DRVH2 –1 32
DRVH1, DRVH2 (wrt SWx) –0.3 6
Output voltage V
DRVL1, DRVL2, VREG5 –0.3 6
PGND1, PGND2 –0.3 0.3
TAOperating ambient temperature range –40 85 °C
TJJunction temperature range –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
MIN MAX UNIT
Tstg Storage temperature range –55 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all –2000 2000
pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification –500 500
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN MAX UNIT
VIN 4.5 24
Supply input voltage range V
V5FILT 4.5 5.5
VBST1, VBST2 –0.1 30
VBST1, VBST2 (wrt SWx) –0.1 5.5
VFB1, VFB2, VO1, VO2, TEST1, TEST2 –0.1 5.5
Input voltage range V
TRIP1, TRIP2 –0.1 0.3
EN1, EN2 –0.1 24
SW1, SW2 –1.8 24
DRVH1, DRVH2 –0.1 30
VBST1, VBST2 (wrt SWx) –0.1 5.5
Output voltage range V
DRVL1, DRVL2, VREG5 –0.1 5.5
PGND1, PGND2 –0.1 0.1
TAOperating free-air temperature –40 85 °C
TJOperating junction temperature –40 125 °C
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7.4 Thermal Information
TPS53126
THERMAL METRIC(1) UNIT
PW (24 PINS) RGE( 24 PINS)
RθJA Junction-to-ambient thermal resistance 88.9 35.4
RθJC(top) Junction-to-case (top) thermal resistance 26.5 39.1
RθJB Junction-to-board thermal resistance 43.5 13.6 °C/W
ψJT Junction-to-top characterization parameter 1.1 0.5
ψJB Junction-to-board characterization parameter 43.0 13.6
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 3.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over recommended free-air temperature range, VIN = 12 V (Unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN current, TA= 25°C, VREG5 tied to V5FLT, EN1 =
IIN VIN supply current 450 800 μA
EN2 = 5V, VFB1 = VFB2 = 0.8V, SW1 = SW2 = 0.5V
VIN current, TA= 25°C, No load, EN1 = EN2 = 0 V,
IVINSDN VIN shutdown current 30 60 μA
VREG5 = ON
VFB VOLTAGE and DISCHARGE RESISTANCE
Bandgap initial regulation
VBG TA= 25°C -1.0% 1.0%
accuracy
TA= 25°C, TEST2 = 0 V, SWinj = OFF 755 765 775
VVFBTHLx VFBx threshold voltage mV
TA= –40°C to 85°C, TEST2 = 0 V, SWinj = OFF(1) 752 778
TA= 25°C, TEST2 = V5FILT, SWinj = OFF 748 758 768
VVFBTHHx VFBx threshold voltage mV
TA= –40°C to 85°C, TEST2 = V5FILT, SWinj = OFF(1) 745 771
IVFB VFB input current VFBx = 0.8 V, TA= 25°C –0.01 ±0.1 μA
RDischg VO discharge resistance ENx = 0 V, VOx = 0.5 V, TA= 25°C 40 80 Ω
VREG5 OUTPUT
TA= 25°C, 5.5 V < VIN < 24 V,
VVREG5 VREG5 output voltage 4.6 5.0 5.2 V
0 < IVREG5 < 10 mA
VLN5 Line regulation 5.5 V < VIN < 24 V, IVREG5 = 10 mA 20 mV
VLD5 Load regulation 1 mA < IVREG5 < 10 mA 40 mV
IVREG5 Output current VIN = 5.5 V, VVREG5 = 4 V, TA= 25°C 170 mA
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
Source, IDRVHx = –100 mA 5.5 11
RDRVH DRVH resistance Ω
Sink, IDRVHx = 100 mA 2.5 5
Source, IDRVLx = –100 mA 4 12
RDRVL DRVL resistance Ω
Sink, IDRVLx = 100 mA 2 4
INTERNAL BOOST DIODE
VFBST Forward voltage VVREG5-VBSTx, IF= 10 mA, TA= 25°C 0.7 0.8 0.9 V
IVBSTLK VBST leakage current VBSTx = 29 V, SWx = 24 V, TA= 25°C 0.1 1 μA
SOFT START
Tss Internal SS time Internal soft start VFBx = 0.735 V 0.85 1.2 1.4 ms
UVLO
Wake up 3.7 4.0 4.3
VUV5VFILT V5FILT UVLO threshold V
Hysteresis 0.2 0.3 0.4
(1) Ensured by design. Not production tested.
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Electrical Characteristics (continued)
over recommended free-air temperature range, VIN = 12 V (Unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC THRESHOLD
VENH ENx H-level input voltage EN ½ 2.0 V
VENL ENx L-level input voltage EN ½ 0.3 V
CURRENT SENSE
ITRIP TRIP source current VTRIPx = 0.1 V, TA= 25°C 8.5 10 11.5 μA
TCITRIP ITRIP temperature coefficient On the basis of 25°C(2) 4000 ppm/°C
(VTRIPx-GND-VPGNDx-SWx) voltage, –15 0 15
VTRIPx-GND = 60 mV, TA= 25°C
VOCLoff OCP compensation offset mV
(VTRIPx-GND-VPGNDx-SWx) voltage, –20 20
VTRIPx-GND = 60 mV
Current limit threshold setting
VRtrip VTRIPx-GND voltage 30 300 mV
range
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP Output OVP trip threshold OVP detect 110% 115% 120%
UVP detect 65% 70% 75%
VUVP Output UVP trip threshold Hysteresis (recovery < 20 μs) 10%
THERMAL SHUTDOWN
Shutdown temperature(2) 150
TSDN Thermal shutdown threshold °C
Hysteresis(2) 20
(2) Ensured by design. Not production tested.
7.6 Timing Requirements
TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
DRVHx-low to DRVLx-on 20 50 80
tDDead time ns
DRVLx-low to DRVHx-on 20 40 80
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
tOVPDEL Output OVP prop delay time 1.5 μs
tUVPDEL Output UVP delay time 17 30 40 μs
tUVPEN Output UVP enable delay time UVP enable delay 1.2 2 2.5 ms
7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ON-TIME TIMER CONTROL
tON1L CH1 on time SW1 = 12 V, VO1 = 1.8 V, TEST2 = 0 V 490 ns
tON2L CH2 on time SW2 = 12 V, VO2 = 1.8 V, TEST2 = 0 V 390 ns
tOFF1L CH1 min off time SW1 = 0.7 V, TA= 25°C, VFB1 = 0.7 V, TEST2 = 0 V 285 ns
tOFF2L CH2 min off time SW2 = 0.7 V, TA= 25°C, VFB2 = 0.7 V, TEST2 = 0 V 285 ns
tON1H CH1 on time SW1 = 12 V, VO1 = 1.8 V, TEST2 = V5FILT 165 ns
tON2H CH2 on time SW2 = 12 V, VO2 = 1.8 V, TEST2 = V5FILT 140 ns
SW1 = 0.7 V, TA= 25°C, VFB1 = 0.7 V, TEST2 =
tOFF1H CH1 min off time 216 ns
V5FILT
SW2 = 0.7 V, TA= 25°C, VFB2 = 0.7 V, TEST2 =
tOFF2H CH2 min off time 216 ns
V5FILT
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TJ − Junction Temperature − °C
0
100
200
300
400
500
600
700
800
−50 0 50 100 150
IVIN − VIN Supply Current − µA
G001
TPS53126
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SLUS909B –MAY 2009–REVISED AUGUST 2014
7.8 Typical Characteristics
Figure 1. VIN Supply Current vs Junction Temperature Figure 2. VIN Shutdown Current vs Junction Temperature
Figure 3. Trip Source Current vs Junction Temperature Figure 4. VREG5 Voltage vs Junction Temperature
CH1 = 1.8 V, IO= 4 A
Figure 5. VREG5 Voltage vs Input Voltage Figure 6. VFB1 Voltage vs Junction Temperature
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VIN − Input Voltage − V
0.750
0.755
0.760
0.765
0.770
0.775
0.780
0.785
0.790
0.795
0.800
0 5 10 15 20 25
VVFB2 − VFB2 Voltage − V
G011
VO2 = 1.05V
TEST2 = GND
TJ − Junction Temperature − °C
0.750
0.755
0.760
0.765
0.770
0.775
0.780
0.785
0.790
0.795
0.800
−50 0 50 100 150
VVFB2 − VFB2 Voltage − V
G007
IOUT = 4A
VO2 = 1.05V
TEST2 = GND
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Typical Characteristics (continued)
CH2 = 1.05 V, IO= 4 A CH1 = 1.8 V, IO= 4 A
Figure 7. VFB2 Voltage vs Junction Temperature Figure 8. VFB1 Voltage vs Junction Temperature
CH2 = 1.05 V, IO= 4 A CH1 = 1.8 V
Figure 9. VFB2 Voltage vs Junction Temperature Figure 10. VFB1 Voltage vs Input Voltage
CH2 = 1.05 V CH1 = 1.8 V
Figure 11. VFB2 Voltage vs Input Voltage Figure 12. VFB1 Voltage vs Input Voltage
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Typical Characteristics (continued)
CH2 = 1.05 V
Figure 13. VFB2 Voltage vs Input Voltage
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4V/3.7V
V5FILT
VO1
VBST1
DRVH1
SW1
DRVL1
PGND1
Switcher Controller
Fault
Ref
Sdn
ON1
BGR
EN/SS Control
Fault
Ref
Sdn
ON2
Switcher Controller
TRIP1
TRIP2
VFB1
VFB2
TEST1
EN1
EN2
GND
TEST2
VREG5
TSD
VO2
VBST2
DRVH2
SW2
DRVL2
PGND2
TPS53126
SLUS909B –MAY 2009–REVISED AUGUST 2014
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8 Detailed Description
8.1 Overview
The TPS53126 is a dual, adaptive on-time, D-CAP2™ mode synchronous Buck controller. The TPS53126
enables system designers to complete the suite of various end equipment's power bus regulators with a cost
effective, low external component count, and low standby current solution. The main control loop for the
TPS53126 uses the D-CAP2™ mode control which provides a very fast transient response with no external
components. The TPS53126 also has a proprietary circuit that enables the device to adapt to both low equivalent
series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors.
The device provides convenient and efficient operation with input voltages from 4.5 V to 24 V and output
voltages from 0.76 V to 5.5 V.
8.2 Functional Block Diagram
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fiat/Mfg: : : fi> i
V5FILT
GND
Ref
VFBx
TRIPx
VOx
–30%
15%
SSx ERR
COMP
GND
LL
PGNDx
LL
PGNDx ENx
XCON
UV
OV
V5OK
VREG5
VBSTx
DRVHx
SWx
VREG5
DRVLx
PGNDx
LLx
VOx
Fault
Sdn
OCP
1 Shot
Control Logic
On/Off Time
Minimun On/Off
OVP/UVP,
Discharge
Control
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Functional Block Diagram (continued)
8.3 Feature Description
8.3.1 PWM Operation
The main control loop of the TPS53126 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2 mode control. D-CAP2 Mode control combines constant on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot timer is set by the converter input voltage ,VIN, and the output voltage ,VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the
need for ESR induced output ripple from D-CAP mode control.
8.3.2 Drivers
Each SMPS of the TPS53126 contains 2 high-current resistive MOSFET drivers. The Low-side driver is a ground
referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET
whose source is connected to PGND. The High-side Driver is a floating SW referenced VBST powered driver
designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET. To maintain the BST voltage during
the high-side driver ON time, a capacitor is placed from SW to VBST. Each driver draws average current equal to
Gate Charge (Qg AT Vgs = 5V) times Switching Frequency (fsw).
To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF
between each driver transition. During this time the inductor current is carried by one of the MOSFETs body
diodes.
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l TEXAS INSTRUMENTS
trip
trip
trip
V (mV)
R (k ) = I ( A)
Wm
x
x
xfsw
xRDS(on)
Vtrip IOCL 2
L1
VIN VOVO
VIN
=
TPS53126
SLUS909B –MAY 2009–REVISED AUGUST 2014
www.ti.com
Feature Description (continued)
8.3.3 PWM Frequency And Adaptive On-time Control
The TPS53126 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS53126 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time
one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage,
therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
8.3.4 5 Volt Regulator
The TPS53126 has an internal 5V Low-Dropout (LDO) Regulator to provide a regulated voltage for all four
drivers and the ICs internal logic. A capacitor from VREG5 to GND is required to stabilize the internal regular. An
internal 10Ωresistor from VREG5 filters the regulator output to the IC’s analog and logic input voltage, V5FILT.
An additional capacitor is required from V5FILT to GND to filter switching noise from VREG5.
8.3.5 Soft Start
The TPS53126 has an internal, 1.2ms, voltage servo soft-start for each channel. When the ENx pin becomes
high, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the
output voltage is maintained during start up. As the TPS53126 shares one DAC with both channels, if ENx pin is
set to high while another channel is starting up, soft start is postponed until another channel soft start has
completed. If both of EN1 and EN2 are set high at a same time, both channels start up at same time.
8.3.6 Pre-Bias Support
The TPS53126 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the
low-side driver is held off until the soft-start commands a voltage higher than the pre-bias level (internal soft-start
becomes greater than feedback voltage [VFB]), then the TPS53126 slowly activates synchronous rectification by
limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle
basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the pre-
bias output, and ensure that the output voltage (VOUT) starts and ramps up smoothly into regulation and the
control loop is given time to transition from pre-biased start-up to normal mode operation.
8.3.7 Switching Frequency Selection
The TPS53126 allows the user to select from 2 different switching frequencies by connecting the TEST2 pin to
either GND or V5FILT. Connect TEST2 to GND for a switching frequency (fsw) of 350KHz. Connect TEST2 to
V5FILT for a switching frequency of 700KHz.
8.3.8 Output Discharge Control
The TPS53126 discharges the outputs when ENx is low, or when the controller is turned off by the protection
functions (OVP, UVP, UVLO, and thermal shutdown). The device discharges an output using an internal 40-Ω
MOSFET which is connected to VOx and PGNDx. The external low-side MOSFET is not turned on during the
output discharge operation to avoid the possibility of causing negative voltage at the output. This discharge
ensures that, on start, the regulated voltage always initializes from zero volts.
8.3.9 Overcurrent Limit
The TPS53126 has a cycle-by-cycle over current limit feature. The over current limits the inductor valley current
by monitoring the voltage drop across the low-side MOSFET RDS(on) during the low-side driver on-time. If the
inductor current is larger than the over current limit (OCL), the TPS53126 delays the start of the next switching
cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(on) current sensing is used to
provide an accuracy and cost effective solution without external devices. To program the OCL, the TRIPx pin
should be connected to GND through a trip voltage setting resistor, according to the following equations.
(1)
(2)
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TPS53126
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Feature Description (continued)
The trip voltage should be between 30mV to 300mV over all operational temperature, including the 4000ppm/°C
temperature slope compensation for the temperature dependency of the RDS(on). If the load current exceeds the
over-current limit, the voltage will begin to drop. If the over-current conditions continues the output voltage will fall
below the under voltage protection threshold and the TPS53126 will shut down.
8.3.10 Over/under Voltage Protection
The TPS53126 monitors the output voltage via the feedback voltage to detect over and under voltage. When the
feedback voltage becomes higher than 115% of the reference voltage, the TPS53126 turns off the high-side
MOSFET driver, turns on the low-side MOSFET driver and latches off.
When the feedback voltage becomes lower than 70% of the reference voltage, the TPS53126 begins an internal
UVP delay counter. After 30μs, the TPS53126 turns off both top and bottom MOSFET drivers and latches off.
The UVP function is enabled approximately 2.0ms after power-on to prevent detecting UVP during soft-start.
Both OVP and UVP latch conditions are reset when V5FILT triggers UVLO or the ENx pin goes low.
8.3.11 UVLO Protection
The TPS53126 has under voltage lock out protection (UVLO) that monitors the voltage of V5FILT pin. When the
V5FILT voltage is lower than UVLO threshold voltage, the device is shut off. During shut-off, VREG5 and all
output drivers are OFF and output discharge is ON. The UVLO is non-latch protection.
8.3.12 Thermal Shutdown
The TPS53126 includes an over temperature protection shut-down feature. If the TPS53126 die temperature
exceeds the OTP threshold (typically 150°C), both the high-side and low-side drivers are shut off, the output
voltage discharge function is enabled and then the device is shut off until the die temperature drops. Thermal
shutdown is a non-latch protection.
8.4 Device Functional Modes
The TPS53126 has two operating modes. The TPS53126 is in shut down mode when the EN1 and EN2 pins are
low. When the EN1 and EN2 pins is pulled high, the TPS53126 enters the normal operating mode.
Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
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l TEXAS INSTRUMENTS
DRVH2
VBST2
EN2
SW1
DRVL1
DRVH1
VBST1
EN1
VFB2
VO2
VO1
VFB1
GND
PGND2 PGND1
DRVL2
SW2
Input Voltage
PGND
PGND
PGND
SGND
24
22
23
19
20
21
13 14 15 16 17 18
8
9
10
11
12
7
12
3
4
5
6
PGND
SGND
TEST1
TEST2
TRIP2
V5FILT
VREG5
VIN
TRI P1
4.5V to 24V C9
10 Fm
C4
22 F 4m ´
C1
22 F 4m ´
VO2
1.05V/4A
C6
10 Fm
Q3
FDS8878
L2
SPM6530T
1.5 Hm
Q4
FDS8690
C5
0.1 Fm
R4
3.52kW
R5
10kW
R2
10kW
R1
13kW
R6
3.3kW
C8
1 Fm
C7
4.7 Fm
R3
4.7kW
VO1
1.8V/4A
C3
10 Fm
Q1
FDS8878
L1
SPM6530T
1.5 Hm
Q2
FDS8690
C2
0.1 Fm
PowerPAD
TPS53126
RGE
(QFN)
TPS53126
SLUS909B –MAY 2009–REVISED AUGUST 2014
www.ti.com
9 Application and Implementation
9.1 Application Information
9.2 350 kHz Operation Application
The schematic of Figure 14 shows a typical 350 kHz application schematic. The 350 kHz switching frequency is
selected by connecting TEST2 to the GND pin. The input voltage is 4.5 V to 24 V and the output voltage is 1.8 V
for VO1 and 1.05 V for VO2.
Figure 14. Typical Application Circuit at 350kHz Switching Frequency Selection (TEST2 Pin = GND)
9.2.1 Design Requirements
Table 1. Design Parameters
PARAMETERS CHANNEL 1 CHANNEL 2
Input voltage 4.5 V to 24 V 4.5 V to 24 V
Output voltage 1.8 V 1.05 V
Output Current 4 A 4 A
Switching Frequency 350 kHz 350 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Choose Inductor
The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load.
Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation.
Equation 3 can be used to calculate L1.
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l TEXAS INSTRUMENTS IL IL 7 IL / ( x x AV x x A
L1(ripple)
I1
C1 = 8 Vo1(ripple) sw
´¦
IN
Tmin(off) Ton1
K = (V Vo1) Vo1
Ton1 Ton1 + Tmin(off)
æ ö
- - ´ ´
ç ÷
è ø
2
ΔIload L1
C1 =
2 K Vus
´
´ ´ D
2
Iload L1
C1 =
2 Vo1 Vos
D ´
´ ´ D
( )
2
21
L1(RMS) L1(ripple)
12
I = Io1 + I
trip
L1(peak) L1(ripple)
DS(on)
V
I = + I
R
IN(max)
L1(ripple)
IN(max)
V Vo1 Vo1
I = L1 sw V
-´
´ ¦
( ) ( )
IN(max) IN(max)
L1(ripple) IN(max) IN(max)
V Vo1 3 V Vo1
Vo1 Vo1
L1 = =
I ƒsw V Io1 sw V
- ´ -
´ ´
´ ´ ¦
TPS53126
www.ti.com
SLUS909B –MAY 2009–REVISED AUGUST 2014
(3)
The inductors current ratings needs to support both the RMS (thermal) current and the Peak (saturation) current.
The RMS and peak inductor current can be estimated as follows:
(4)
(5)
(6)
Note: The calculation above shall serve as a general reference. To further improve transient response, the output
inductance could be reduced further. This needs to be considered along with the selection of the output
capacitor.
9.2.2.2 Choose Output Capacitor
The capacitor value and ESR determines the amount of output voltage ripple and load transient response.
Recommend to use ceramic output capacitor.
(7)
(8)
Where:
(9)
(10)
Select the capacitance value greater than the largest value calculated from Equation 7,Equation 8 and
Equation 10. The capacitance for C1 should be greater than 66 μF.
Where:
ΔVos = the allowable amount of overshoot voltage in load transition
ΔVus = the allowable amount of undershoot voltage in load transition
Tmin(off) = Min-off time
9.2.2.3 Choose Input Capacitor
The TPS53126 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A minimum 10-μF high-quality ceramic capacitor is recommended for the input capacitor. The
capacitor voltage rating needs to be greater than the maximum input voltage.
9.2.2.4 Choose Bootstrap Capacitor
The TPS53126 requires a bootstrap capacitor from SWx to VBSTx to provide the floating supply for the high-side
drivers. A minimum 0.1-μF high-quality ceramic capacitor is recommended. The voltage rating should be greater
than 6 V.
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l TEXAS INSTRUMENTS
trip
trip
trip
V (mV)
R (k ) = I ( A)
Wm
x
x
xfsw
xRDS(on)
Vtrip IOCL 2
L1
VIN VOVO
VIN
=
(ripple)
Vo1
R1 = 1 R2 (TEST2 V5FILT)
VFB1
0.758 + 2
æ ö
ç ÷
ç ÷
- ´ =
ç ÷
ç ÷
è ø
(ripple)
Vo1
R1 = 1 R2 (TEST2=GND)
VFB1
0.765 + 2
æ ö
ç ÷
ç ÷
- ´
ç ÷
ç ÷
è ø
TPS53126
SLUS909B –MAY 2009–REVISED AUGUST 2014
www.ti.com
9.2.2.5 Choose VREG5 and V5FILT Capacitors
The TPS53126 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-μF high-
quality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A minimum
1.0-μF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper operation.
Both of these capacitors’ voltage ratings should be greater than 6 V.
9.2.2.6 Choose Output Voltage Set Point Resistors
The output voltage is set with a resistor divider from output voltage node to the VFBx pin. It is recommended to
use 1% tolerance or better resisters. Select R2 between 10 kΩand 100 kΩand use Equation 11 and
Equation 12 to calculate R1.
(11)
(12)
Where:
VFB1(ripple) = Ripple Voltage at VFB1
9.2.2.7 Choose Over Current Limit Set Point Resistors
(13)
(14)
Where:
RDS(on) = Low Side FET on-resistance
Itrip = TRIP pin source current （= 10 μA）
IOCL = Over current limit
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t − time − 100µs/div COUT = 22µF × 4 G018
TEST2 = GND
350kHz Selection
VO1 (50mV/div)
Iout1 (2A/div)
t − time − 100µs/div COUT = 22µF × 4 G020
TEST2 = GND
350kHz Selection
VO2 (50mV/div)
Iout2 (2A/div)
IOUT − Output Current − A
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VOUT − Output Voltage − V
G017
TEST2 = V5FILT
TEST2 = GND
VIN = 12V
VO2 = 1.05V
TPS53126
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SLUS909B –MAY 2009–REVISED AUGUST 2014
9.2.3 350 kHz Application Curves
Application curves Figure 15,Figure 16,Figure 17,Figure 18,Figure 23 and Figure 24 apply to both the circuits
of 350 kHz Operation Application and 700 Khz Operation Application.
IO1 = 3 A IO2 = 3 A
Figure 15. SWITCHING FREQUENCY vs INPUT VOLTAGE Figure 16. SWITCHING FREQUENCY vs INPUT VOLTAGE
(CH1) (CH2)
VIN = 12 V VIN = 12 V
Figure 17. OUTPUT VOLTAGE vs OUTPUT CURRENT Figure 18. OUTPUT VOLTAGE vs OUTPUT CURRENT
(CH1) (CH2)
CH2, TEST2 = GND
CH1, TEST2 = GND
Figure 20. 1.05V LOAD TRANSIENT RESPONSE
Figure 19. 1.8V LOAD TRANSIENT RESPONSE
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‘5‘ TEXAS INSTRUMENTS
G028
TEST2 = GND
350kHz Selection
VO1 (20mV/div)
VO1 = 1.8V
VIN − Input Voltage − V
0.95
0.97
0.99
1.01
1.03
1.05
1.07
1.09
1.11
1.13
1.15
0 5 10 15 20 25
VOUT − Output Voltage − V
G027
TEST2 = V5FILT
TEST2 = GND
IOUT = 3A
VO2 = 1.05V
G022
TEST2 = GND
350kHz Selection
EN1 (10V/div)
VO1 (0.5V/div)
TPS53126
SLUS909B –MAY 2009–REVISED AUGUST 2014
www.ti.com
Figure 21. 1.8V START-UP WAVEFORMS VIN = 12 V
Figure 22. 1.8V EFFICIENCY vs OUTPUT CURRENT (CH1)
IO= 3 A IO= 3 A
Figure 23. 1.8V OUTPUT VOLTAGE vs INPUT VOLTAGE Figure 24. 1.05V OUTPUT VOLTAGE vs INPUT VOLTAGE
Figure 25. 1.8V OUTPUT RIPPLE VOLTAGE
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‘5‘ TEXAS INSTRUMENTS
DRVH2
VBST2
EN2
SW1
DRVL1
DRVH1
VBST1
EN1
VFB2
VO2
VO1
VFB1
GND
PGND2 PGND1
DRVL2
SW2
Input Voltage
PGND
PGND
PGND
SGND
24
22
23
19
20
21
13 14 15 16 17 18
8
9
10
11
12
7
12
3
4
5
6
PGND
SGND
TEST1
TEST2
TRIP2
V5FILT
VREG5
VIN
TRI P1
4.5V to 24V C9
10 Fm
C4
22 F 4m ´
C1
22 F 4m ´
VO2
1.05V/4A
C6
10 Fm
Q3
FDS8878
L2
SPM6530T
1.5 Hm
Q4
FDS8690
C5
0.1 Fm
R4
3.52kW
R5
10kW
R2
10kW
R1
13kW
R6
3.3kW
C8
1 Fm
C7
4.7 Fm
R3
4.7kW
VO1
1.8V/4A
C3
10 Fm
Q1
FDS8878
L1
SPM6530T
1.5 Hm
Q2
FDS8690
C2
0.1 Fm
PowerPAD
TPS53126
RGE
(QFN)
TPS53126
www.ti.com
SLUS909B –MAY 2009–REVISED AUGUST 2014
9.3 700 Khz Operation Application
The schematic of Figure 26 shows a typical 700 kHz application schematic. The 700 kHz switching frequency
is selected by connecting TEST2 to the V5FILT pin. The input voltage is 4.5 V to 24 V and the output voltage
is 1.8 V for VO1 and 1.05 V for VO2.
Figure 26. Typical Application Circuit at 700 kHz Switching frequency Selection (TEST2 Pin = V5FILT)
9.3.1 Design Parameters
PARAMETERS CHANNEL 1 CHANNEL 2
Input voltage 4.5 to 24 V 4.5 to 24 V
Output voltage 1.8 V 1.05 V
Output current 4 A 4 A
Switching Frequency 700 kHz 700 kHz
9.3.2 Detailed Design Procedure
For the Detailed Design Procedure, refer to Detailed Design Procedure.
9.3.3 700 kHz Application Curves
Application curves Figure 15,Figure 16,Figure 17,Figure 18,Figure 23 and Figure 24 apply to both the
circuits of 350 kHz Operation Application and 700 Khz Operation Application.
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l TEXAS INSTRUMENTS Nmmmmfl
G029
TEST2 = V5FILT
700kHz Selection
VO2 (20mV/div)
VO2 = 1.05V
G023
TEST2 = V5FILT
700kHz Selection
EN2 (5V/div)
VO2 (0.2V/div)
t − time − 100µs/div COUT = 22µF × 2 G019
TEST2 = V5FILT
700kHz Selection
VO1 (50mV/div)
Iout1 (2A/div)
t − time − 100µs/div COUT = 22µF × 2 G021
TEST2 = V5FILT
700kHz Selection
VO2 (50mV/div)
Iout2 (2A/div)
TPS53126
SLUS909B –MAY 2009–REVISED AUGUST 2014
www.ti.com
CH1, TEST2 = V5FILT CH2, TEST2 = V5FILT
Figure 27. 1.8V LOAD TRANSIENT RESPONSE Figure 28. 1.05V LOAD TRANSIENT RESPONSE
Figure 29. 1.05V START-UP WAVEFORMS VIN = 12 V
Figure 30. 1.05V EFFICIENCY vs OUTPUT CURRENT (CH2)
Figure 31. 1.05V OUTPUT RIPPLE VOLTAGE
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SLUS909B –MAY 2009–REVISED AUGUST 2014
10 Power Supply Recommendations
The TPS53126 is designed to operate from an input voltage supply range between 4.5 V and 24 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the TPS53126 device
additional 0.1 µF ceramic capacitance may be required in addition to the ceramic bypass capacitors, 10 µF.
11 Layout
11.1 Layout Guidelines
• Keep the input switching current loop as small as possible. (VIN ≥C3 ≥PNGD ≥Sync FET ≥SW ≥Control
FET)
• Place the input capacitor (C3) close to the top switching FET. The output current loop should also be kept as
small as possible.
• Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback terminal (FBx) of the device.
• Keep analog and non-switching components away from switching components.
• Make a single point connection from the signal ground to power ground.(1)
• Do not allow switching current to flow under the device.
• DRVH and DRVL line should not run close to SW node or minimize it. (2)
• GND terminals for capacitors of SSx and V5FILT and resistors of feedback and TRIPx should be connected
to SGND. (3)
• GND terminals for capacitors of VREG5 and VIN should be connected to PGND. (4)
• Signal lines should not run under/near Output Inductor or minimize it. (5)
11.2 Layout Example
The layout example of Figure 32 corresponds to the schematic of Figure 14.
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Product Folder Links: TPS53126
% TEXAS INSTRUMENTS Component Pads Shown in White
SW1
DRVL1
DRVH1
VBST1
EN1
PGND1
TRIP1
VIN
VREG5
V5FILT
TEST2
TRIP2
PGND2
DRVL2
SW2
DRVH2
VBST2
EN2
VO1
VFB1
GND
TEST1
VFB2
VO2
12
3
4
5
6
7
8
9
11
12
10
13 15 16 17 18
19
20
21
22
23
24
14
TPS53126
RGE
(QFN )
Thermal PAD
R1
R2
R4
R5
C2
R3
C7
C9
C8
R6
C5
Q2
Q1
Q3
Q4
L2
C4, 1
C4, 2
C1, 1
C1, 2
L1
C6 C3
TO EN 2 TO EN 1
(3)
(3) (3)
(1)
(4)
(5)(5)
VIN
S 1W
S 2W
VOUT2 VOUT1
PGND
SGND
Top Side Component or Via
Bottom Side Component
Top Side Etch
Bottom Side Etch
Component Pads Shown in White
C4, 3
C4, 4
C1, 3
C1, 4
TPS53126
SLUS909B –MAY 2009–REVISED AUGUST 2014
www.ti.com
Layout Example (continued)
Figure 32. Board Layout
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12 Device and Documentation Support
12.1 Trademarks
D-CAP2 is a trademark of Texas Instruments.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: TPS53126
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS53126PW ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PS53126
TPS53126PWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PS53126
TPS53126RGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
53126
TPS53126RGET ACTIVE VQFN RGE 24 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
53126
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«Pi» Reel Diameler AD Dimension designed to accommodate the componeni width ED Dimension deSigned to accommodaie me componeni iengm KO Dlmenslun designed to accommodate the eomponeni thickness 7 w OveraH Widlh loe earner cape i p1 Piich between successive cawiy ceniers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprockeiHules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS53126PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
TPS53126RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS53126RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS53126PWR TSSOP PW 24 2000 853.0 449.0 35.0
TPS53126RGER VQFN RGE 24 3000 853.0 449.0 35.0
TPS53126RGET VQFN RGE 24 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 2
I TEXAS INSTRUMENTS
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
RGE 24 VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4204104/H
vi iv:‘l_$f CCCECCN
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PACKAGE OUTLINE
C
SEE TERMINAL
DETAIL
24X 0.3
0.2
2.45 0.1
24X 0.5
0.3
1 MAX
(0.2) TYP
0.05
0.00
20X 0.5
2X
2.5
2X 2.5
A4.1
3.9 B
4.1
3.9 0.3
0.2
0.5
0.3
VQFN - 1 mm max heightRGE0024B
PLASTIC QUAD FLATPACK - NO LEAD
4219013/A 05/2017
PIN 1 INDEX AREA
0.08 C
SEATING PLANE
1
613
18
7 12
24 19
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05
EXPOSED
THERMAL PAD
25 SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 3.000
DETAIL
OPTIONAL TERMINAL
TYPICAL
j|j
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EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
24X (0.25)
24X (0.6)
( 0.2) TYP
VIA
20X (0.5)
(3.8)
(3.8)
( 2.45)
(R0.05)
TYP
(0.975) TYP
VQFN - 1 mm max heightRGE0024B
PLASTIC QUAD FLATPACK - NO LEAD
4219013/A 05/2017
SYMM
1
6
712
13
18
19
24
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
25
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
j||4 wig? ; Vi
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EXAMPLE STENCIL DESIGN
24X (0.6)
24X (0.25)
20X (0.5)
(3.8)
(3.8)
4X ( 1.08)
(0.64)
TYP
(0.64) TYP
(R0.05) TYP
VQFN - 1 mm max heightRGE0024B
PLASTIC QUAD FLATPACK - NO LEAD
4219013/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
25
SYMM
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
6
712
13
18
19
24
I ,/ x /. \_ , ‘ .\ ,, /x ,, S 1 EL fig
www.ti.com
PACKAGE OUTLINE
C
22X 0.65
2X
7.15
24X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
7.9
7.7
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
1
12 13
24
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.000
gmmmflgmmfij ‘w“““‘+“‘w““‘ Emma—5% R
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
24X (1.5)
24X (0.45)
22X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
12 13
24
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
fiflmmmmmfimmmfi$% Emma—5%g
www.ti.com
EXAMPLE STENCIL DESIGN
24X (1.5)
24X (0.45)
22X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
12 13
24
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