Scheda tecnica SN74AUP2G04 di Texas Instruments

I TEXAS INSTRUMENTS ,~ ,‘
4
2
3
2A
GND
1A
2Y
1
DCKPACKAGE
(TOP VIEW)
1Y
6
VCC
5
2A 2Y
34
GND 25
1A 6
1
VCC
1Y
DSFPACKAGE
(TOP VIEW)
YFP PACKAGE
(TOP VIEW)
2A
1Y
GND 5
4
2
3
1A
2Y
1
DRY PACKAGE
(TOP VIEW)
6
VCC 2A
1A
2Y
1Y
GND
3
6
2
1
4
5VCC
A1
B1
C1
A2
B2
C2
(A) Single,dual,andtriplegates
Static-PowerConsumption
(µA)
AUP
AUP
3.3-V
Logic(A)
0%
20%
40%
60%
80%
100%
Dynamic-PowerConsumption
(pF)
AUP
AUP
3.3-V
Logic(A)
0%
20%
40%
60%
80%
100%
SwitchingCharacteristics
at25MHz(A)
−0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0 5 10 15 20 25 30 35 40 45
Time(ns)
Voltage(V)
OutputInput
(A) SN74AUP2GxxdataatC =15pF.
L
SN74AUP2G04
www.ti.com
SCES747B –SEPTEMBER 2009–REVISED MARCH 2010
LOW-POWER DUAL INVERTER GATE
Check for Samples: SN74AUP2G04
1FEATURES
• Available in the Texas Instruments NanoStar™ • Optimized for 3.3-V Operation
Package • 3.6-V I/O Tolerant to Support Mixed-Mode
• Low Static-Power Consumption: Signal Operation
ICC = 0.9 mA Max • tpd = 4.3 ns Max at 3.3 V
• Low Dynamic-Power Consumption: • Suitable for Point-to-Point Applications
Cpd = 4.3 pF Typ at 3.3 V • Latch-Up Performance Exceeds 100 mA Per
• Low Input Capacitance: Ci= 1.5 pF Typ JESD 78, Class II
• Low Noise: Overshoot and Undershoot • ESD Performance Tested Per JESD 22
<10% of VCC – 2000-V Human-Body Model
• Ioff Supports Partial-Power-Down Mode (A114-B, Class II)
Operation – 1000-V Charged-Device Model (C101)
• Wide Operating VCC Range of 0.8 V to 3.6 V
N.C. – No internal connection
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
Figure 1. AUP – The Lowest-Power Family Figure 2. Excellent Signal Integrity
The SN74AUP2G04 performs the Boolean function Y = A in positive logic.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
l TEXAS INSTRUMENTS IA TY
1A 1Y
1 6
2A 2Y
3 4
SN74AUP2G04
SCES747B –SEPTEMBER 2009–REVISED MARCH 2010
www.ti.com
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
ORDERABLE TOP-SIDE
TAPACKAGE(2) PART NUMBER MARKING(3)
NanoStar™ – WCSP (DSBGA) Reel of 3000 SN74AUP2G04YFPR _ _ _ H C _
0.23-mm Large Bump – YFP (Pb-free)
QFN – DRY Reel of 5000 SN74AUP2G04DRYR H4
–40°C to 85°C
uQFN – DSF Reel of 5000 SN74AUP2G04DSFR H4
SOT (SC-70) – DCK Reel of 3000 SN74AUP2G04DCKR H4_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
(Each Inverter)
INPUT OUTPUT
A Y
H L
L H
LOGIC DIAGRAM (POSITIVE LOGIC)
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SCES747B –SEPTEMBER 2009–REVISED MARCH 2010
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 4.6 V
VIInput voltage range(2) –0.5 4.6 V
VOVoltage range applied to any output in the high-impedance or power-off state(2) –0.5 4.6 V
VOOutput voltage range in the high or low state(2) –0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±20 mA
Continuous current through VCC or GND ±50 mA
DCK package 252
DRY package 234
qJA Package thermal impedance(3) °C/W
DSF package 300
YFP package 132
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
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SCES747B –SEPTEMBER 2009–REVISED MARCH 2010
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RECOMMENDED OPERATING CONDITIONS(1)
MIN MAX UNIT
VCC Supply voltage 0.8 3.6 V
VCC = 0.8 V VCC
VCC = 1.1 V to 1.95 V 0.65 × VCC
VIH High-level input voltage V
VCC = 2.3 V to 2.7 V 1.6
VCC = 3 V to 3.6 V 2
VCC = 0.8 V 0
VCC = 1.1 V to 1.95 V 0.35 × VCC
VIL Low-level input voltage V
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.9
VIInput voltage 0 3.6 V
VOOutput voltage 0 VCC V
VCC = 0.8 V –20 mA
VCC = 1.1 V –1.1
VCC = 1.4 V –1.7
IOH High-level output current VCC = 1.65 –1.9 mA
VCC = 2.3 V –3.1
VCC = 3 V –4
VCC = 0.8 V 20 mA
VCC = 1.1 V 1.1
VCC = 1.4 V 1.7
IOL Low-level output current VCC = 1.65 V 1.9 mA
VCC = 2.3 V 3.1
VCC = 3 V 4
Δt/Δv Input transition rise or fall rate VCC = 0.8 V to 3.6 V 200 ns/V
TAOperating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow of Floating CMOS Inputs, literature number SCBA004.
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SCES747B –SEPTEMBER 2009–REVISED MARCH 2010
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
TA= 25°C TA= –40°C to 85°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX
IOH = –20 mA 0.8 V to 3.6 V VCC – 0.1 VCC – 0.1
IOH = –1.1 mA 1.1 V 0.75 × VCC 0.7 × VCC
IOH = –1.7 mA 1.4 V 1.11 1.03
IOH = –1.9 mA 1.65 V 1.32 1.3
VOH V
IOH = –2.3 mA 2.05 1.97
2.3 V
IOH = –3.1 mA 1.9 1.85
IOH = –2.7 mA 2.72 2.67
3 V
IOH = –4 mA 2.6 2.55
IOL = 20 mA 0.8 V to 3.6 V 0.1 0.1
IOL = 1.1 mA 1.1 V 0.3 × VCC 0.3 × VCC
IOL = 1.7 mA 1.4 V 0.31 0.37
IOL = 1.9 mA 1.65 V 0.31 0.35
VOL V
IOL = 2.3 mA 0.31 0.33
2.3 V
IOL = 3.1 mA 0.44 0.45
IOL = 2.7 mA 0.31 0.33
3 V
IOL = 4 mA 0.44 0.45
IIA or B input VI= GND to 3.6 V 0 V to 3.6 V 0.1 0.5 mA
Ioff VIor VO= 0 V to 3.6 V 0 V 0.2 0.6 mA
ΔIoff VIor VO= 0 V to 3.6 V 0 V to 0.2 V 0.2 0.6 mA
VI= GND or (VCC to 3.6 V),
ICC 0.8 V to 3.6 V 0.5 0.9 mA
IO= 0
ΔICC VI= VCC – 0.6 V(1), IO= 0 3.3 V 40 50 mA
0 V 1.5
CiVI= VCC or GND pF
3.6 V 1.5
CoVO= GND 0 V 3 pF
(1) One input at VCC – 0.6 V, other input at VCC or GND.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL= 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
TA= 25°C TA= –40°C to 85°C
FROM TO
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX
0.8 V 18
1.2 V ± 0.1 V 2.6 7.3 12.8 2.1 15.6
1.5 V ± 0.1 V 1.4 5.2 8.7 0.9 10.3
tpd A or B Y ns
1.8 V ± 0.15 V 1 4.2 6.6 0.5 8.2
2.5 V ± 0.2 V 1 3 4.4 0.5 5.5
3.3 V ± 0.3 V 1 2.4 3.5 0.5 4.3
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SCES747B –SEPTEMBER 2009–REVISED MARCH 2010
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SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL= 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
TA= 25°C TA= –40°C to 85°C
FROM TO
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX
0.8 V 21
1.2 V ± 0.1 V 1.5 8.5 14.7 1 17.2
1.5 V ± 0.1 V 1 6.2 10 0.5 11.3
tpd A or B Y ns
1.8 V ± 0.15 V 1 5 7.7 0.5 9
2.5 V ± 0.2 V 1 3.6 5.2 0.5 6.1
3.3 V ± 0.3 V 1 2.9 4.2 0.5 4.7
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL= 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
TA= 25°C TA= –40°C to 85°C
FROM TO
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX
0.8 V 24
1.2 V ± 0.1 V 3.6 9.9 16.3 3.1 19.9
1.5 V ± 0.1 V 2.3 7.2 11.1 1.8 13.2
tpd A or B Y ns
1.8 V ± 0.15 V 1.6 5.8 8.7 1.1 10.6
2.5 V ± 0.2 V 1 4.3 5.9 0.5 7.3
3.3 V ± 0.3 V 1 3.4 4.8 0.5 5.9
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL= 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
TA= 25°C TA= –40°C to 85°C
FROM TO
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX
0.8 V 32.8
1.2 V ± 0.1 V 4.9 13.1 20.9 4.4 25.5
1.5 V ± 0.1 V 3.4 9.5 14.2 2.9 16.9
tpd A or B Y ns
1.8 V ± 0.15 V 2.5 7.7 11 2 13.5
2.5 V ± 0.2 V 1.8 5.7 7.6 1.3 9.4
3.3 V ± 0.3 V 1.5 4.7 6.2 1 7.5
OPERATING CHARACTERISTICS
TA= 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
0.8 V 4
1.2 V ± 0.1 V 4
1.5 V ± 0.1 V 4
Cpd Power dissipation capacitance f = 10 MHz pF
1.8 V ± 0.15 V 4
2.5 V ± 0.2 V 4.1
3.3 V ± 0.3 V 4.3
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l TEXAS INSTRUMENTS INVERTING AND NONINVERTING OUTPUTS SETUP AND HOLD TIMES
VM
FromOutput
UnderTest
CL
(seeNote A)
LOADCIRCUIT
1MΩ
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0V
Input
Output
Output
VMVM
VMVM
VM
5,10,15,30pF
VCC/2
VCC
VCC =1.2V
±0.1V
VCC =0.8V VCC =1.5V
±0.1V
VCC =1.8V
±0.15V
VCC =2.5V
±0.2V
VCC =3.3V
±0.3V
5,10,15,30pF
VCC/2
VCC
5,10,15,30pF
VCC/2
VCC
5,10,15,30pF
VCC/2
VCC
CL
VM
VI
5,10,15,30pF
VCC/2
VCC
5,10,15,30pF
VCC/2
VCC
th
tsu
DataInput
TimingInput
VCC
0V
VCC
0V
0V
tw
Input
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VOLTAGEWAVEFORMS
PULSEDURATION
VCC/2 VCC/2
VCC/2
VCC/2
VCC
VCC/2
SN74AUP2G04
www.ti.com
SCES747B –SEPTEMBER 2009–REVISED MARCH 2010
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Width)
A. CLincludes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, for
propagation delays tr/tf= 3 ns, for setup and hold times and pulse width tr/tf= 1.2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLH and tPHL are the same as tpd.
F. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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l TEXAS INSTRUMENTS S1 fl i444 i 4 T L f LOW— AND HIGH-LEVEL ENABLING
5,10,15,30pF
VCC/2
VCC
0.15V
VCC =1.2V
±0.1V
VCC =0.8V VCC =1.5V
±0.1V
VCC =1.8V
±0.15V
VCC =2.5V
±0.2V
VCC =3.3V
±0.3V
5,10,15,30pF
VCC/2
VCC
0.1V
5,10,15,30pF
VCC/2
VCC
0.1V
5,10,15,30pF
VCC/2
VCC
0.1V
CL
VM
VI
V∆
5,10,15,30pF
VCC/2
VCC
0.15V
5,10,15,30pF
VCC/2
VCC
0.3V
Output
Waveform1
S1at2 xVCC
(seeNoteB)
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0V
VOL +V∆
VOH -V∆
≈0V
VCC
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
Output
Control VCC/2 VCC/2
VCC/2
VCC/2
tPLZ/tPZL
tPHZ/tPZH
2xVCC
GND
TEST S1
FromOutput
UnderTest
CL
(seeNote A)
LOADCIRCUIT
S1
GND
5kΩ
5kΩ
2xVCC
SN74AUP2G04
SCES747B –SEPTEMBER 2009–REVISED MARCH 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
A. CLincludes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf= 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPLH and tPHL are the same as tpd.
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74AUP2G04DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (H45, H4F)
SN74AUP2G04DRYR ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 H4
SN74AUP2G04DSFR ACTIVE SON DSF 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 H4
SN74AUP2G04YFPR ACTIVE DSBGA YFP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 HCN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Diameter AD Dimension designed to accommodate the component Width ED Dimension destgned to accommodate the component tengtti K0 Dimension designed to accommodate the component thickness 7 W OveraH wtdlh loe earner tape i P1 Pttch between successwe cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE OOODOODD ,,,,,,,,,,, ‘ User Direcllon 0' Feed Sprocket Hoies Pockel Quadrants
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AUP2G04DCKR SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AUP2G04DCKR SC70 DCK 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74AUP2G04DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1
SN74AUP2G04DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
SN74AUP2G04YFPR DSBGA YFP 6 3000 178.0 9.2 0.89 1.29 0.62 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AUP2G04DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74AUP2G04DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74AUP2G04DRYR SON DRY 6 5000 184.0 184.0 19.0
SN74AUP2G04DSFR SON DSF 6 5000 184.0 184.0 19.0
SN74AUP2G04YFPR DSBGA YFP 6 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
MECHANICAL DATA DCK (R-PDSO-GS) PLASTIC SMALL-OUTLINE PACKAGE E 18’) 6 4 7 H Fl H ‘fi «40 1233 \ ’i’ To enugemane Seanng Mane Pm 1/ ' ‘ ' ‘ ‘ maexArea Wm H m} j; / ‘ u / Um "4L 1—]; f Scamg Mane \\ \ / 31 409555574/8 U‘ /200/ , m m hmeters AH \mec' mmens‘mrs Tm drawmq \s sumsc: 0 change wmu: nome Body mmensmns do nut mc‘ude mom flcsh m aroms'm Mom Has» and pruvuswon W m exceed 015 :2r m FuHs an JFDFC M07763 vunuhcn AB NO'FS Umm> INSrRUMEm-s www.1i.com
LAND PATTERN DATA 7PJSOiC6> PLASTC SMALL OU’LME NOTES' maop> Exc'm‘e Boc'd Luyum stem Openings Based or a stencfl hickncss uf 127mm (005mm) * 1* :E /23\\der Musk Cpen‘wg “ 2m Geometry M \meur dimensmns are m m'flhrvete's Th's drawqu is sweat (a chc'vge mm: 'vuhce Custume's shoud p‘uce a new 01 We cvcmt buurd (abr'cahun c'awmg rm :0 uHer the ce'fle' smder musk defined and, ”Jbficuhon \PC77351 is reco'n'nended (Dr uHernme designs Laser cumrg opc'mvcs mm "apczmda wuHs and mo rouncmq corners wm am bcncr aosxc recuscv mstomcrs show can thew Guard assemwy sue for gene design recommencnmons Exomme sxercu deswgw basec on a 50% vo‘umemc bad My paste M‘cr m M4523 var other new rccowmcwdatnrs. ' hams Q‘ INSTRUMENTS www.li.com
E” r, LELA J Q3021 ‘ I-III
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PACKAGE OUTLINE
C
0.5 MAX
0.19
0.13
0.8
TYP
0.4
TYP
0.4 TYP
6X 0.25
0.21
B E A
D
4223410/A 11/2016
DSBGA - 0.5 mm max heightYFP0006
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
BALL A1
CORNER
SEATING PLANE
BALL TYP 0.05 C
A
B
C
2
0.015 C A B
SYMM
SYMM
1
SCALE 10.000
D: Max =
E: Max =
1.19 mm, Min =
0.79 mm, Min =
1.13 mm
0.73 mm
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EXAMPLE BOARD LAYOUT
6X ( 0.23)
(0.4) TYP
(0.4) TYP
( 0.23)
METAL 0.05 MAX
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
( 0.23)
SOLDER MASK
OPENING
0.05 MIN
4223410/A 11/2016
DSBGA - 0.5 mm max heightYFP0006
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
SOLDER MASK DETAILS
NOT TO SCALE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:50X
A
B
C
12
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
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EXAMPLE STENCIL DESIGN
(0.4) TYP
(0.4) TYP
6X ( 0.25) (R0.05) TYP
METAL
TYP
4223410/A 11/2016
DSBGA - 0.5 mm max heightYFP0006
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:50X
A
B
C
12
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PACKAGE OUTLINE
C
6X 0.22
0.12
6X 0.45
0.35
2X
0.7 4X
0.35
0.4 MAX
0.05
0.00
B1.05
0.95 A
1.05
0.95
(0.11) TYP
(0.1)
PIN 1 ID
4220597/A 06/2017
X2SON - 0.4 mm max heightDSF0006A
PLASTIC SMALL OUTLINE - NO LEAD
PIN 1 INDEX AREA
SEATING PLANE
0.05 C
1
34
6
0.07 C B A
0.05 C
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.
SCALE 10.000
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EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
6X (0.6)
6X (0.17)
4X (0.35)
(0.8)
(R0.05) TYP
X2SON - 0.4 mm max heightDSF0006A
PLASTIC SMALL OUTLINE - NO LEAD
4220597/A 06/2017
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
SYMM
SYMM
1
34
6
EXPOSED METAL
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
““‘+“‘w‘
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EXAMPLE STENCIL DESIGN
6X (0.6)
6X (0.17)
4X (0.35)
(0.8)
(R0.05) TYP
X2SON - 0.4 mm max heightDSF0006A
PLASTIC SMALL OUTLINE - NO LEAD
4220597/A 06/2017
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
SYMM
SYMM
1
34
6
I TEXAS INSTRUMENTS
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DRY 6 USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4207181/G
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PACKAGE OUTLINE
C
6X 0.25
0.15
4X
0.5
5X 0.35
0.25
2X
1
0.6 MAX
0.05
0.00
3X 0.6
0.4
0.3
B1.05
0.95 A
1.5
1.4
(0.05) TYP (0.127) TYP
4222894/A 01/2018
USON - 0.6 mm max heightDRY0006A
PLASTIC SMALL OUTLINE - NO LEAD
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
34
6
(OPTIONAL)
PIN 1 ID
0.1 C A B
0.05 C
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
SCALE 8.500
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EXAMPLE BOARD LAYOUT
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
5X (0.3)
6X (0.2)
4X (0.5)
(0.6)
(R0.05) TYP
(0.35)
4222894/A 01/2018
USON - 0.6 mm max heightDRY0006A
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
1
34
6
SYMM
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
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EXAMPLE STENCIL DESIGN
5X (0.3)
6X (0.2)
4X (0.5)
(0.6)
(R0.05) TYP
(0.35)
4222894/A 01/2018
USON - 0.6 mm max heightDRY0006A
PLASTIC SMALL OUTLINE - NO LEAD
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
SYMM
1
34
6
SYMM
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