Scheda tecnica CDCLVD2102 di Texas Instruments

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I TEXAS INSTRUMENTS

PHY2

DAC2

200 MHz

Clock

Generation

100 MHz

CDCLVD 2102

ADC2

CDCLVD2102

www.ti.com

SCAS904A –MAY 2010–REVISED JUNE 2010

Dual 1:2 Low Additive Jitter LVDS Buffer

Check for Samples: CDCLVD2102

1FEATURES DESCRIPTION

• Dual 1:2 Differential Buffer

• Low Additive Jitter <300 fs RMS in 10-kHz to The CDCLVD2102 clock buffer distributes two clock

inputs (IN0, IN1) to a total of 4 pairs of differential

20-MHz LVDS clock outputs (OUT0, OUT3). Each buffer block

• Low Within Bank Output Skew of 15 ps (Max) consists of one input and 2 LVDS outputs. The inputs

• Universal Inputs Accept LVDS, LVPECL, can either be LVDS, LVPECL, or LVCMOS.

LVCMOS The CDCLVD2102 is specifically designed for driving

• One Input Dedicated for Two Outputs 50-Ωtransmission lines. If driving the inputs in single

• Total of 4 LVDS Outputs, ANSI EIA/TIA-644A ended mode, the appropriate bias voltage (VAC_REF)

Standard Compatible should be applied to the unused negative input pin.

• Clock Frequency up to 800 MHz Using the control pin (EN), outputs can be either

disabled or enabled. If the EN pin is left open two

• 2.375–2.625V Device Power Supply buffers with all outputs are enabled, if switched to a

• LVDS Reference Voltage, VAC_REF, Available for logical "0" both buffers with all outputs are disabled

Capacitive Coupled Inputs (static logical "0"), if switched to a logical "1", one

• Industrial Temperature Range –40°C to 85°C buffer with two outputs is disabled and another buffer

with two outputs is enabled. The part supports a fail

• Packaged in 3mm × 3mm 16-Pin QFN (RGT) safe function. It incorporates an input hysteresis,

• ESD Protection Exceeds 3 kV HBM, 1 kV CDM which prevents random oscillation of the outputs in

absence of an input signal.

APPLICATIONS The device operates in 2.5V supply environment and

• Telecommunications/Networking is characterized from –40°C to 85°C (ambient

• Medical Imaging temperature). The CDCLVD2102 is packaged in

• Test and Measurement Equipment small 16-pin, 3-mm × 3-mm QFN package.

• Wireless Communications

• General Purpose Clocking

Figure 1. Application Example

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

l TEXAS INSTRUMENTS ’)—(‘ XV) GND |_||_||_||J FIFIFII—I I—II—II—IFI

Reference

Generator

LVDS

INN0

INP0

INN1

INP1

GND

OUTN [0..1]

OUTP [0..1]

VCC

200 kW

LVDS

OUTN [2..3]

OUTP [2..3]

VAC_REF

VCC

200 kW

3mm x 3mm

16 pin QFN (RGT)

Thermal Pad

VCC

INP0

INN0

1 2 3 4

12 11 10 9

OUTP0

OUTN0

OUTP1

OUTN1

OUTP2

OUTN3

OUTP3

OUTN2

INN1

INP1

GND

VAC_REF

CDCLVD2102

SCAS904A –MAY 2010–REVISED JUNE 2010

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Figure 2. CDCLVD2102 Block Diagram

TOP VIEW

Product Folder Link(s): CDCLVD2102

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CDCLVD2102

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SCAS904A –MAY 2010–REVISED JUNE 2010

PIN FUNCTIONS

PIN TYPE DESCRIPTION

NAME NO.

VCC 5 Power 2.5V supplies for the device

GND 1 Ground Device ground

INP0, INN0 6, 7 Input Differential input pair or single ended input

INP1, INN1 3, 4 Input Differential redundant input pair or single ended input

Bias voltage output for capacitive coupled inputs. If used, it is recommended to

VAC_REF 8 Output use a 0.1µF to GND on this pin

OUTP0, OUTN0 9, 10 Output Differential LVDS output pair no. 0 INP0/INN0 is the input

OUTP1, OUTN1 11, 12 Output Differential LVDS output pair no. 1

OUTP2, OUTN2 13, 14 Output Differential LVDS output pair no. 2 INP1/INN1 is the input

OUTP3, OUTN3 15, 16 Output Differential LVDS output pair no. 3

Input with internal

EN 2 200kΩpull-up and Control pin – enables or disables the outputs, (See Table 1)

pull-down

Thermal Pad See thermal management recommendations

Table 1. Output Control Table

EN CLOCK OUTPUTS

0 All outputs disabled (static "0")

OPEN All outputs enabled

1 OUT0, OUT1 enabled and OUT2, OUT3 disabled (static "0")

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)(1)

VALUE / UNIT

Supply voltage range, VCC –0.3 to 2.8 V

Input voltage, VI–0.2 to (VCC + 0.2) V

Output voltage range, VO–0.2 to (VCC + 0.2) V

Driver short circuit current, IOSD See Note (2)

Electrostatic discharge (HBM, 1.5 kΩ, 100 pF) >3000 V

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) The outputs can handle permanent short.

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNITS

Device supply voltage, VCC 2.375 2.5 2.625 V

Ambient temperature, TA–40 85 oC

Product Folder Link(s): CDCLVD2102

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CDCLVD2102

SCAS904A –MAY 2010–REVISED JUNE 2010

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THERMAL INFORMATION

CDCLVD2102

THERMAL METRIC(1) RGT UNITS

16 PINS

qJA Junction-to-ambient thermal resistance 51.3

qJC(top) Junction-to-case(top) thermal resistance 85.4

qJB Junction-to-board thermal resistance 20.1 °C/W

yJT Junction-to-top characterization parameter 1.3

yJB Junction-to-board characterization parameter 19.4

qJC(bottom) Junction-to-case(bottom) thermal resistance 6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

ELECTRICAL CHARACTERISTICS:

At VCC = 2.375 V to 2.625 V and TA= –40°C to 85°C (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

EN PIN INPUT CHARACTERISTICS

VdI3 3-State Open 0.5×VCC V

VdIH Input high voltage 0.7×VCC V

VdIL Input low voltage 0.2×VCC V

IdIH Input high current VCC = 2.625 V, VIH = 2.625 V 30 mA

IdIL Input low current VCC = 2.625 V, VIL = 0 V –30 mA

Rpull(EN) Input pull-up/ pull-down resistor 200 kΩ

2.5V LVCMOS (see Figure 7) INPUT CHARACTERISTICS

fIN Input frequency 200 MHz

External threshold voltage applied

Vth Input threshold voltage 1.1 1.5 V

to complementary input

VIH Input high voltage Vth + 0.1 VCC V

VIL Input low voltage 0 Vth – 0.1 V

IIH Input high current VCC = 2.625 V, VIH = 2.625 V 10 mA

IIL Input low current VCC = 2.625 V, VIL = 0 V –10 mA

ΔV/ΔT Input edge rate 20% – 80% 1.5 V/ns

CIN Input capacitance 2.5 pF

DIFFERENTIAL INPUT CHARACTERISTICS

fIN Input frequency Clock input 800 MHz

Differential input voltage

VIN, DIFF VICM = 1.25 V 0.3 1.6 VP-P

peak-to-peak

VICM Input common-mode voltage range VIN, DIFF, PP > 0.4V 1 VCC – 0.3 V

IIH Input high current VCC = 2.625 V, VIH = 2.625 V 10 mA

IIL Input low current VCC = 2.625 V, VIL = 0 V –10 mA

ΔV/ΔT Input edge rate 20% to 80% 0.75 V/ns

CIN Input capacitance 2.5 pF

Product Folder Link(s): CDCLVD2102

l TEXAS INSTRUMENTS

CDCLVD2102

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SCAS904A –MAY 2010–REVISED JUNE 2010

ELECTRICAL CHARACTERISTICS: (continued)

At VCC = 2.375 V to 2.625 V and TA= –40°C to 85°C (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LVDS OUTPUT CHARACTERISTICS

|VOD| Differential output voltage magnitude 250 450 mV

Change in differential output voltage

ΔVOD –15 15 mV

magnitude VIN, DIFF, PP = 0.3 V,RL= 100 Ω

Steady-state common mode output

VOC(SS) 1.1 1.375 V

voltage

Steady-state common mode output

ΔVOC(SS) VIN, DIFF, PP = 0.6 V,RL= 100 Ω–15 15 mV

voltage

Percentage of output amplitude

Vring Output overshoot and undershoot 10%

VOD

VOS Output ac common mode VIN, DIFF, PP = 0.6 V, RL= 100 Ω25 70 mVPP

IOS Short-circuit output current VOD = 0 V ±24 mA

tPD Propagation delay VIN, DIFF, PP = 0.3 V 1.5 2.5 ns

tSK, PP Part-to-part skew 600 ps

tSK, O_WB Within bank output skew 15 ps

tSK,O_BB Bank-to-bank output skew Both inputs are phase aligned 100 ps

Pulse skew(with 50% duty cycle Crossing-point-to-crossing-point

tSK,P –50 50 ps

input) distortion

Random additive jitter (with 50% duty Edge speed = 0.75V/ns,

tRJIT 0.3 ps, RMS

cycle input) 10 kHz – 20 MHz

tR/tFOutput rise/fall time 20% to 80%,100 Ω, 5 pF 50 300 ps

ICCSTAT Static supply current Outputs unterminated, f = 0 Hz 27 45 mA

All outputs enabled, RL= 100 Ω,

ICC100 Supply current 49 77 mA

f = 100 MHz

All outputs enabled, RL= 100 Ω,

ICC800 Supply current 76 106 mA

f = 800 MHz

VAC_REF CHARACTERISTICS

VAC_REF Reference output voltage VCC = 2.5 V, Iload = 100 µA 1.1 1.25 1.35 V

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CDCLVD2102

SCAS904A –MAY 2010–REVISED JUNE 2010

www.ti.com

Typical Additive Phase Noise Characteristics for 100 MHz Clock

PARAMETER MIN TYP MAX UNIT

phn100 Phase noise at 100 Hz offset -132.9 dBc/Hz

phn1k Phase noise at 1 kHz offset -138.8 dBc/Hz

phn10k Phase noise at 10 kHz offset -147.4 dBc/Hz

phn100k Phase noise at 100 kHz offset -153.6 dBc/Hz

phn1M Phase noise at 1 MHz offset -155.2 dBc/Hz

phn10M Phase noise at 10 MHz offset -156.2 dBc/Hz

phn20M Phase noise at 20 MHz offset -156.6 dBc/Hz

tRJIT Random additive jitter from 10 kHz to 20 MHz 171 fs, RMS

Typical Additive Phase Noise Characteristics for 737.27 MHz Clock

PARAMETER MIN TYP MAX UNIT

phn100 Phase noise at 100 Hz offset -80.2 dBc/Hz

phn1k Phase noise at 1 kHz offset -114.3 dBc/Hz

phn10k Phase noise at 10 kHz offset -138 dBc/Hz

phn100k Phase noise at 100 kHz offset -143.9 dBc/Hz

phn1M Phase noise at 1 MHz offset -145.2 dBc/Hz

phn10M Phase noise at 10 MHz offset -146.5 dBc/Hz

phn20M Phase noise at 20 MHz offset -146.6 dBc/Hz

tRJIT Random additive jitter from 10 kHz to 20 MHz 65 fs, RMS

Product Folder Link(s): CDCLVD2102

l TEXAS INSTRUMENTS Wham Nmse lEI.ﬂmiB/RAF .70 nudnzjhz JD an Can-u wumwa MHz T3.) 743 ' 1 23.511552 MHz 455.4972 as: m: W cm )ul Cluck W . .. .»._ M >11 , W~ -, j H Inpul Cluck " * MW < "“1="" 11="" m="" m="" ,w="" a="" \fsdnmj="" melmlmlj="" om!="" momenta“="" 95m="" cms‘="" [phase="" nmse]="" stnp="" zn="" nhz="" .="" [phase="" nmse]="" center="" monsm="" mhz="" [phase="" mme]="" span="" 15.985331="" mhz="" [phase="" mme]="" noise="" [phase="" mmse]="" ana'lys‘s="" range="" x:="" aahd="" marks!="" [phase="" mmse]="" mamas="" range="" v:="" band="" marky="" [phase="" nmse]="" intg="" nmse:="" 42.15»:="" as:="" 19.52="" mhz="" [phase="" nmse]="" ms="" nms="" 58,2559="" wad="" [phase="" mme]="" 5.="" 2533="" mdeg="" mane]rmsj1mer:155.529fsec="" [phase="" mmse]="" rem-m="" m:="" 1.126="" w1="">

250

260

270

280

290

300

310

320

330

340

350

0 100 200 300 400 500 600 800

V Differential Output Voltage − mV

OD −

Frequency − MHz

700

T = 25 C

2.625V

2.5V

2.375V

CDCLVD2102

www.ti.com

SCAS904A –MAY 2010–REVISED JUNE 2010

TYPICAL CHARACTERISTICS

INPUT CLOCK AND OUTPUT CLOCK PHASE NOISES

FREQUENCY FROM THE CARRIER (TA= 25°C and VCC = 2.5V)

Input clock jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs

Figure 3. 100 MHz Input and Output Phase Noise Plot

Differential Output Voltage

Frequency

Figure 4.

Product Folder Link(s): CDCLVD2102

*9 TEXAS INSTRUMENTS v.‘ ————- ———————————————- — V.»

LVDS 100 WOscilloscope

LVDS

50 W

Phase Noise

Analyzer

OUTNx

OUTPx

80%

20%

0 V

trtf

VOD

VOH

VOL

V (= 2 x V )

OUT,DIFF,PP OD

CDCLVD2102

SCAS904A –MAY 2010–REVISED JUNE 2010

www.ti.com

TEST CONFIGURATIONS

Figure 5. LVDS Output DC Configuration During Device Test

Figure 6. LVDS Output AC Configuration During Device Test

Figure 7. DC Coupled LVCMOS Input During Device Test

Figure 8. Output Voltage and Rise/Fall Time

Product Folder Link(s): CDCLVD2102

*9 TEXAS INSTRUMENTS 75 X a, 35 a)? >C: 3“?

tPLH3

tPLH0 tPHL0

tPLH1 tPHL1

tPHL3

INPx

INNx

OUTP0

OUTN0

OUTP1

OUTN1

OUTP3

OUTN3

tPLH2 tPHL2

OUTP2

OUTN2

0V Differential

OUTPx

OUTNx

VOD

Vring

VOS

GND

CDCLVD2102

www.ti.com

SCAS904A –MAY 2010–REVISED JUNE 2010

A. Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn

or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, 3).

B. Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest

tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, 3).

C. Both inputs (IN0 and IN1) are phase aligned.

Figure 9. Output Skew and Part-to-Part Skew

Figure 10. Output Overshoot and Undershoot

Figure 11. Output AC Common Mode

Product Folder Link(s): CDCLVD2102

l TEXAS INSTRUMENTS 1.6 mm (min) OO 00:: 033 mm ((pr i T 05 mm (W) 4H 147 OT 1

FerriteBead

1 µF 10 µF 0.1 µF

Board

Supply

Chip

Supply

CDCLVD2102

SCAS904A –MAY 2010–REVISED JUNE 2010

www.ti.com

APPLICATION INFORMATION

THERMAL MANAGEMENT

For reliability and performance reasons, the die temperature should be limited to a maximum of 125°C.

The device package has an exposed pad that provides the primary heat removal path to the printed circuit board

(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a

ground plane must be incorporated into the PCB within the footprint of the package. The Thermal Pad must be

soldered down to ensure adequate heat conduction to of the package. Figure 12 shows a recommended land

and via pattern.

Figure 12. Recommended PCB Layout

POWER-SUPPLY FILTERING

High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the

additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when

jitter/phase noise is critical to applications.

Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass

capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system

against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required

by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors,

they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It

is recommended to add as many high-frequency (for example, 0.1 mF) bypass capacitors as there are supply

pins in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply

and the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these

beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with

very low dc resistance because it is imperative to provide adequate isolation between the board supply and the

chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required

for proper operation.

Figure 13. Power-Supply Decoupling

Product Folder Link(s): CDCLVD2102

l TEXAS INSTRUMENTS \ 1:50;: V 1:50;: 1 \ 1:50;: , 1:50;:

LVDS

Z = 50 W

CDCLVD2102 100 W

Z = 50 W

LVDS

Z = 50 W

CDCLVD2102

100 nF

Z = 50 W

100 W

100 nF

LVDS

Z = 50 W

CDCLVD2102

100 W

Z = 50 W

LVDS

Z = 50 W

CDCLVD2102

Z = 50 W

VAC_REF

50 W50 W

100 nF

CDCLVD2102

www.ti.com

SCAS904A –MAY 2010–REVISED JUNE 2010

LVDS OUTPUT TERMINATION

The proper LVDS termination for signal integrity over two 50 Ωlines is 100 Ωbetween the outputs on the

receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs. It is

recommended to place termination resister close to the receiver. If the receiver is internally biased to a voltage

different than the output common mode voltage of the CDCLVD2102, ac-coupling should be used. If the LVDS

receiver has internal 100 ohm termination, external termination must be omitted.

Unused outputs can be left open without connecting any trace to the output pins.

Figure 14. Output DC Termination

Figure 15. Output AC Termination With Receiver Internally Biased

INPUT TERMINATION

The CDCLVD2102 inputs can be interfaced with LVDS, LVPECL, or LVCMOS drivers.

LVDS Driver can be connected to CDCLVD2102 inputs with dc or ac coupling as shown Figure 16 and

Figure 17, respectively.

Figure 16. LVDS Clock Driver Connected to CDCLVD2102 Input (DC Coupled)

Figure 17. LVDS Clock Driver Connected to CDCLVD2102 Input (AC Coupled)

Product Folder Link(s): CDCLVD2102

l TEXAS INSTRUMENTS

VAC_REF

50 W

150 W

75 W

CDCLVD2102

Z = 50 W

LVPECL

100 nF

Z = 50 W

100 nF

75 W

150 W50 W

VIH +VIL

Vth =

CDCLVD2102

Z = 50 W

LVCMOS

(2.5V)

CDCLVD2102

SCAS904A –MAY 2010–REVISED JUNE 2010

www.ti.com

Figure 18 shows how to connect LVPECL inputs to the CDCLVD2102. The series resistors are required to

reduce the LVPECL signal swing if the signal swing is >1.6 VPP.

Figure 18. LVPECL Clock Driver Connected to CDCLVD2102 Input

Figure 19 illustrates how to couple a 2.5 V LVCMOS clock input to the CDCLVD2102 directly. The series

resistance (RS) should be placed close to the LVCMOS driver if needed. 3.3 V LVCMOS clock input swing needs

to be limited to VIH ≤VCC.

Figure 19. 2.5V LVCMOS Clock Driver Connected to CDCLVD2102 Input

If one of the buffers is used, then the other unused buffer should be disabled through the EN pin, and the unused

input pins should be grounded by 1kΩresistors.

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CDCLVD2102

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SCAS904A –MAY 2010–REVISED JUNE 2010

REVISION HISTORY

Changes from Original (May 2010) to Revision A Page

• Changed Features bullet From: ESD Protection Exceeds 2kV HBM, 500V CDM To: ESD Protection Exceeds 3 kV

HBM, 1 kV CDM ................................................................................................................................................................... 1

• Electrostatic discharge was <2000 ....................................................................................................................................... 3

•ΔVOD values, MIN was-50, MAX was 50 .............................................................................................................................. 5

• VOC(SS) MIN value was 1.125 ................................................................................................................................................ 5

•ΔVOC(SS) values, MIN was-50, MAX was 50 .......................................................................................................................... 5

• Vring MAX value was 20% ..................................................................................................................................................... 5

• VOS values, TYP was 30, MAX was 100 ............................................................................................................................... 5

• tPD MAX value was 2 ............................................................................................................................................................. 5

• tSK, PP - deleted the TYP value of 300 ................................................................................................................................... 5

• tR/tFMIN value was 200 ........................................................................................................................................................ 5

• ICCSTAT MAX value was 42 .................................................................................................................................................... 5

• Added new paragraph following Figure 19 ......................................................................................................................... 12

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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

CDCLVD2102RGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 D2102

CDCLVD2102RGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 D2102

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

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Addendum-Page 2

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension desIgned Io eeeemmodaIe me component Iengm K0 Dlmenslun desIgned to accommodate me componem Ihlckness 7 w Overall with loe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

CDCLVD2102RGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 1-Sep-2021

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CDCLVD2102RGTR VQFN RGT 16 3000 350.0 350.0 43.0

PACKAGE MATERIALS INFORMATION

www.ti.com 1-Sep-2021

Pack Materials-Page 2

GENERIC PACKAGE VIEW RGT 16 VQFN - 1 mm max heigm PLASTIC QUAD FLATPACKV N0 LEAD Images above are jusl a represenlalion of the package family, aclual package may vary Refel lo the product dala sheel for package details. 4203495” I TEXAS INSTRI IMFNTS

‘n ‘ ‘D ,, + ,

www.ti.com

PACKAGE OUTLINE

16X 0.30

0.18

1.66 0.1

16X 0.5

0.3

1.0

0.8

(0.1) TYP

0.05

0.00

12X 0.5

1.5

A3.15

2.85 B

3.15

2.85

VQFN - 1 mm max heightRGT0016P

PLASTIC QUAD FLATPACK - NO LEAD

4228232/A 11/2021

PIN 1 INDEX AREA

0.08

SEATING PLANE

16 13

X 0.35)(45PIN 1 ID 0.1 C A B

0.05

EXPOSED

THERMAL PAD

17 SYMM

SYMM

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 3.600

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EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

16X (0.24)

16X (0.6)

( 0.2) TYP

VIA

12X (0.5)

(2.8)

(0.58)

TYP

( 1.66)

(R0.05)

ALL PAD CORNERS (0.58) TYP

VQFN - 1 mm max heightRGT0016P

PLASTIC QUAD FLATPACK - NO LEAD

4228232/A 11/2021

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

EXPOSED

METAL

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EXAMPLE STENCIL DESIGN

16X (0.6)

16X (0.24)

12X (0.5)

(2.8)

( 1.51)

(R0.05) TYP

VQFN - 1 mm max heightRGT0016P

PLASTIC QUAD FLATPACK - NO LEAD

4228232/A 11/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SYMM

ALL AROUND

METAL

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

84% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

SYMM

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