Scheda tecnica PCF85176 di NXP USA Inc.

Commenti/errori della scheda tecnica

Table 24 on page 49

1. General description

The PCF85176 is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or

multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily

cascaded for larger LCD applications. The PCF85176 is compatible with most

microcontrollers and communicates via the two-line bidirectional I2C-bus. Communication

overheads are minimized by a display RAM with auto-incremented addressing, by

hardware subaddressing, and by display memory switching (static and duplex drive

modes).

For a selection of NXP LCD segment drivers, see Table 24 on page 49.

2. Features and benefits

Single chip LCD controller and driver

Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing

Selectable display bias configuration: static, 1⁄2, or 1⁄3

Internal LCD bias generation with voltage-follower buffers

40 segment drives:

Up to 20 7-segment numeric characters

Up to 10 14-segment alphanumeric characters

Any graphics of up to 160 segments/elements

40  4-bit RAM for display data storage

Auto-incremented display data loading across device subaddress boundaries

Display memory bank switching in static and duplex drive modes

Versatile blinking modes

Independent supplies possible for LCD and logic voltages

Wide power supply range: from 1.8 V to 5.5 V

Wide logic LCD supply range:

From 2.5 V for low-threshold LCDs

Up to 6.5 V for guest-host LCDs and high-threshold twisted nematic LCDs

Low power consumption

400 kHz I2C-bus interface

May be cascaded for large LCD applications (up to 2560 segments/elements possible)

No external components required

Manufactured in silicon gate CMOS process

PCF85176

40 x 4 universal LCD driver for low multiplex rates

Rev. 5 — 6 January 2015 Product data sheet

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.

Product data sheet Rev. 5 — 6 January 2015 2 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

3. Ordering information

3.1 Ordering options

4. Marking

Table 1. Ordering information

Type number Package

Name Description Version

PCF85176H TQFP64 plastic thin quad flat package, 64 leads;

body 10 10 1.0 mm SOT357-1

PCF85176T TSSOP56 plastic thin shrink small outline package,

56 leads; body width 6.1 mm SOT364-1

Table 2. Ordering options

Product type number Sales item (12NC) Orderable part number IC

revision Delivery form

PCF85176H/1 935290063518 PCF85176H/1,518 1 tape and reel, 13 inch, dry pack

PCF85176T/1 935290075118 PCF85176T/1,118 1 tape and reel, 13 inch

Table 3. Marking codes

Product type number Marking code

PCF85176H/1 PCF85176H

PCF85176T/1 PCF85176T

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Product data sheet Rev. 5 — 6 January 2015 3 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

5. Block diagram

Fig 1. Block diagram of PCF85176

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Product data sheet Rev. 5 — 6 January 2015 4 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

6. Pinning information

6.1 Pinning

Top view. For mechanical details, see Figure 29. Top view. For mechanical details, see Figure 30.

Fig 2. Pinning diagram for TQFP64 (PCF85176H) Fig 3. Pinning diagram for TSSOP56 (PCF85176T)

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Product data sheet Rev. 5 — 6 January 2015 5 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

6.2 Pin description

Table 4. Pin description

Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.

Symbol Pin Description

TQFP64

(PCF85176H) TSSOP56

(PCF85176T) Type

SDA 10 44 input/output I2C-bus serial data line

SCL 11 45 input I2C-bus serial clock

CLK 13 47 input/output clock line

VDD 14 48 supply supply voltage

SYNC 12 46 input/output cascade synchronization

input or output; if not used

it must be left open

OSC 15 49 input internal oscillator enable

A0 to A2 16 to 18 50 to 52 input subaddress inputs

SA0 19 53 input I2C-bus address input

VSS 20 54 supply ground supply voltage

VLCD 21 55 supply LCD supply voltage

BP0, BP2,

BP1, BP3 25 to 28 56, 1, 2, 3 output LCD backplane outputs

S0 to S39 29 to 32, 34 to 47,

49 to 64, 2 to 7 4 to 43 output LCD segment outputs

n.c. 1, 8, 9, 22 to 24,

33, 48 - - not connected; do not

connect and do not use as

feed through

Figure 4 Table 5 Table 7 Table 8 Table 9 Table 10 Table 11 Figure 22 Table 6

Product data sheet Rev. 5 — 6 January 2015 6 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

7. Functional description

The PCF85176 is a versatile peripheral device designed to interface between any

microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 4). It

can directly drive any static or multiplexed LCD containing up to four backplanes and up to

40 segments.

7.1 Commands of PCF85176

The commands available to the PCF85176 are defined in Table 5.

All available commands carry a continuation bit C in their most significant bit position as

shown in Figure 22. When this bit is set logic 1, it indicates that the next byte of the

transfer to arrive will also represent a command. If this bit is set logic 0, it indicates that

the command byte is the last in the transfer. Further bytes are regarded as display data

(see Table 6).

Table 5. Definition of PCF85176 commands

Bit position labeled as - is not used.

Command Operation Code Reference

Bit 76543210

mode-set C 1 0 - E B M[1:0] Table 7

load-data-pointer C 0 P[5:0] Table 8

device-select C1100A[2:0] Table 9

bank-select C 1 1 1 1 0 I O Table 10

blink-select C 1 1 1 0 AB BF[1:0] Table 11

Table 6. C bit description

Bit Symbol Value Description

7C continue bit

0 last control byte in the transfer; next byte will be regarded

as display data

1 control bytes continue; next byte will be a command too

Section 7. 6. 1

Product data sheet Rev. 5 — 6 January 2015 7 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

7.1.1 Command: mode-set

The mode-set command allows configuring the multiplex mode, the bias levels and

enabling or disabling the display.

[1] The possibility to disable the display allows implementation of blinking under external control.

[2] Default value.

[3] The display is disabled by setting all backplane and segment outputs to VLCD.

[4] Not applicable for static drive mode.

7.1.2 Command: load-data-pointer

The load-data-pointer command defines the display RAM address where the following

display data are sent to.

[1] Default value.

Table 7. Mode-set command bit description

Bit Symbol Value Description

7C0, 1see Table 6

6 to 5 - 10 fixed value

4 - - unused

3E display status[1]

0[2] disabled (blank)[3]

1 enabled

2B LCD bias configuration[4]

0[2] 1⁄3 bias

11⁄2 bias

1 to 0 M[1:0] LCD drive mode selection

01 static; BP0

10 1:2 multiplex; BP0, BP1

11 1:3 multiplex; BP0, BP1, BP2

00[2] 1:4 multiplex; BP0, BP1, BP2, BP3

Table 8. Load-data-pointer command bit description

See Section 7.6.1.

Bit Symbol Value Description

7C0, 1see Table 6

6 - 0 fixed value

5 to 0 P[5:0] 000000[1] to

100111 6-bit binary value, 0 to 39; transferred to the data pointer to

define one of 40 display RAM addresses

Section 7. 6.2

Product data sheet Rev. 5 — 6 January 2015 8 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

7.1.3 Command: device-select

The device-select command allows defining the subaddress counter value.

[1] Default value.

7.1.4 Command: bank-select

The bank-select command controls where data is written to RAM and where it is displayed

from.

[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.

[2] Default value.

Table 9. Device-select command bit description

See Section 7.6.2.

Bit Symbol Value Description

7C0, 1see Table 6

6 to 3 - 1100 fixed value

2 to 0 A[2:0] 000[1] to 111 3-bit binary value, 0 to 7; transferred to the subaddress

counter to define 1 of 8 hardware subaddresses

Table 10. Bank-select command bit description

See Section 7.6.5.

Bit Symbol Value Description

Static 1:2 multiplex[1]

7 C 0, 1 see Table 6

6 to 2 - 11110 fixed value

1I input bank selection; storage of arriving display data

0[2] RAM row 0 RAM rows 0 and 1

1 RAM row 2 RAM rows 2 and 3

0O output bank selection; retrieval of LCD display data

0[2] RAM row 0 RAM rows 0 and 1

1 RAM row 2 RAM rows 2 and 3

Section 7.1.5.1 Table 11 6% Table 7

Product data sheet Rev. 5 — 6 January 2015 9 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

7.1.5 Command: blink-select

The blink-select command allows configuring the blink mode and the blink frequency.

[1] Default value.

[2] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.

[3] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.

7.1.5.1 Blinking

The display blinking capabilities of the PCF85176 are very versatile. The whole display

can blink at frequencies selected by the blink-select command (see Table 11). The blink

frequencies are derived from the clock frequency. The ratio between the clock and blink

frequencies depends on the blink mode selected (see Table 12).

An additional feature is for an arbitrary selection of LCD segments/elements to blink. This

applies to the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. With the output bank selector, the displayed RAM banks are

exchanged with alternate RAM banks at the blink frequency. This mode can also be

specified by the blink-select command.

In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of

LCD segments/elements can blink by selectively changing the display RAM data at fixed

time intervals.

The entire display can blink at a frequency other than the nominal blink frequency. This

can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 7).

Table 11. Blink-select command bit description

See Section 7.1.5.1.

Bit Symbol Value Description

7C0, 1see Table 6

6 to 3 - 1110 fixed value

2AB blink mode selection

0[1] normal blinking[2]

1 alternate RAM bank blinking[3]

1 to 0 BF[1:0] blink frequency selection

00[1] off

01 1

10 2

11 3

Table 7

Product data sheet Rev. 5 — 6 January 2015 10 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

[1] The blink frequency is proportional to the clock frequency (fclk). For the range of the clock frequency, see

Table 20.

7.2 Power-On Reset (POR)

At power-on the PCF85176 resets to the following starting conditions:

•All backplane and segment outputs are set to VLCD

•The selected drive mode is: 1:4 multiplex with 1⁄3 bias

•Blinking is switched off

•Input and output bank selectors are reset

•The I2C-bus interface is initialized

•The data pointer and the subaddress counter are cleared (set to logic 0)

•The display is disabled (bit E = 0, see Table 7)

Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow

the reset action to complete.

Table 12. Blink frequencies

Blink mode Blink frequency[1]

off -

fblink

fclk

768

----------

fblink

fclk

1536

-------------

fblink

fclk

3072

-------------

n Table 13 Figure 5 o /| 5 - - k 4 913355312

Product data sheet Rev. 5 — 6 January 2015 11 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

7.3 Possible display configurations

The possible display configurations of the PCF85176 depend on the number of active

backplane outputs required. A selection of display configurations is shown in Table 13. All

of these configurations can be implemented in the typical system shown in Figure 5.

[1] 7 segment display has 8 segments/elements including the decimal point.

[2] 14 segment display has 16 segments/elements including decimal point and accent dot.

Fig 4. Example of displays suitable for PCF85176

Table 13. Selection of possible display configurations

Number of

Backplanes Icons Digits/Characters Dot matrix:

segments/

elements

7-segment[1] 14-segment[2]

4 160 20 10 160 (4  40)

3 120 15 7 120 (3  40)

28010580 (2  40)

1405240 (1  40)

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Product data sheet Rev. 5 — 6 January 2015 12 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

The host microcontroller maintains the 2-line I2C-bus communication channel with the

PCF85176. The internal oscillator is enabled by connecting pin OSC to pin VSS. The

appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.

The only other connections required to complete the system are the power supplies (VDD,

VSS, and VLCD) and the LCD panel chosen for the application.

7.3.1 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider of three

impedances connected between VLCD and VSS. The center impedance is bypassed by

switch if the 1⁄2bias voltage level for the 1:2 multiplex drive mode configuration is

selected.

7.3.2 Display register

The display register holds the display data while the corresponding multiplex signals are

generated.

7.3.3 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

mode-set command from the command decoder. The biasing configurations that apply to

the preferred modes of operation, together with the biasing characteristics as functions of

VLCD and the resulting discrimination ratios (D) are given in Table 14.

Discrimination is a term which is defined as the ratio of the on and off RMS voltage across

a segment. It can be thought of as a measurement of contrast.

The resistance of the power lines must be kept to a minimum.

Fig 5. Typical system configuration

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Table 14. Biasing characteristics

LCD drive

mode Number of: LCD bias

configuration

Backplanes Levels

static 1 2 static 0 1 

1:2 multiplex 2 3 1⁄20.354 0.791 2.236

1:2 multiplex 2 4 1⁄30.333 0.745 2.236

1:3 multiplex 3 4 1⁄30.333 0.638 1.915

1:4 multiplex 4 4 1⁄30.333 0.577 1.732

Voff RMS

VLCD

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Von RMS

VLCD

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DVon RMS

Voff RMS

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Equation 1 Equation 2 Equation 3 Eguation 3 J3 J? 3 J75 [w]

Product data sheet Rev. 5 — 6 January 2015 13 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD

threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode, a suitable choice is VLCD >3V

th(off).

Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and

hence the contrast ratios are smaller.

Bias is calculated by , where the values for a are

a = 1 for 1⁄2 bias

a = 2 for 1⁄3 bias

The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:

(1)

where the values for n are

n = 1 for static drive mode

n = 2 for 1:2 multiplex drive mode

n = 3 for 1:3 multiplex drive mode

n = 4 for 1:4 multiplex drive mode

The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:

(2)

Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:

(3)

Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with

1⁄2bias is and the discrimination for an LCD drive mode of 1:4 multiplex with

1⁄2bias is .

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD

as follows:

•1:3 multiplex (1⁄2 bias):

•1:4 multiplex (1⁄2 bias):

These compare with when 1⁄3 bias is used.

VLCD is sometimes referred as the LCD operating voltage.

1a+

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n1a+

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Voff RMS

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

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DVon RMS

Voff RMS

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VLCD 6V

off RMS

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VLCD 43

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VLCD 3Voff RMS

Figure 6 \v m Equation 1 0 Equation 3 011335494

Product data sheet Rev. 5 — 6 January 2015 14 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

7.3.3.1 Electro-optical performance

Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The

RMS voltage, at which a pixel is switched on or off, determine the transmissibility of the

pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative

transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see

Figure 6. For a good contrast performance, the following rules should be followed:

(4)

(5)

Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection

of a, n (see Equation 1 to Equation 3) and the VLCD voltage.

Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module

manufacturer. Vth(off) is sometimes named Vth. Vth(on) is sometimes named saturation

voltage Vsat.

It is important to match the module properties to those of the driver in order to achieve

optimum performance.

Fig 6. Electro-optical characteristic: relative transmission curve of the liquid

Von RMS

Vth on



Voff RMS

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Product data sheet Rev. 5 — 6 January 2015 15 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

7.3.4 LCD drive mode waveforms

7.3.4.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD. The

backplane (BPn) and segment (Sn) drive waveforms for this mode are shown in Figure 7.

Vstate1(t) = VSn(t)  VBP0(t).

Von(RMS) = VLCD.

Vstate2(t) = V(Sn + 1)(t)  VBP0(t).

Voff(RMS) = 0 V.

Fig 7. Static drive mode waveforms

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Product data sheet Rev. 5 — 6 January 2015 16 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

7.3.4.2 1:2 Multiplex drive mode

When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The

PCF85176 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 8 and

Figure 9.

Vstate1(t) = VSn(t)  VBP0(t).

Von(RMS) = 0.791VLCD.

Vstate2(t) = VSn(t)  VBP1(t).

Voff(RMS) = 0.354VLCD.

Fig 8. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias

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Product data sheet Rev. 5 — 6 January 2015 17 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

Vstate1(t) = VSn(t)  VBP0(t).

Von(RMS) = 0.745VLCD.

Vstate2(t) = VSn(t)  VBP1(t).

Voff(RMS) = 0.333VLCD.

Fig 9. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias

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Product data sheet Rev. 5 — 6 January 2015 18 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

7.3.4.3 1:3 Multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as

shown in Figure 10.

Vstate1(t) = VSn(t)  VBP0(t).

Von(RMS) = 0.638VLCD.

Vstate2(t) = VSn(t)  VBP1(t).

Voff(RMS) = 0.333VLCD.

Fig 10. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias

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Product data sheet Rev. 5 — 6 January 2015 19 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

7.3.4.4 1:4 Multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as

shown in Figure 11.

Vstate1(t) = VSn(t)  VBP0(t).

Von(RMS) = 0.577VLCD.

Vstate2(t) = VSn(t)  VBP1(t).

Voff(RMS) = 0.333VLCD.

Fig 11. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias

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Product data sheet Rev. 5 — 6 January 2015 20 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

7.4 Oscillator

7.4.1 Internal clock

The internal logic of the PCF85176 and its LCD drive signals are timed either by its

internal oscillator or by an external clock. The internal oscillator is enabled by connecting

pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used

as the clock signal for several PCF85176 in the system that are connected in cascade.

7.4.2 External clock

Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD

frame frequency is determined by the clock frequency (fclk).

Remark: A clock signal must always be supplied to the device. Removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.4.3 Timing

The PCF85176 timing controls the internal data flow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. In cascaded

applications, the correct timing relationship between each PCF85176 in the system is

maintained by the synchronization signal at pin SYNC. The timing also generates the LCD

frame frequency signal. The frame frequency signal is a fixed division of the clock

frequency from either the internal or an external clock:

7.5 Backplane and segment outputs

7.5.1 Backplane outputs

The LCD drive section includes 4 backplane outputs BP0 to BP3 which must be

connected directly to the LCD. The backplane output signals are generated in accordance

with the selected LCD drive mode. If less than four backplane outputs are required, the

unused outputs can be left open-circuit.

•In 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities

•In 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 all carry the

same signals and may also be paired to increase the drive capabilities

•In static drive mode, the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements

7.5.2 Segment outputs

The LCD drive section includes 40 segment outputs S0 to S39 which should be

connected directly to the LCD. The segment output signals are generated in accordance

with the multiplexed backplane signals and with data residing in the display register. When

less than 40 segment outputs are required, the unused segment outputs should be left

open-circuit.

ffr

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-------

Figure 12 mbe525 Figure 13

Product data sheet Rev. 5 — 6 January 2015 21 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

7.6 Display RAM

The display RAM is a static 40  4-bit RAM which stores LCD data.

There is a one-to-one correspondence between

•the bits in the RAM bitmap and the LCD segments/elements

•the RAM columns and the segment outputs

•the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;

similarly, a logic 0 indicates the off-state.

The display RAM bitmap, Figure 12, shows the rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the

segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,

second, third, and fourth row of the display RAM are time-multiplexed with BP0, BP1,

BP2, and BP3 respectively.

When display data is transmitted to the PCF85176, the display bytes received are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and depending on the current multiplex drive mode the bits are stored singularly,

in pairs, triples, or quadruples. To illustrate the filling order, an example of a 7-segment

display showing all drive modes is given in Figure 13. The RAM filling organization

depicted applies equally to other LCD types.

•In static drive mode the eight transmitted data bits are placed into row 0 as 1 byte

•In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into

row 0 and 1 as four successive 2-bit RAM words

•In 1:3 multiplex drive mode the 8 bits are placed in triples into row 0, 1, and 2 as three

successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is not

recommended to use this bit in a display because of the difficult addressing. This last

bit may, if necessary, be controlled by an additional transfer to this address, but care

should be taken to avoid overwriting adjacent data because always full bytes are

transmitted (see Section 7.6.3)

•In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples

into row 0, 1, 2, and 3 as two successive 4-bit RAM words

The display RAM bitmap shows the direct relationship between the display RAM column and the

segment outputs; and between the bits in a RAM row and the backplane outputs.

Fig 12. Display RAM bitmap

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Product data sheet Rev. 5 — 6 January 2015 22 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

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Fig 13. Relationship between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus

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Product data sheet Rev. 5 — 6 January 2015 23 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

7.6.1 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer command (see Table 8). Following this command, an

arriving data byte is stored at the display RAM address indicated by the data pointer. The

filling order is shown in Figure 13.

After each byte is stored, the content of the data pointer is automatically incremented by a

value dependent on the selected LCD drive mode:

•In static drive mode by eight

•In 1:2 multiplex drive mode by four

•In 1:3 multiplex drive mode by three

•In 1:4 multiplex drive mode by two

If an I2C-bus data access terminates early, then the state of the data pointer is unknown.

Consequently, the data pointer must be rewritten prior to further RAM accesses.

7.6.2 Subaddress counter

The storage of display data is determined by the contents of the subaddress counter.

Storage is allowed only when the content of the subaddress counter matches with the

hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined

by the device-select command (see Table 9). If the content of the subaddress counter and

the hardware subaddress do not match, then data storage is inhibited but the data pointer

is incremented as if data storage had taken place. The subaddress counter is also

incremented when the data pointer overflows.

The storage arrangements described lead to extremely efficient data loading in cascaded

applications. When a series of display bytes are sent to the display RAM, automatic

wrap-over to the next PCF85176 occurs when the last RAM address is exceeded.

Subaddressing across device boundaries is successful even if the change to the next

device in the cascade occurs within a transmitted character.

The hardware subaddress must not be changed while the device is being accessed on the

I2C-bus interface.

Table 15 Figure 13 Table 16 n Table 16 Seclion 7.6.1 on gage 23

Product data sheet Rev. 5 — 6 January 2015 24 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

7.6.3 RAM writing in 1:3 multiplex drive mode

In 1:3 multiplex drive mode, the RAM is written as shown in Table 15 (see Figure 13 as

well).

If the bit at position BP2/S2 would be written by a second byte transmitted, then the

mapping of the segment bits would change as illustrated in Table 16.

In the case described in Table 16, the RAM has to be written entirely and BP2/S2,

BP2/S5, BP2/S8 etc. have to be connected to segments/elements on the display. This can

be achieved by a combination of writing and rewriting the RAM like follows:

•In the first write to the RAM, bits a7 to a0 are written

•The data-pointer (see Section 7.6.1 on page 23) has to be set to the address of bit a1

•In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7

and b6

•The data-pointer has to be set to the address of bit b1

•In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and

Depending on the method of writing to the RAM (standard or entire filling by rewriting),

some segments/elements remain unused or can be used, but it has to be considered in

the module layout process as well as in the driver software design.

Table 15. Standard RAM filling in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any segments/elements on the

display.

Display RAM

bits (rows)/

backplane

outputs (BPn)

Display RAM addresses (columns)/segment outputs (Sn)

0123456789:

0a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 :

1a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 :

2a5 a2 - b5 b2 - c5 c2 - d5 :

3----------:

Table 16. Entire RAM filling by rewriting in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to segments/elements on the display.

Display RAM

bits (rows)/

backplane

outputs (BPn)

Display RAM addresses (columns)/segment outputs (Sn)

0123456789:

0a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4 :

1a6 a3 a0/b6 b3 b0/c6 c3 c0/d6 d3 d0/e6 e3 :

2a5 a2 b5 b2 c5 c2 d5 d2 e5 e2 :

3----------:

Table 10 Table 10 Figure 14

Product data sheet Rev. 5 — 6 January 2015 25 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

7.6.4 Writing over the RAM address boundary

In all multiplex drive modes, depending on the setting of the data pointer, it is possible to

fill the RAM over the RAM address boundary. If the PCF85176 is part of a cascade the

additional bits fall into the next device that also generates the acknowledge signal. If the

PCF85176 is a single device or the last device in a cascade, the additional bits are

discarded and no acknowledge signal is generated.

7.6.5 Bank selection

7.6.5.1 Output bank selector

The output bank selector (see Table 10) selects one of the four rows per display RAM

address for transfer to the display register. The actual row selected depends on the

selected LCD drive mode in operation and on the instant in the multiplex sequence.

•In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by

the contents of row 1, 2, and then 3

•In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially

•In 1:2 multiplex mode, rows 0 and 1 are selected

•In static mode, row 0 is selected

The PCF85176 includes a RAM bank switching feature in the static and 1:2 multiplex drive

modes. In the static drive mode, the bank-select command may request the contents of

row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex mode,

the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the

provision for preparing display information in an alternative bank and to be able to switch

to it once it is assembled.

7.6.5.2 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the

selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode

or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see

Table 10). The input bank selector functions independently to the output bank selector.

7.6.5.3 RAM bank switching

The PCF85176 includes a RAM bank switching feature in the static and 1:2 multiplex drive

modes. A bank can be thought of as one RAM row or a collection of RAM rows (see

Figure 14). The RAM bank switching gives the provision for preparing display information

in an alternative bank and to be able to switch to it once it is complete.

ass-004787 Figure 14 Table 10 on gage 8 Figure 15 Figure 16

Product data sheet Rev. 5 — 6 January 2015 26 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

There are two banks; bank 0 and bank 1. Figure 14 shows the location of these banks

relative to the RAM map. Input and output banks can be set independently from one

another with the Bank-select command (see Table 10 on page 8). Figure 15 shows the

concept.

In the static drive mode, the bank-select command may request the contents of row 2 to

be selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the

contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the

provision for preparing display information in an alternative bank and to be able to switch

to it once it is assembled.

In Figure 16 an example is shown for 1:2 multiplex drive mode where the displayed data is

read from the first two rows of the memory (bank 0), while the transmitted data is stored in

the second two rows of the memory (bank 1).

Fig 14. RAM banks in static and multiplex driving mode 1:2

Fig 15. Bank selection

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Product data sheet Rev. 5 — 6 January 2015 27 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

Fig 16. Example of the Bank-select command with multiplex drive mode 1:2

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Product data sheet Rev. 5 — 6 January 2015 28 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

8. Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time is

interpreted as a control signal (see Figure 17).

8.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P.

The START and STOP conditions are illustrated in Figure 18.

8.3 System configuration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves. The system configuration is shown in Figure 19.

Fig 17. Bit transfer

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Product data sheet Rev. 5 — 6 January 2015 29 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

8.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge

cycle.

•A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte

•A master receiver must generate an acknowledge after the reception of each byte that

has been clocked out of the slave transmitter

•The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered)

•A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition

Acknowledgement on the I2C-bus is illustrated in Figure 20.

Fig 19. System configuration

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Product data sheet Rev. 5 — 6 January 2015 30 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

8.5 I2C-bus controller

The PCF85176 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or

transmit data to an I2C-bus master receiver. The only data output from the PCF85176 are

the acknowledge signals of the selected devices. Device selection depends on the

I2C-bus slave address, on the transferred command data and on the hardware

subaddress.

In single device applications, the hardware subaddress inputs A0, A1, and A2 are

normally tied to VSS which defines the hardware subaddress 0. In multiple device

applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that

no two devices with a common I2C-bus slave address have the same hardware

subaddress.

8.6 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

8.7 I2C-bus protocol

Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the

PCF85176. The entire I2C-bus slave address byte is shown in Table 17.

The PCF85176 is a write-only device and is not responding to a read access, therefore bit

0 should always be logic 0. Bit 1 of the slave address byte that a PCF85176 responds to,

is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).

Having two reserved slave addresses allows the following on the same I2C-bus:

•Up to 16 PCF85176 for very large LCD applications

•The use of two types of LCD multiplex drive modes

The I2C-bus protocol is shown in Figure 21. The sequence is initiated with a START

condition (S) from the I2C-bus master which is followed by one of the two possible

PCF85176 slave addresses available. All PCF85176 whose SA0 inputs correspond to

bit 0 of the slave address respond by asserting an acknowledge in parallel. This I2C-bus

transfer is ignored by all PCF85176 whose SA0 inputs are set to the alternative level.

Table 17. I2C slave address byte

Slave address

Bit 7 6 5 4 3 2 1 0

MSB LSB

011100SA0R/W

\ \ | \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5 013mm Figure 22

Product data sheet Rev. 5 — 6 January 2015 31 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

After an acknowledgement, one or more command bytes follow that define the status of

each addressed PCF85176.

The last command byte sent is identified by resetting its most significant bit, continuation

bit C (see Figure 22). The command bytes are also acknowledged by all addressed

PCF85176 on the bus.

After the last command byte, one or more display data bytes may follow. Display data

bytes are stored in the display RAM at the address specified by the data pointer and the

subaddress counter. Both data pointer and subaddress counter are automatically updated

and the data directed to the intended PCF85176 device.

An acknowledgement after each byte is asserted only by the PCF85176 that are

addressed via address lines A0, A1, and A2. After the last display byte, the I2C-bus

master asserts a STOP condition (P). Alternately a START may be asserted to restart an

I2C-bus access.

Fig 21. I2C-bus protocol

Fig 22. Format of command byte

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Product data sheet Rev. 5 — 6 January 2015 32 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

9. Internal circuitry

Fig 23. Device protection circuits

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Product data sheet Rev. 5 — 6 January 2015 33 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

10. Safety notes

11. Limiting values

[1] Pass level; Human Body Model (HBM), according to Ref. 6 “JESD22-A114”

[2] Pass level; Charged-Device Model (CDM), according to Ref. 7 “JESD22-C101”

[3] Pass level; latch-up testing according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max)).

[4] According to the store and transport requirements (see Ref. 13 “UM10569”) the devices have to be stored at a temperature of +8 C to

+45 C and a humidity of 25 % to 75 %.

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling

electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or

equivalent standards.

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.

Table 18. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +6.5 V

VLCD LCD supply voltage 0.5 +7.5 V

VIinput voltage on each of the pins CLK, SDA,

SCL, SYNC, SA0, OSC, A0 to A2

0.5 +6.5 V

VOoutput voltage on each of the pins S0 to S39,

BP0 to BP3

0.5 +7.5 V

IIinput current 10 +10 mA

IOoutput current 10 +10 mA

IDD supply current 50 +50 mA

IDD(LCD) LCD supply current 50 +50 mA

ISS ground supply current 50 +50 mA

Ptot total power dissipation - 400 mW

Pooutput power - 100 mW

VESD electrostatic

discharge voltage HBM [1] -3500 V

CDM

TQFP64 (PCF85176H) [2] -1000 V

TSSOP56 (PCF85176T) [2] -2000 V

Ilu latch-up current [3] -100mA

Tstg storage temperature [4] 55 +150 C

Tamb ambient temperature operating device 40 +85 C

Product data sheet Rev. 5 — 6 January 2015 34 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

12. Static characteristics

[1] VLCD > 3 V for 1⁄3 bias.

[2] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.

[3] For typical values, see Figure 24.

[4] The I2C-bus interface of the PCF85176 is 5 V tolerant.

[5] When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 18 (see Figure 23

as well).

[6] Propagation delay of driver between clock (CLK) and LCD driving signals.

[7] Periodically sampled, not 100 % tested.

[8] Outputs measured one at a time.

Table 19. Static characteristics

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage 1.8 - 5.5 V

VLCD LCD supply voltage [1] 2.5- 6.5V

IDD supply current fclk(ext) = 1536 Hz [2][3] -3.57A

VDD =3.0V; T

amb =25C-2.7-A

IDD(LCD) LCD supply current fclk(ext) = 1536 Hz [2] -2332A

VLCD =3.0V; T

amb =25C-13-A

Logic[4]

VP(POR) power-on reset supply

voltage 1.01.31.6V

VIL LOW-level input

voltage on pins CLK, SYNC, OSC, A0 to

A2, SA0, SCL, SDA VSS -0.3V

DD V

VIH HIGH-level input

voltage on pins CLK, SYNC, OSC, A0 to

A2, SA0, SCL, SDA

[5][6] 0.7VDD -V

DD V

IOL LOW-level output

current output sink current;

VOL =0.4V; V

DD =5V

on pins CLK and SYNC 1- - mA

on pin SDA 3 - - mA

IOH(CLK) HIGH-level output

current on pin CLK output source current;

VOH =4.6V; V

DD =5V 1- - mA

ILleakage current VI=V

DD or VSS;

on pins CLK, SCL, SDA, A0 to A2

and SA0

1- +1A

IL(OSC) leakage current on pin

OSC VI=V

DD 1- +1A

CIinput capacitance [7] --7pF

LCD outputs

VOoutput voltage

variation on pins BP0 to BP3 and

S0 to S39

100 - +100 mV

ROoutput resistance VLCD = 5 V [8]

on pins BP0 to BP3 - 1.5 - k

on pins S0 to S39 - 6.0 - k

Product data sheet Rev. 5 — 6 January 2015 35 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

Tamb =30C; 1:4 multiplex drive mode; VLCD = 6.5 V; fclk(ext) = 1.536 kHz; all RAM written with

logic 1; no display connected; I2C-bus inactive.

Fig 24. Typical IDD with respect to VDD

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Product data sheet Rev. 5 — 6 January 2015 36 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

13. Dynamic characteristics

Table 20. Dynamic characteristics

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Clock

fclk(int) internal clock

frequency

[1] 1440 1850 2640 Hz

fclk(ext) external clock

frequency 960 - 2640 Hz

ffr frame frequency internal clock 60 77 110 Hz

external clock 40 - 110 Hz

tclk(H) HIGH-level clock time 60 - - s

tclk(L) LOW-level clock time 60 - - s

Synchronization

tPD(SYNC_N) SYNC propagation

delay -30-ns

tSYNC_NL SYNC LOW time 1 - - s

tPD(drv) driver propagation

delay VLCD = 5 V [2] --30s

I2C-bus[3]

Pin SCL

fSCL SCL clock frequency - - 400 kHz

tLOW LOW period of the

SCL clock 1.3 - - s

tHIGH HIGH period of the

SCL clock 0.6 - - s

Pin SDA

tSU;DAT data set-up time 100 - - ns

tHD;DAT data hold time 0 - - ns

Pins SCL and SDA

tBUF bus free time between

a STOP and START

condition

1.3 - - s

tSU;STO set-up time for STOP

condition 0.6 - - s

tHD;STA hold time (repeated)

START condition 0.6 - - s

tSU;STA set-up time for a

repeated START

condition

0.6 - - s

trrise time of both SDA

and SCL signals fSCL = 400 kHz - - 0.3 s

fSCL < 125 kHz - - 1.0 s

\ L

Product data sheet Rev. 5 — 6 January 2015 37 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

[1] Typical output duty factor: 50 % measured at the CLK output pin.

[2] Not tested in production.

[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an

input voltage swing of VSS to VDD.

tffall time of both SDA

and SCL signals --0.3s

Cbcapacitive load for

each bus line --400pF

tw(spike) spike pulse width on the I2C-bus - - 50 ns

Table 20. Dynamic characteristics …continued

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Fig 25. Driver timing waveforms

Fig 26. I2C-bus timing waveforms

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Product data sheet Rev. 5 — 6 January 2015 38 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

14. Application information

14.1 Cascaded operation

Large display configurations of up to 16 PCF85176 can be recognized on the same

I2C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable

I2C-bus slave address (SA0).

When cascaded PCF85176 are synchronized, they can share the backplane signals from

one of the devices in the cascade. The other PCF85176 of the cascade contribute

additional segment outputs. The backplanes can either be connected together to enhance

the drive capability or some can be left open-circuit (such as the ones from the slave

in Figure 27) or just some of the master and some of the slave an be taken to facilitate the

layout of the display.

Table 21. Addressing cascaded PCF85176

Cluster Bit SA0 Pin A2 Pin A1 Pin A0 Device

100000

0011

0102

0113

1004

1015

1106

1117

210008

0019

01010

01111

10012

10113

11014

11115

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Product data sheet Rev. 5 — 6 January 2015 39 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCF85176. Synchronization is guaranteed after a power-on reset. The only time that

SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in

adverse electrical environments or by defining a multiplex drive mode when PCF85176

with different SA0 levels are cascaded).

SYNC is organized as an input/output pin. The output selection is realized as an

open-drain driver with an internal pull-up resistor. A PCF85176 asserts the SYNC line at

the onset of its last active backplane signal and monitors the SYNC line at all other times.

If synchronization in the cascade is lost, it is restored by the first PCF85176 to assert

SYNC. The timing relationship between the backplane waveforms and the SYNC signal

for the various drive modes of the PCF85176 are shown in Figure 28.

The PCF85176 can always be cascaded with other devices of the same type or

conditionally with other devices of the same family. This allows optimal drive selection for

a given number of pixels to display. Figure 25 and Figure 28 show the timing of the

synchronization signals.

Only one master but multiple slaves are allowed in a cascade. All devices in the cascade

have to use the same clock whether it is supplied externally or provided by the master.

(1) Is master (OSC connected to VSS).

(2) Is slave (OSC connected to VDD).

Fig 27. Cascaded PCF85176 configuration

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Product data sheet Rev. 5 — 6 January 2015 40 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

If an external clock source is used, all PCF85176 in the cascade must be configured such

as to receive the clock from that external source (pin OSC connected to VDD). Thereby it

must be ensured that the clock tree is designed such that on all PCF85176 the clock

propagation delay from the clock source to all PCF85176 in the cascade is as equal as

possible since otherwise synchronization artefacts may occur.

In mixed cascading configurations, care has to be taken that the specifications of the

individual cascaded devices are met at all times.

Fig 28. Synchronization of the cascade for the various PCF85176 drive modes

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Product data sheet Rev. 5 — 6 January 2015 41 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

15. Package outline

Fig 29. Package outline SOT357-1 (TQFP64) of PCF85176H

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Product data sheet Rev. 5 — 6 January 2015 42 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

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Product data sheet Rev. 5 — 6 January 2015 43 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

R61. 10 “SOT35771 518" Ref. 11 “SOT36471 118" on gage 52

Product data sheet Rev. 5 — 6 January 2015 44 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

17. Packing information

17.1 Tape and reel information

For tape and reel packing information, see Ref. 10 “SOT357-1_518” and Ref. 11

“SOT364-1_118” on page 52.

18. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

18.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

Figure 31 Table 22 23 Figure 31

Product data sheet Rev. 5 — 6 January 2015 45 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

18.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

18.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 31) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 22 and 23

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 31.

Table 22. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 23. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

mamum peak hamperature = MSL hymn damage \eve\ mmmum peak |emperature = mwmmum soldenng |emperamre

Product data sheet Rev. 5 — 6 January 2015 46 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

MSL: Moisture Sensitivity Level

Fig 31. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 5 — 6 January 2015 47 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

19. Footprint information

Fig 32. Footprint information for reflow soldering of SOT357-1 (TQFP64) of PCF85176H

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Product data sheet Rev. 5 — 6 January 2015 48 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

Fig 33. Footprint information for reflow soldering of SOT364-1 (TSSOP56) of PCF85176T

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Product data sheet Rev. 5 — 6 January 2015 49 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

20. Appendix

20.1 LCD segment driver selection

Table 24. Selection of LCD segment drivers

Type name Number of elements at MUX VDD (V) VLCD (V) ffr (Hz) VLCD (V)

charge

pump

VLCD (V)

temperature

compensat.

Tamb (C) Interface Package AEC-

Q100

1:1 1:2 1:3 1:4 1:6 1:8 1:9

PCA8553DTT 40 80 120 160 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256[1] NN 40 to 105 I2C / SPI TSSOP56 Y

PCA8546ATT - - - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300[1] NN 40 to 95 I2C TSSOP56 Y

PCA8546BTT - - - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300[1] NN 40 to 95 SPI TSSOP56 Y

PCA8547AHT 44 88 - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300[1] YY 40 to 95 I2CTQFP64Y

PCA8547BHT 44 88 - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300[1] YY 40 to 95 SPI TQFP64 Y

PCF85134HL 60 120 180 240 - - - 1.8 to 5.5 2.5 to 6.5 82 N N 40 to 85 I2CLQFP80N

PCA85134H 60 120 180 240 - - - 1.8 to 5.5 2.5 to 8 82 N N 40 to 95 I2CLQFP80Y

PCA8543AHL 60 120 - 240 - - - 2.5 to 5.5 2.5 to 9 60 to 300[1] YY 40 to 105 I2CLQFP80Y

PCF8545ATT - - - 176 252 320 - 1.8 to 5.5 2.5 to 5.5 60 to 300[1] NN 40 to 85 I2C TSSOP56 N

PCF8545BTT - - - 176 252 320 - 1.8 to 5.5 2.5 to 5.5 60 to 300[1] NN 40 to 85 SPI TSSOP56 N

PCF8536AT - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300[1] NN 40 to 85 I2C TSSOP56 N

PCF8536BT - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300[1] NN 40 to 85 SPI TSSOP56 N

PCA8536AT - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300[1] NN 40 to 95 I2C TSSOP56 Y

PCA8536BT - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300[1] NN 40 to 95 SPI TSSOP56 Y

PCF8537AH 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300[1] YY 40 to 85 I2CTQFP64N

PCF8537BH 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300[1] YY 40 to 85 SPI TQFP64 N

PCA8537AH 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300[1] YY 40 to 95 I2CTQFP64Y

PCA8537BH 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300[1] YY 40 to 95 SPI TQFP64 Y

PCA9620H 60 120 - 240 320 480 - 2.5 to 5.5 2.5 to 9 60 to 300[1] YY 40 to 105 I2CLQFP80Y

PCA9620U 60 120 - 240 320 480 - 2.5 to 5.5 2.5 to 9 60 to 300[1] YY 40 to 105 I2C Bare die Y

PCF8576DU 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 77 N N 40 to 85 I2C Bare die N

PCF8576EUG 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 77 N N 40 to 85 I2C Bare die N

PCA8576FUG 40 80 120 160 - - - 1.8 to 5.5 2.5 to 8 200 N N 40 to 105 I2C Bare die Y

PCF85133U 80 160 240 320 - - - 1.8 to 5.5 2.5 to 6.5 82, 110[2] NN 40 to 85 I2C Bare die N

PCA85133U 80 160 240 320 - - - 1.8 to 5.5 2.5 to 8 82, 110[2] NN 40 to 95 I2C Bare die Y

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Product data sheet Rev. 5 — 6 January 2015 50 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

[1] Software programmable.

[2] Hardware selectable.

PCA85233UG 80 160 240 320 - - - 1.8 to 5.5 2.5 to 8 150, 220[2] NN 40 to 105 I2C Bare die Y

PCF85132U 160 320 480 640 - - - 1.8 to 5.5 1.8 to 8 60 to 90[1] NN 40 to 85 I2C Bare die N

PCA8530DUG 102 204 - 408 - - - 2.5 to 5.5 4 to 12 45 to 300[1] YY 40 to 105 I2C / SPI Bare die Y

PCA85132U 160 320 480 640 - - - 1.8 to 5.5 1.8 to 8 60 to 90[1] NN 40 to 95 I2C Bare die Y

PCA85232U 160 320 480 640 - - - 1.8 to 5.5 1.8 to 8 117 to 176[1] NN 40 to 95 I2C Bare die Y

PCF8538UG 102 204 - 408 612 816 918 2.5 to 5.5 4 to 12 45 to 300[1] YY 40 to 85 I2C / SPI Bare die N

PCA8538UG 102 204 - 408 612 816 918 2.5 to 5.5 4 to 12 45 to 300[1] YY 40 to 105 I2C / SPI Bare die Y

Table 24. Selection of LCD segment drivers …continued

Type name Number of elements at MUX VDD (V) VLCD (V) ffr (Hz) VLCD (V)

charge

pump

VLCD (V)

temperature

compensat.

Tamb (C) Interface Package AEC-

Q100

1:1 1:2 1:3 1:4 1:6 1:8 1:9

Product data sheet Rev. 5 — 6 January 2015 51 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

21. Abbreviations

Table 25. Abbreviations

Acronym Description

CMOS Complementary Metal-Oxide Semiconductor

CDM Charged Device Model

DC Direct Current

HBM Human Body Model

I2C Inter-Integrated Circuit

IC Integrated Circuit

LCD Liquid Crystal Display

LSB Least Significant Bit

MSB Most Significant Bit

MSL Moisture Sensitivity Level

PCB Printed-Circuit Board

POR Power-On Reset

RAM Random Access Memory

RC Resistance and Capacitance

RMS Root Mean Square

SCL Serial CLock line

SDA Serial DAta Line

SMD Surface-Mount Device

Table 18 Tab‘e 19 Table 20 m Figure 24

Product data sheet Rev. 5 — 6 January 2015 52 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

22. References

[1] AN10365 — Surface mount reflow soldering description

[2] AN10853 — ESD and EMC sensitivity of IC

[3] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[5] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices

[6] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[7] JESD22-C101 — Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[8] JESD78 — IC Latch-Up Test

[9] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[10] SOT357-1_518 — TSSOP64; Reel pack; SMD, 13", packing information

[11] SOT364-1_118 — TSSOP56; Reel pack; SMD, 13", packing information

[12] UM10204 — I2C-bus specification and user manual

[13] UM10569 — Store and transport requirements

23. Revision history

Table 26. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCF85176 v.5 20150106 Product data sheet - PCF85176 v.4

Modifications: •The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Adjusted ESD values in Table 18

•Changed IDD(LCD) values in Table 19

•Changed fclk(int) typical value in Table 20

•Changed Section 17.1

•Adjusted Figure 24

PCF85176 v.4 20130610 Product data sheet - PCF85176 v.3

PCF85176 v.3 20120905 Product data sheet - PCF85176 v.2

PCF85176 v.2 20110627 Product data sheet - PCF85176 v.1

PCF85176 v.1 20100414 Product data sheet - -

Product data sheet Rev. 5 — 6 January 2015 53 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

24. Legal information

24.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

24.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

24.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

: hitE:I/www.nxg.com salesaddresses®nx9£0m

Product data sheet Rev. 5 — 6 January 2015 54 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

24.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP Semiconductors N.V.

25. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 5 — 6 January 2015 55 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

26. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 5. Definition of PCF85176 commands . . . . . . . . . .6

Table 6. C bit description . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 7. Mode-set command bit description . . . . . . . . . .7

Table 8. Load-data-pointer command bit description . . . .7

Table 9. Device-select command bit description . . . . . . .8

Table 10. Bank-select command bit description . . . . . . . .8

Table 11. Blink-select command bit description . . . . . . . . .9

Table 12. Blink frequencies . . . . . . . . . . . . . . . . . . . . . . .10

Table 13. Selection of possible display configurations . . .11

Table 14. Biasing characteristics . . . . . . . . . . . . . . . . . . .12

Table 15. Standard RAM filling in 1:3 multiplex drive

mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 16. Entire RAM filling by rewriting in 1:3 multiplex

drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 17. I2C slave address byte . . . . . . . . . . . . . . . . . . .30

Table 18. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 19. Static characteristics . . . . . . . . . . . . . . . . . . . .34

Table 20. Dynamic characteristics . . . . . . . . . . . . . . . . . .36

Table 21. Addressing cascaded PCF85176 . . . . . . . . . .38

Table 22. SnPb eutectic process (from J-STD-020D) . . .45

Table 23. Lead-free process (from J-STD-020D) . . . . . .45

Table 24. Selection of LCD segment drivers . . . . . . . . . .49

Table 25. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 26. Revision history . . . . . . . . . . . . . . . . . . . . . . . .52

Product data sheet Rev. 5 — 6 January 2015 56 of 57

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

27. Figures

Fig 1. Block diagram of PCF85176 . . . . . . . . . . . . . . . . .3

Fig 2. Pinning diagram for TQFP64 (PCF85176H) . . . . .4

Fig 3. Pinning diagram for TSSOP56 (PCF85176T) . . . .4

Fig 4. Example of displays suitable for PCF85176 . . . .11

Fig 5. Typical system configuration . . . . . . . . . . . . . . . .12

Fig 6. Electro-optical characteristic: relative

transmission curve of the liquid . . . . . . . . . . . . . .14

Fig 7. Static drive mode waveforms. . . . . . . . . . . . . . . .15

Fig 8. Waveforms for the 1:2 multiplex drive mode

with 1⁄2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Fig 9. Waveforms for the 1:2 multiplex drive mode

with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Fig 10. Waveforms for the 1:3 multiplex drive mode

with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Fig 11. Waveforms for the 1:4 multiplex drive mode

with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Fig 12. Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . .21

Fig 13. Relationship between LCD layout, drive mode,

display RAM filling order, and display data

transmitted over the I2C-bus . . . . . . . . . . . . . . . .22

Fig 14. RAM banks in static and multiplex driving

mode 1:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Fig 15. Bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Fig 16. Example of the Bank-select command with

multiplex drive mode 1:2 . . . . . . . . . . . . . . . . . . .27

Fig 17. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Fig 18. Definition of START and STOP conditions. . . . . .28

Fig 19. System configuration . . . . . . . . . . . . . . . . . . . . . .29

Fig 20. Acknowledgement of the I2C-bus . . . . . . . . . . . .29

Fig 21. I2C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . . .31

Fig 22. Format of command byte. . . . . . . . . . . . . . . . . . .31

Fig 23. Device protection circuits. . . . . . . . . . . . . . . . . . .32

Fig 24. Typical IDD with respect to VDD . . . . . . . . . . . . . .35

Fig 25. Driver timing waveforms . . . . . . . . . . . . . . . . . . .37

Fig 26. I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .37

Fig 27. Cascaded PCF85176 configuration. . . . . . . . . . .39

Fig 28. Synchronization of the cascade for the various

PCF85176 drive modes . . . . . . . . . . . . . . . . . . . .40

Fig 29. Package outline SOT357-1 (TQFP64) of

PCF85176H. . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Fig 30. Package outline SOT364-1 (TSSOP56) of

PCF85176T . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Fig 31. Temperature profiles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Fig 32. Footprint information for reflow soldering of

SOT357-1 (TQFP64) of PCF85176H. . . . . . . . . .47

Fig 33. Footprint information for reflow soldering of

SOT364-1 (TSSOP56) of PCF85176T . . . . . . . .48

NXP Semiconductors PCF85176

40 x 4 universal LCD driver for low multiplex rates

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 6 January 2015

Document identifier: PCF85176

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

28. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Functional description . . . . . . . . . . . . . . . . . . . 6

7.1 Commands of PCF85176 . . . . . . . . . . . . . . . . . 6

7.1.1 Command: mode-set . . . . . . . . . . . . . . . . . . . . 7

7.1.2 Command: load-data-pointer . . . . . . . . . . . . . . 7

7.1.3 Command: device-select . . . . . . . . . . . . . . . . . 8

7.1.4 Command: bank-select. . . . . . . . . . . . . . . . . . . 8

7.1.5 Command: blink-select. . . . . . . . . . . . . . . . . . . 9

7.1.5.1 Blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.2 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 10

7.3 Possible display configurations . . . . . . . . . . . 11

7.3.1 LCD bias generator . . . . . . . . . . . . . . . . . . . . 12

7.3.2 Display register. . . . . . . . . . . . . . . . . . . . . . . . 12

7.3.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . 12

7.3.3.1 Electro-optical performance . . . . . . . . . . . . . . 14

7.3.4 LCD drive mode waveforms . . . . . . . . . . . . . . 15

7.3.4.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 15

7.3.4.2 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 16

7.3.4.3 1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 18

7.3.4.4 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 19

7.4 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.4.1 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.4.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.4.3 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.5 Backplane and segment outputs . . . . . . . . . . 20

7.5.1 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 20

7.5.2 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 20

7.6 Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.6.1 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.6.2 Subaddress counter . . . . . . . . . . . . . . . . . . . . 23

7.6.3 RAM writing in 1:3 multiplex drive mode. . . . . 24

7.6.4 Writing over the RAM address boundary . . . . 25

7.6.5 Bank selection . . . . . . . . . . . . . . . . . . . . . . . . 25

7.6.5.1 Output bank selector . . . . . . . . . . . . . . . . . . . 25

7.6.5.2 Input bank selector . . . . . . . . . . . . . . . . . . . . . 25

7.6.5.3 RAM bank switching . . . . . . . . . . . . . . . . . . . . 25

8 Characteristics of the I2C-bus . . . . . . . . . . . . 28

8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.2 START and STOP conditions. . . . . . . . . . . . . 28

8.3 System configuration . . . . . . . . . . . . . . . . . . . 28

8.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.5 I2C-bus controller. . . . . . . . . . . . . . . . . . . . . . 30

8.6 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.7 I2C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . 30

9 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 32

10 Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33

12 Static characteristics . . . . . . . . . . . . . . . . . . . 34

13 Dynamic characteristics. . . . . . . . . . . . . . . . . 36

14 Application information . . . . . . . . . . . . . . . . . 38

14.1 Cascaded operation. . . . . . . . . . . . . . . . . . . . 38

15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 41

16 Handling information . . . . . . . . . . . . . . . . . . . 43

17 Packing information . . . . . . . . . . . . . . . . . . . . 44

17.1 Tape and reel information . . . . . . . . . . . . . . . 44

18 Soldering of SMD packages. . . . . . . . . . . . . . 44

18.1 Introduction to soldering. . . . . . . . . . . . . . . . . 44

18.2 Wave and reflow soldering. . . . . . . . . . . . . . . 44

18.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 45

18.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 45

19 Footprint information . . . . . . . . . . . . . . . . . . . 47

20 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

20.1 LCD segment driver selection . . . . . . . . . . . . 49

21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 51

22 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

23 Revision history . . . . . . . . . . . . . . . . . . . . . . . 52

24 Legal information . . . . . . . . . . . . . . . . . . . . . . 53

24.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 53

24.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

24.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 53

24.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 54

25 Contact information . . . . . . . . . . . . . . . . . . . . 54

26 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

27 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

28 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Scheda tecnica PCF85176 di NXP USA Inc.

INFORMAZIONI

GUIDA

CONTATTI

SEGUICI