Scheda tecnica LTC4314 di Analog Devices Inc.

Commenti/errori della scheda tecnica

L7L|nt “I2 LTC4314 TECHNOLOGY SCLDLI'H V L7 LJUW

LTC4314

4314f

TYPICAL APPLICATION

DESCRIPTION

Pin-Selectable, 4-Channel,

2-Wire Multiplexer

with Bus Buffers

The LTC

4314 is a hot-swappable 4-channel 2-wire bus

multiplexer that allows one upstream bus to connect to

any combination of downstream busses or channels.

An individual enable pin controls each connection. The

LTC4314 provides bidirectional buffering, keeping the up-

stream bus capacitance isolated from the downstream bus

capacitances. The high noise margin allows the LTC4314

to be interoperable with I2C devices that drive a high VOL

(> 0.4V). The LTC4314 supports level translation between

1.5V, 1.8V, 2.5V, 3.3V and 5V busses. The hot-swappable

nature of the LTC4314 allows I/O card insertion into, and

removal from, a live backplane without corruption of the

data and clock busses.

If both data and clock are not simultaneously high at

least once in 45ms and DISCEN is high, a FAULT signal is

generated indicating a stuck bus low condition, the input

is disconnected from all enabled output channels, and up

to 16 clocks are generated on the enabled downstream

busses. A three state ACC pin enables input and output

side rise time accelerators of varying strengths and sets

the VIL,RISING voltage.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap

is a trademark of Linear Technology Corporation. All other trademarks are the property of their

respective owners. Protected by U.S. Patents, including 6356140, 6650174, 7032051, 7478286.

FEATURES

APPLICATIONS

n 1:4 Multiplexer/Switch for 2-Wire Bus

n Bidirectional Buffer for SDA and SCL Lines

n High Noise Margin with VIL = 0.3•VCC

n ENABLE Pins Connect SDA and SCL Lines

n Selectable Rise Time Accelerator Current and

Activation Voltage

n Level Shift 1.5V, 1.8V, 2.5V, 3.3V and 5V Busses

n Prevents SDA and SCL Corruption During Live Board

Insertion and Removal from Backplane

n Stuck Bus Disconnect and Recovery

n Compatible with I2C, I2C Fast Mode and SMBus

n ±4kV Human Body Model (HBM) ESD Ruggedness

n 20-Lead SSOP and 3mm × 4mm QFN Packages

n Telecommunications Systems Including ATCA

n Address Expansion

n Level Translator

n Capacitance Buffers/Bus Extender

n Live Board Insertion

n PMBus

Rising Edge from Asserted Low

with Level Translation

LTC4314

GND

VCC VCC2

4314 TA01a

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLIN

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

ACC

DISCEN

FAULT

SCLIN

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

3.3V

10k

FAULT

10k10k

0.01μF

3.3V 3.3V

10k10k

•••

0.01μF

200ns/DIV

1V/DIV

4314 TA01b

CSCLOUT1 + CSCLOUT4 = 100pF

CSCLIN = 50pF SCLOUT4

SCLOUT1

SCLIN

3.3V

LTC4314 3333333333 EEEEEEEEEE L7LJCUEN2

LTC4314

4314f

ABSOLUTE MAXIMUM RATINGS

Supply Voltages

VCC, VCC2 ................................................. –0.3V to 6V

Input Voltages

ACC, DISCEN, ENABLE1-4 ....................... –0.3V to 6V

Input/Output Voltages

SDAIN, SCLIN, SCLOUT1-4,

SDAOUT1-4, FAULT ................................. –0.3V to 6V

(Notes 1, 2)

20 19 18 17

7 8

TOP VIEW

UDC PACKAGE

20-LEAD (3mm s 4mm) PLASTIC QFN

9 10

SCLOUT1

SDAOUT1

SDAIN

SCLIN

SCLOUT2

SDAOUT2

SDAOUT4

SCLOUT4

VCC2

FAULT

SDAOUT3

SCLOUT3

VCC

DISCEN

ACC

GND

ENABLE4

ENABLE 3

ENABLE2

ENABLE1

TJMAX = 150°C, θJA = 68°C/W, θJC = 4.2°C/W

EXPOSED PAD (PIN 21) PCB CONNECTION TO GND IS OPTIONAL

GN PACKAGE

20-LEAD PLASTIC SSOP

TOP VIEW

DISCEN

VCC

SCLOUT1

SDAOUT1

SDAIN

SCLIN

SCLOUT2

SDAOUT2

ENABLE4

ENABLE3

ACC

GND

SDAOUT4

SCLOUT4

VCC2

FAULT

SDAOUT3

SCLOUT3

ENABLE1

ENABLE2

TJMAX = 150°C, θJA = 90°C/W, θJC = 30°C/W

PIN CONFIGURATION

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4314IUDC#PBF LTC4314IUDC#TRPBF LFMR 20-Lead (3mm × 4mm) QFN –40°C to 85°C

LTC4314IGN#PBF LTC4314IGN#TRPBF LTC4314GN 20-Lead Plastic SSOP –40°C to 85°C

LTC4314CUDC#PBF LTC4314CUDC#TRPBF LFMR 20-Lead (3mm × 4mm) QFN 0°C to 70°C

LTC4314CGN#PBF LTC4314CGN#TRPBF LTC4314GN 20-Lead Plastic SSOP 0°C to 70°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

Output DC Sink Currents

FAULT ................................................................. 50mA

Operating Ambient Temperature Range

LTC4314C ................................................ 0°C to 70°C

LTC4314I..............................................–40°C to 85°C

Storage Temperature Range ..................–65°C to 150°C

Lead Temperature (Soldering, 10 sec)

SSOP ............................................................... 300°C

LTC43 1 4 L7 LJUW

LTC4314

4314f

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Supply/Start-Up

VCC Input Supply Voltage l2.9 5.5 V

VDD, BUS 2-Wire Bus Supply Voltage l2.25 5.5 V

VCC2 Output Side Accelerator Supply

Voltage

l2.25 5.5 V

ICC Input Supply Current One or More VENABLE1-4 = VCC = VCC2 = 5.5V

(Note 3)

l6.0 7.3 9 mA

ICC(DISABLED) Input Supply Current VENABLE1-4 = 0V, VCC = VCC2 = 5.5V (Note 3) l1.6 2.2 3.5 mA

ICC2 VCC2 Supply Current One or More VENABLE1-4 = VCC = VCC2 = 5.5V

(Note 3)

l0.35 0.5 0.6 mA

tUVLO UVLO Delay l60 110 200 μs

VTH_UVLO UVLO Threshold l2.3 2.6 V

VCC_UVLO(HYST) UVLO Threshold Hysteresis Voltage 200 mV

Buffers

VOS(SAT) Buffer Offset Voltage IOL = 4mA, Driven VSDAIN, SCLIN = 50mV l130 220 280 mV

IOL = 500μA, Driven VSDAIN, SCLIN = 50mV l15 60 120 mV

VOS2(SAT) Buffer Offset Voltage IOL = 4mA, Driven VSDAOUT, SCLOUT = 50mV l90 190 260 mV

IOL = 500μA, Driven VSDAOUT, SCLOUT = 50mV l15 55 110 mV

VOS Buffer Offset Voltage IOL = 4mA, Driven VSDAIN, SCLIN = 200mV l50 130 195 mV

IOL = 500μA, Driven VSDAIN, SCLIN = 200mV l15 55 110 mV

VOS2 Buffer Offset Voltage IOL = 4mA, Driven VSDAOUT,SCLOUT = 200mV l35 95 170 mV

IOL = 500μA, Driven VSDAOUT,SCLOUT = 200mV l15 50 100 mV

VIL,FALLING Buffer Input Logic Low Voltage SDA, SCL Pins (Notes 4, 5) l0.3•VMIN 0.33•VMIN 0.36•VMIN V

VIL,RISING Buffer Input Logic Low Voltage SDA, SCL Pins; ACC Grounded l0.5 0.6 0.7 V

SDA, SCL Pins; ACC Open or High (Notes 4, 5) l0.3•VMIN 0.33•VMIN 0.36•VMIN V

ILEAK Input Leakage Current SDA, SCL Pins; VCC, VCC2 = 0V, 5.5V l±10 μA

CIN Input Capacitance SDA, SCL Pins (Note 6) <20 pF

Rise Time Accelerators

dV/dt (RTA) Minimum Slew Rate Requirement SDA, SCL Pins; VCC = VCC2 = 5V l0.1 0.2 0.4 V/μs

VRTA(TH) Rise Time Accelerator DC

Threshold Voltage

SDA, SCL Pins; VCC = VCC2 = 5V, ACC Grounded l0.7 0.8 0.9 V

ACC Open or High, VCC = VCC2 = 5V (Note 4) l0.36•VMIN 0.4•VMIN 0.44•VMIN V

ΔVACC Buffers Off to Accelerator On Voltage SDA, SCL Pins; VCC = VCC2 = 5V, ACC Grounded l100 200 mV

ACC Open, VCC = VCC2 = 5V (Note 4) l0.05•VMIN 0.07•VMIN mV

IRTA Rise Time Accelerator

Pull-Up Current

SDA, SCL Pins; VCC = VCC2 = 5V,

ACC Grounded (Note 7)

l20 35 45 mA

ACC Open, VCC = VCC2 = 5V (Note 7) l1.5 3 4 mA

Enable/Control

VDISCEN(TH) DISCEN Threshold Voltage l0.8 1.4 2 V

ΔVDISCEN(HYST) DISCEN Hysteresis Voltage 20 mV

VEN(TH) ENABLE1-4 Threshold Voltage l0.8 1.4 2 V

ΔVEN(HYST) ENABLE1-4 Hysteresis Voltage 20 mV

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = VCC2 = 3.3V unless otherwise noted.

LTC4314 L7LJCUEN2

LTC4314

4314f

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = VCC2 = 3.3V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tLH_EN ENABLE1-4 High to Buffer Active l0.56 1 μs

ILEAK Input Leakage Current DISCEN = ENABLE1–4 Pins = 5.5V l0.1 ±10 μA

IACC(IN, HL) ACC High, Low Input Current VCC = 5V, VACC = 5V, 0V l±23 ±40 μA

IACC(IN, Z) Allowable Leakage Current in

Open State

VCC = 5V l±5 μA

IACC(EN, Z) ACC High Z Input Current VCC = 5V l±5 μA

VACC(L, TH) ACC Input Low Threshold Voltages VCC = 5V l0.2•VCC 0.3•VCC 0.4•VCC V

VACC(H,TH) ACC Input High Threshold Voltages VCC = 5V l0.7•VCC 0.8•VCC 0.9•VCC V

Stuck Low Timeout Circuitry

tTIMEOUT Bus Stuck Low Timer SDAOUT or SCLOUT < 0.3•VCC l35 45 55 ms

VFAULT(OL) FAULT Output Low Voltage IFAULT = 3mA l0.4 V

IFAULT(OH) FAULT Leakage Current l0.1 ±5 μA

I2C Interface Timing

fSCL(MAX) I2C Frequency Max (Note 6) l400 kHz

tPDHL SCL, SDA Fall Delay VCC = 3V to 5.5V, CBUS = 50pF, IBUS = 1mA (Note 6) 60 100 ns

tfSCL, SDA Fall Times VCC = 3V to 5.5V, CBUS = 50pF, IBUS = 1mA (Note 6) 10 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive and all voltages are referenced to

GND unless otherwise indicated.

Note 3: SDAIN, SCLIN pulled low.

Note 4: VMIN = minimum of VCC and VCC2 if VCC2 > 2.25V else VMIN = VCC.

Note 5: VIL is tested for the following (VCC, VCC2) combinations:

(2.9V, 5.5V), (5.5V, 2.25V), (3.3V, 3.3V) and (5V, 0V).

Note 6: Guaranteed by design and not tested.

Note 7: Measured in a special DC mode with VSDA,SCL = VRTA(TH) + 1V.

The transient IRTA seen during rising edges when ACC is low will depend

on the bus loading condition and the slew rate of the bus. The LTC4314’s

internal slew rate control circuitry limits the maximum bus rise rate to

75V/μs by controlling the transient IRTA.

LTC43 1 4 wasv In // 2200 7 / Vccz = 5v . / \ 7 DIN /\ mom 7 m 2200 \ / 5V somv \ 5v / / /’ 3 av // L7 LJDW

LTC4314

4314f

TYPICAL PERFORMANCE CHARACTERISTICS

Rise Time Accelerator Current

vs Temperature

Buffer High to Low Propagation

Delay vs Output Capacitance

Input to Output Offset Voltage

vs Bus Current for Different

Driven Input Voltage Levels

Output to Input Offset Voltage

vs Bus Current for Different

Driven Output Voltage Levels

ICC Enabled Current

vs Supply Voltage

ICC Disabled (ENABLE1-4 Low)

Current vs Supply Voltage

Multiplexer Switch Resistance

RMUX vs Temperature

TA = 25°C, VCC = 3.3V unless otherwise noted.

Buffer DC IOL vs Temperature

CBUS (pF)

tPDF (ns)

250

100

150

200

0500

4314 G05

15001000

VCC = VCC2 = VDD, BUS = 5V

RBUS = 2.7kΩ

VCC (V)

ICC (mA)

8.0

7.5

7.0

6.5 3

4314 G01

645

VSDAIN, SCLIN = 0V

VCC (V)

ICC (mA)

3.0

2.5

1.5

2.0

1.0 3

4314 G02

645

VSDAIN, SCLIN = 0V

TEMPERATURE (°C)

–50

IOL (mA)

4500

4314 G04

10025–25 75

VSDAIN, SCLIN = 0.4V

VSDAOUT, SCLOUT = 0.4V

VCC = VCC2 = 3.3V

IBUS (mA)

VOS (mV)

350

100

150

200

300

250

4314 G06

≥200mV

100mV

DRIVEN VSDAIN,SCLIN = 50mV

VCC = VCC2 = VDD, BUS = 5V

TEMPERATURE (°C)

–50

IRTA (mA)

4314 G08

100–25 25 50 75

3.3V

VCC = VCC2 = VDD, BUS

VSDA,SCLtVDD,BUS

ACC = 0V

CBUS = 400pF

RBUS = 10k

IBUS (mA)

VOS (mV)

350

100

150

200

300

250

4314 G07

100mV

≥200mV

DRIVEN VSDAOUT, SCLOUT = 50mV

VCC = VCC2 = VDD, BUS = 5V

tRISE(30%–70%) vs CBUS

CBUS (pF)

tRISE (ns)

150

125

100

0400

4314 G08

800200 600

3.3V

VCC = VCC2 = VDD, BUS

ACC = 0V

TEMPERATURE (°C)

–50

RMUX (Ω)

500

4314 G03

10025–25 75

VCC2 = 3.3V

IDS = 4mA

VCC2 = 5V

LTC4314 L7LJCUEN2

LTC4314

4314f

PIN FUNCTIONS

ACC: Three-State Acceleration and Buffer Mode Selec-

tor. This pin controls the turn on voltage of the rise time

accelerators and their current strength on both the input

and output sides. It also controls the turn-off voltage of

the buffers. See Table 1 in the Applications Information

section.

DISCEN: Disconnect Stuck Bus Enable Input. When this

pin is high, stuck busses are automatically disconnected

and FAULT is pulled low after a timeout period of 45ms.

Up to sixteen clock pulses are subsequently applied to the

stuck output channels. When DISCEN is low, stuck busses

are neither disconnected nor clocked but FAULT is pulled

low. Connect to GND if unused.

ENABLE1-ENABLE4: Connection Enable Inputs. These

input pins enable or disable the corresponding output

channel. Driving an ENABLE pin low isolates SDAIN and

SCLIN from the corresponding SDAOUT and SCLOUT.

Only enable and disable a channel when all busses are

idle. During bus stuck low fault condition, a falling edge

on all ENABLE pins followed by a rising edge on one or

more ENABLE pins forces a connection from SDAIN to

the selected SDAOUT and SCLIN to the selected SCLOUT.

Connect to GND if unused.

Exposed Pad (QFN Package Only): Exposed pad may be

left open or connected to device GND.

FAULT: Stuck Bus Fault Output. This open drain N-channel

MOSFET output pulls low if a simultaneous high on the

enabled SCLOUT and SDAOUT channels does not occur in

45ms. In normal operation FAULT is high. Connect a pull

up resistor, typically 10k, from this pin to the bus pull-up

supply. Leave open or tie to GND if unused.

GND: Device Ground.

SCLIN: Upstream Serial Bus Clock Input/Output. Connect

this pin to the SCL line on the upstream bus. Connect an

external pull-up resistor or current source between this

pin and the bus supply. Do not leave open.

SCLOUT1-SCLOUT4: Downstream Serial Bus Clock Input/

Output Channels 1-4. Connect pins SCLOUT1-SCLOUT4

to the SCL lines on the downstream channels 1-4, respec-

tively. When in use, an external pull-up resistor or current

source is required between the pin and the corresponding

bus supply. Leave open or tie to GND and connect the

corresponding ENABLE pin to GND if unused.

SDAIN: Upstream Serial Bus Data Input/Output. Connect

this pin to the SDA line on the upstream bus. Connect an

external pull-up resistor or current source between this

pin and the bus supply. Do not leave open.

SDAOUT1-SDAOUT4: Downstream Serial Bus Data Input/

Output Channels 1-4. Connect pins SDAOUT1-SDAOUT4 to

the SDA lines on downstream channels 1-4, respectively.

When in use, an external pull-up resistor or current source

is required between the pin and the corresponding bus

supply. Leave open or tie to GND and connect the cor-

responding ENABLE pin to GND if unused.

VCC: Power Supply Voltage. Power this pin from a sup-

ply between 2.9V and 5.5V. Bypass with at least 0.01μF

to GND.

VCC2: Output Side Rise Time Accelerator (RTA) Power

Supply Voltage. When powering VCC2, use a supply volt-

age ranging from 2.25V to 5.5V and bypass with at least

0.01μF to GND. If the downstream busses are powered

from multiple supply voltages, power VCC2 from the low-

est supply voltage. Output side RTAs are active if VCC2 ≥

2.25V and ACC is low or open. Grounding VCC2 disables

output side RTAs.

LTC43 1 4 W 12% 8:02 W 4 / L7 LJUW

LTC4314

4314f

BLOCK DIAGRAM

IBOOST_SCL/IBOOST_SDA

4314 BD

VIL

VCC

IRTA

UVLO 110μs

TIMER

45ms

TIMER

LOGIC

SCLIN

SDAIN

DISCEN

GND

VCC

ENABLE1

ENABLE4

ACC

VCC

IRTA

VCC2

SCLOUT1

SDAOUT1

SDAOUT4

FAULT

SCLOUT4

–

VIL VIL

–

CIN

DIN

CO1

CO4

DO1

DO4

VCC2

IRTA

VCC2

IRTA

VCC2

IRTA

VCC2

IRTA

EN1

EN4

MUX

–

VIL

–

ttt

CONNECT

ttt

SLEW RATE

DETECTOR

0.2V/μs

SLEW RATE

DETECTOR

0.2V/μs

SLEW RATE

DETECTOR

0.2V/μs

SLEW RATE

DETECTOR

0.2V/μs

LTC4314 L7LJCUEN2

LTC4314

4314f

OPERATION

The Block Diagram shows the major functional blocks of

the LTC4314. The LTC4314 is a 1:4 multiplexer with ca-

pacitance buffering for I2C signals. Capacitance buffering

is achieved by use of back to back buffers on the clock

and data channels which isolate the SDAIN and SCLIN

capacitances from the SDAOUT and SCLOUT capacitances

respectively. All SDA and SCL pins are fully bidirectional.

The high noise margin allows the LTC4314 to operate

with I2C devices that drive a non-compliant high VOL.

Multiplexing is done using N-channel MOSFETs that are

controlled by dedicated ENABLE pins. When enabled,

rise time accelerator pull-up currents IRTA turn on dur-

ing rising edges to reduce system rise time. In a typical

application the input side bus is pulled up to VCC and the

output side busses are pulled up to VCC2 although these

are not requirements. VCC is the primary power supply to

the LTC4314. VCC and VCC2 serve as the input and output

side rise time accelerator supplies respectively. Ground-

ing VCC2 disables the output side rise time accelerators.

The multiplexer N-channel MOSFET gates of the enabled

channels are driven to VCC2 if VCC2 is > 1.8V, otherwise

they are driven to VCC.

When the LTC4314 ﬁ rst receives power on its VCC pin, it

starts out in an undervoltage lockout mode (UVLO) until

110μs after VCC exceeds 2.3V. During this time, the buffers

and rise time accelerators are disabled, the multiplexer

gates are off and the LTC4314 ignores transitions on the

clock and data pins independent of the state of the ENABLE

pins. VCC2 transitions from a high to a low or vice-versa

across a 1.8V threshold also cause the LTC4314 to dis-

able the buffers, rise time accelerators and transmission

gates and to ignore the clock and data pins until 110μs

after that transition. Assuming that the LTC4314 is not

in UVLO mode, when one or more ENABLEs is asserted,

the LTC4314 activates the connection circuitry between

the SDAIN, SCLIN inputs and selected output channels.

The input rise time accelerators and the output rise time

accelerators of the selected channels are also enabled at

this time. When a SDA,SCL input pin or output pin on an

enabled output channel is driven below the VIL,FALLING

level of 0.33•VMIN, the buffers are turned on and the logic

low level is propagated though the LTC4314 to the other

side. For VCC2 > 1.8V, VMIN is the lower of the VCC and

VCC2 voltages. For VCC2 < 1.8V, VMIN is the VCC voltage.

The LTC4314 is designed to sink a minimum total bus

current IOL of 4mA while holding a VOL of 0.4V. If multiple

output channels are enabled, the bus current of all enabled

channels needs to be summed to get the total bus current.

See the Typical Performance Characteristics curves for IOL

as a function of temperature.

A high occurs when all devices on the input and output

sides release high. Once the bus voltages rise above the

VIL, RISING level, which is determined by the state of the ACC

pin, the buffers are turned off. The rise time accelerators

are turned on at a slightly higher voltage. The rise time

accelerators accelerate the rising edges of the SDA,SCL

inputs and selected outputs up to voltages of 0.9•VCC and

0.8•VCC2 respectively, provided that the busses on their

own are rising at a minimum rate of 0.2V/μs as determined

by the slew rate detectors. ACC is a 3-state input that con-

trols VIL,RISING, the rise time accelerator turn-on voltage

and the rise time accelerator pull-up strength.

The LTC4314 detects a bus stuck low (fault) condition

when both clock and data busses are not simultaneously

high at least once in 45ms. The voltage monitoring for a

stuck low condition is done on the common internal node

of the clock and data outputs. Hence a stuck low condition

is detected only if it occurs on an enabled output channel.

When a stuck bus occurs, the LTC4314 asserts the FAULT

ﬂ ag. If DISCEN is tied high, the LTC4314 also disconnects

the input and output sides. After waiting at least 40μs, it

generates up to sixteen 5.5kHz clock pulses on the enabled

SCLOUT pins and a stop bit to attempt to free the stuck

bus. If the bus recovers high before 16 clocks are issued,

the LTC4314 ceases issuing clocks and generates a stop

bit. If DISCEN is tied low, a stuck bus event only causes

FAULT ﬂ ag assertion. Disconnection of the input and output

sides and clock generation do not occur. Once the stuck

bus recovers and the fault has been cleared, in order for a

connection to be established between the input and output

sides, all ENABLE pins need to be driven low followed

by the assertion high of the desired ENABLE pins. When

powering into a stuck low condition, the LTC4314 upon

exiting UVLO will connect the input and output sides for

45ms until a stuck bus timeout event is detected.

LTC43 1 4 L7 LJDW

LTC4314

4314f

APPLICATIONS INFORMATION

The LTC4314 is a 1:4 pin selectable I2C multiplexer that

provides a high noise margin, capacitance buffering and

level translation capability on its clock and data pins. Rise

time accelerators accelerate rising edges to enable opera-

tion at high frequencies with heavy loads. These features

are illustrated in the following subsections.

Rise Time Accelerators and DC Hold-Off Voltage

Once the LTC4314 has exited UVLO and a connection has

been established between the SDA and SCL inputs and

outputs, the rise time accelerators on both the input and

output sides of the SDA and SCL busses are activated based

on the state of the ACC pin and the VCC2 supply voltage.

During positive bus transitions of at least 0.2V/μs, the

rise time accelerators provide pull-up currents to reduce

rise time. Enabling the rise time accelerators allows users

to choose larger bus pull-up resistors, reducing power

consumption and improving logic low noise margins, to

design with bus capacitances outside of the I2C speciﬁ ca-

tion, or switch at a higher clock frequency. The ACC pin

sets the turn-off threshold voltage for the buffers, the

turn-on voltage for the rise time accelerators, and the rise

time accelerator pull-up current strength. The ACC func-

tionality is shown in Table 1. Set ACC open or high when a

high noise margin is required, such as when the LTC4314

is used in a system having I2C devices with VOL > 0.4V.

The ACC pin has a resistive divider between VCC and

ground to set its voltage to 0.5•VCC if left open. In the

current source accelerator mode, the LTC4314 provides

a 3mA constant current source pull-up.

Table 1. ACC Control of the Rise Time Accelerator Current IRTA

and Buffer Turn-Off Voltage VIL,RISING

ACC IRTA VRTA(TH) VIL, RISING

Low Strong 0.8V 0.6V

Hi-Z 3mA 0.4•VMIN 0.33•VMIN

High None N/A 0.33•VMIN

In the strong mode, the LTC4314 sources pull-up current

to make the bus rise at 75V/μs (typical). The strong mode

current is therefore directly proportional to the bus capaci-

tance. The LTC4314 is capable of sourcing a maximum of

45mA of current in the strong mode. The effect of the rise

time accelerator strength is shown in the SDA waveforms in

Figures 1 and 2 for identical bus loads for a single enabled

output channel. The rise time accelerator supplies 3mA and

10mA of pull-up current (IRTA) respectively in the current

source and strong modes for the bus conditions shown

in Figures 1 and 2. The rise time accelerator turn-on volt-

age is also lower in the strong mode than in the current

source mode. For identical bus loading conditions, the

busses return high faster in Figure 1 compared to Figure 2

because of both the higher IRTA and the lower turn-on volt-

age of the rise time accelerator. In each ﬁ gure, note that the

input and output rising waveforms are nearly coincident

due to the input and output busses having nearly identical

bus current and capacitance.

Figure 1. Bus Rising Edge for the Strong

Accelerator Mode

Figure 2. Bus Rising Edge for the

Current Source Accelerator Mode

500ns/DIV

2V/DIV

4314 F01

CIN = COUT = 200pF

RBUS = 10kΩ

ACC = 0

VCC = VCC = 5V

SDAOUT1

SDAIN

500ns/DIV

2V/DIV

4314 F02

CIN = COUT = 200pF

RBUS = 10kΩ

ACC = OPEN

VCC = VCC2 = 5V

SDAOUT1

SDAIN

LTC4314 % 3%“ u”— L7LJCUEN2

LTC4314

4314f

APPLICATIONS INFORMATION

Figure 3. Connection of the LTC4314 in a Level Shift Application. VCC2 is

Less than or Equal to the Minimum Bus Supply Voltage on the Output Side

LTC4314

GND

VCC VCC2

4314 F03

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLIN

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

ACC

DISCEN

FAULT

SCLIN

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

3.3V

FAULT

10k

0.01μF

3.3V 3.3V

10k

0.01μF

10k

•••

If VCC2 is tied low, the output side rise time accelerators

are disabled independent of the state of the ACC pin. Using

a combination of the ACC pin and the VCC2 voltage allows

the user independent control of the input and output side

rise time accelerators. The rise time accelerators are also

internally disabled during power-up and VCC2 transitions

as described in the Operation section, as well as during

automatic clocking and stop bit generation for a bus stuck

low recovery event.

The rise time accelerators when activated pull the bus up

to 0.9•VCC on the input side of the SDA and SCL lines. On

the output side the SDAOUT and SCLOUT lines are pulled

up by the rise time accelerators to 0.8•VCC2. For VCC2

voltages approaching 2.3V, acceleration of the bus may

not be seen all the way to 0.8•VCC2 due to the threshold

voltage of the NFET pass device.

Supply Voltage Considerations in Level Translation

Applications

Care must be taken to ensure that the bus supply voltages

on the input and output sides are greater than 0.9•VCC and

0.8•VCC2 respectively to ensure that the bus is not driven

above the bus supplies by the rise time accelerators. This

is usually accomplished in a level shifting application by

tying VCC to the input bus supply and VCC2 to the lowest

bus supply on the output side as shown in Figure 3.

If VCC2 is grounded, the multiplexer pass gates are powered

from VCC. In this case the minimum output bus supply

of the enabled channels should be greater than or equal

to VCC to prevent cross-conduction between the enabled

output channels. This is shown in Figure 4. Grounding VCC2

as shown in Figure 4 disables the output side rise time

accelerators independent of the state of the ACC pin. The

input rise time accelerators in this conﬁ guration continue

to be controlled by the ACC pin and can be enabled inde-

pendently. In Figure 4, ACC is left open to obtain a high VIL

and a 3mA rise time accelerator current on the input side.

Pull-Up Resistor Value Selection

To guarantee that the rise time accelerators are activated

during a rising edge, the bus must rise on its own with

a positive slew rate of at least 0.4V/μs. To achieve this,

choose a maximum RBUS using equation 1:

RBUS(Ω)≤VDD,BUS(MIN) −VRTA(TH)

()

0.4V/µs • CBUS

(1)

RBUS is the bus pull-up resistor, VDD, BUS(MIN) the mini-

mum bus pull-up supply voltage, VRTA(TH) the voltage at

which the rise time accelerator turns on, which is a func-

tion of ACC, and CBUS the equivalent bus capacitance.

LTC43 1 4 NH .n— L7 LJUW

LTC4314

4314f

RBUS values on each output channel must also be chosen

to ensure that when all the required output channels are

enabled, the total bus current is ≤4mA. The bus current

in each output channel can be 4mA if only one channel is

enabled at any given time. The RBUS value on the input must

also be chosen to limit the bus current to be ≤4mA. The

bus current for a single bus is determined by equation 2:

IBUS(A)=VDD,BUS −0.4V

RBUS

(2)

Input to Output Offset Voltage and Propagation Delay

The LTC4314 introduces both an offset as well as a

propagation delay for falling edges between the input

and output. When a logic low voltage ≥ 200mV is driven

on any of the LTC4314’s data or clock pins, the LTC4314

regulates the voltage on the opposite side to a slightly

higher value. When SCLIN or SDAIN is driven to a logic

low voltage, SCLOUT or SDAOUT is driven to a slightly

higher voltage, as directed by equation 3 which uses SDA

as an example:

VSDAOUT(V)=VSDAIN +45mV

+(10Ω+RMUX )• VDD,BUS

RBUS

(3)

Figure 4. Connection of the LTC4314 in a Level Shift Application. VCC is Less than or Equal to the Minimum

Bus Supply Voltages on the Output Side. VCC2 is Grounded to Disable Output Rise Time Accelerators

LTC4314

GND

VCC VCC2

4314 F04

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLIN

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

ACC

DISCEN

FAULT

SCLIN

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

3.3V

FAULT

10k

0.01μF

3.3V 3.3V

10k

•••

APPLICATIONS INFORMATION

VDD, BUS is the output bus voltage, RBUS is the output bus

pull-up resistance and RMUX is the resistance of the channel

transmission gate in the multiplexer shown in the block

diagram. The offset is affected by the VCC2 voltage and bus

current. A higher VCC2 voltage (VCC if VCC2 is grounded)

reduces RMUX leading to a lower offset. See the Typical

Performance Characteristics plots for the variation of RMUX

as a function of VCC2 and temperature. When SCLOUT or

SDAOUT is driven to a logic low voltage ≥ 200mV, SCLIN

or SDAIN is regulated to a logic low voltage, as directed

by equation 4 which uses SDA as an example:

VSDAIN(V)=VSDAOUT +45mV +10Ω•VDD, BUS

RBUS

(4)

The SCLOUT/SDAOUT to SCLIN/SDAIN offset is lower than

the reverse case as the multiplexer transmission gate does

not affect this offset. For driven logic low voltages <200mV,

the above equations do not apply as the saturation voltage

of the open collector output transistor results in a higher

offset. However, the offset is guaranteed to be less than

400mV for a total bus pull-up current of 4mA under all

conditions. See the Typical Performance Characteristics

curves for the buffer offset voltages as a function of the

driven logic low voltage and bus pull-up current.

LTC4314 m IH|~ .||—| |_| L7LJCUEN2

LTC4314

4314f

Figure 5. Cascading an LTC4314 with Another LTC4314 and LTC Bus Buffers. Only the SCL Pathway Is Shown for Simplicity

APPLICATIONS INFORMATION

The high-to-low propagation delay arises due to both the

ﬁ nite response time of the buffers and their ﬁ nite current

sink capability. See the Typical Performance Characteristics

curves for the propagation delay as a function of the bus

capacitance.

Cascading LTC4314 devices and other LTC Bus Buffers

Multiple LTC4314s can be cascaded or the LTC4314 can

be cascaded with other LTC bus buffers as required by the

application. An example is shown for the clock pathway

in Figure 5 where an LTC4314 is cascaded with another

LTC4314 and some select LTC bus buffers. The data path

is identical. When using such cascades, users should be

aware of the additive logic low offset voltages VOS when

determining system noise margin. If the sum of the offsets

(refer to equations 3 and 4 and to the data sheets of the

corresponding bus buffers) plus the worst-case driven

logic low voltage across the cascade exceeds the buffer

turn-off voltage, signals will not be propagated across the

cascade. Also the minimum rise time accelerator (RTA)

turn-on voltage (wherever applicable) of each device in

the cascade should also be greater than the maximum

buffer turn-off voltage of all the devices in the cascade.

This condition is required to prevent contention between

one device’s buffer and another’s RTA.

Based on this requirement, the LTC4314 can be cascaded

with the LTC4303 and LTC4307 if its RTA turn-on voltage

is set to be 0.8V (ACC low). The LTC4314 can be cascaded

with the LTC4301 and LTC4301L under all ACC settings

as these devices do not have RTAs. The LTC4314 can

be cascaded with the LTC4302, LTC4304, LTC4305 and

LTC4306 if its RTAs are set to turn on at 0.8V (ACC low)

or under all ACC settings if the RTAs on the other bus buf-

fers are disabled. Finally two LTC4314s can be cascaded

if their ACC pins are tied to the same state, HIGH, LOW or

OPEN, or if the ACC pin of one LTC4314 is tied high and

the other is left open.

LTC4314

GND

VCC VCC2

4314 F05

SCLOUT1

SCLOUT2

SCLOUT3

SCLOUT4

SCLIN

ACC

SCLIN

10k

0.01μF

3.3V

10k

LTC4314

GND

VCC VCC2

SCLOUT1

SCLOUT4

SCLIN

ACC

LTC4301

GND

VCC

SCLOUTSCLIN

SCLOUT1

SCLOUT4

SCLOUT5

3.3V

10k

LTC4303

GND

VCC

SCLOUTSCLIN SCLOUT6

10k

LTC4307

GND

VCC

SCLOUTSCLIN SCLOUT7

10k

0.01μF

ttt

LTC43 1 4 ”HF w. W «H; w. HH 1: J w L7 LJUW

LTC4314

4314f

APPLICATIONS INFORMATION

Figure 6. Paralleling LTC4314 Devices to Realize an 1:8 Multiplexer

LTC4314

GND

VCC VCC2

4314 F06

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLIN

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

ACC

DISCEN

FAULT

ENABLE1

ENABLE2

ENABLE3

ENABLE4

3.3V

10k

0.01μF

3.3V 3.3V

10k

I2C

DEVICE

LTC4314

GND

VCC VCC2

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLOUT5

SDAOUT5

SCLOUT8

SDAOUT8

SCLIN

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

ACC

DISCEN

FAULT

ENABLE5

ENABLE6

ENABLE7

ENABLE8

0.01μF C4

0.01μF

3.3V 3.3V

R10

10k

R12

10k

R11

10k

•••

10k

3.3V

10k

Paralleling LTC4314 Devices

The LTC4314s can be paralleled to perform higher order

multiplexing. Figure 6 shows a 1:8 multiplexer with two

LTC4314s.

LTC4314 L7LJCUEN2

LTC4314

4314f

Figure 7. LTC4314s Conﬁ gured for a Radially Connected Redundant Telecommunications Shelf Manager Application

in a 6 × 4 Arrangement. The ENABLE Pins on Only One of the Shelf Managers Are High at Any Time. Only the SDA

Path Is Shown for Simplicity

APPLICATIONS INFORMATION

Radial Telecommunications

Figure 7 shows the use of the LTC4314 in a radial telecom-

munications application. Two shelf managers are wired to

communicate with slave I2C devices for redundancy. Each

shelf manager can have as many LTC4314s as required

depending on the number of boards in the system and

the desired radial/star conﬁ guration. The ENABLE pins of

the LTC4314s inside only one shelf manager are asserted

high at any time. For simplicity, in Figure 7 only the SDA

pathway is shown. The SCL pathway is identical.

LTC4314 #1

GND

VCC

3.3V

VCC2

SHMC #1

SHMC #2

(IDENTICAL TO SHMC#1)

4314 F07

SDAOUT1

SDAOUT2

SDAOUT3

SDAOUT4

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

ACC

ENABLE1A

ENABLE2A

ENABLE3A

ENABLE4A

μP

10k

BACKPLANE

IPMB-A

SDA1

IPMB-A

SDA24

IPMB-B

SDA1

SDA24

SDA1

FRU #1

FRU #24

3.3V

10k

3.3V

ttt

LTC4314 #6

GND

VCC

3.3V

VCC2

SDAOUT1

SDAOUT2

SDAOUT3

SDAOUT4

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

ACC

ENABLE21A

ENABLE22A

ENABLE23A

ENABLE24A

10k

3.3V

ttt

IPMB-A (×24)

IPMB-B (×24)

IPMB-B

SDA24

ttt

SDA24

SDA1

ttt

LTC43 1 4 .||_ L7 LJUW

LTC4314

4314f

APPLICATIONS INFORMATIONAPPLICATIONS INFORMATION

Nested Addressing

The LTC4314 can provide nested addressing when its

ENABLE pins are used as channel select bits. This is shown

in Figure 8 where the master communicates with slave

devices that have the same address by selectively enabling

only one output channel at a time. Since slaves have the

same address care must be taken that the master never

enables channels 1 and 4 at the same time.

Stop Bit Generation and FAULT Clocking

If the output bus sticks low (SCLOUT or SDAOUT stuck

low for at least 45ms) on one of the enabled channels

and DISCEN is high, the LTC4314 attempts to unstick the

bus by ﬁ rst breaking the connection between the input

LTC4314

GND

VCC VCC2

4314 F08

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLIN

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

ACC

DISCEN

FAULT

ENABLE1

ENABLE2

ENABLE3

ENABLE4

3.3V

10k

FAULT

10k

0.01μF

3.3V 3.3V

10k

ADDRESS = 1001 000

10k

I2C

DEVICE

I2C

DEVICE

I2C

DEVICE

•••

Figure 8. Nested Addressing

Figure 9. Bus Waveforms During a SDAOUT1

Stuck Low and Recovery Event

and output, asserting FAULT low and generating up to

16 clock pulses at 5.5kHz on the SCLOUT node common

to the four channels. Should the stuck bus release high

during this period, clock pulsing is stopped, a stop bit is

generated and FAULT ﬂ ag is cleared. In order for a con-

nection to be established between the input and output, all

ENABLES have to be taken low followed by an assertion

of the ENABLES of the required channels. This process is

illustrated in Figure 9 for the case where only channel 1 is

active and SDAOUT1 starts out stuck low and then recov-

ers. If DISCEN is tied low and a stuck low event occurs,

the FAULT ﬂ ag is driven low, but the connection between

the input and output is not broken and clock generation

is not done.

1ms/DIV 4314 F09

SCLOUT1

5V/DIV

SDAOUT1

5V/DIV

SDAIN

5V/DIV

ENABLE1

5V/DIV

CONNECT AT RISING EDGE OF ENABLE1

DISCONNECT

AT TIMEOUT

STUCK LOW>45ms

AUTOMATIC CLOCKING

DRIVEN LOWRECOVERS

LTC4314 M—‘ .”_| II—U .”_| .n. L7LJCUEN2

LTC4314

4314f

Figure 10. The LTC4314 Conﬁ gured as a 2:1 Demultiplexer in a System with Redundancy

LTC4314

GND

VCC2 VCC

4314 F10

SDAIN

SCLIN

ACC

DISCEN

FAULT

SDAOUT1

SCLOUT1

ENABLE1

SDAOUT2

SCLOUT2

ENABLE2

SDAOUT3

SCLOUT3

ENABLE3

SDAOUT4

SCLOUT4

ENABLE4

0.01μF

SDA

SCL

FAULT

3.3V

10k

100k

3.3V

R10

10k

20k

BFP405F

50k

PRIMARY

I2C

MASTER

CONTROLLER

CARD

BACKUP

I2C

MASTER

CONTROLLER

CARD

APPLICATIONS INFORMATION

Demultiplexer Function

Due to its bi-directional nature, the LTC4314 can be used

as a demultiplexer. This is shown in Figure 10 where two

channels are used to drive I2C data from the master side

with redundancy to the slave side. In this application the

SDAOUT/SCLOUT channels serve as the inputs while the

SDAIN/SCLIN channel is the output. Redundancy on the

master side provides protection against power supply

failure. In Figure 10, if the 5V bus supply on channel 1

falls below 1.4V, channel 1 gets disabled as ENABLE1 is

driven below its digital threshold. Simultaneously, the VBE

of the pull-down device on ENABLE4 falls below 0.7V and

it turns off. This causes ENABLE4 to be pulled up by R7

which in turn enables channel 4, causing control to be

transferred to the backup I2C master device.

Hot-Swapping

Figure 11 shows the LTC4314 in a typical hot-swapping

application where the LTC4314 is on the backplane and I/O

cards plug into the downstream channels. The outputs must

idle high and the corresponding output channel must be

disabled before an I/O card can be plugged or unplugged

from an output channel. Figure 11 also shows the use of

a non-compliant I2C device with the LTC4314. The high

noise margin of the LTC4314 supports logic low levels up

to 0.3 •VCC, allowing devices to drive greater than 0.4V

logic low levels on the block and data lines.

Level Translating to Bus Voltages < 2.25V

The LTC4314 can be used for level translation to bus volt-

ages below 2.25V if certain conditions are met. In order to

perform this level translation, RTAs on the low voltage side

need to be disabled in order to prevent an over drive of

the low voltage bus. This can be accomplished by forcing

ACC high or grounding VCC2. If one of the output chan-

nels is pulled up to the low voltage bus supply, all other

output channels need to be disabled when this channel

is active, in order to prevent cross conduction between

the output channels. Since the buffer turn-on and turn-off

voltages are 0.3•VMIN, the minimum bus supply voltage

is determined by equation 5:

VDD,BUS(MIN) ≥0.3 • VMIN

0.7

(5)

in order to meet the VIH = 0.7 •VDD,BUS requirement and

not impact the high side noise margin. Users willing to live

with a lower logic high noise margin can level translate

down to 1.5V. An example of voltage level translation from

LTC43 1 4 5v { .___ L7 LJUW

LTC4314

4314f

APPLICATIONS INFORMATION

Figure 11. SDA, SCL Hot Swap™ and Operation with a Non-Compliant I2C Device

LTC4314

GND

VCC VCC2

4314 F12

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLIN

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

ACC

DISCEN

FAULT

SCLIN

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

3.3V

FAULT

10k

0.01μF

3.3V 1.8V

10k

0.01μF

10k

•••

Figure 12. Level Shifting Down to 1.8V Using the LTC4314. VCC2 Is Grounded to Disable the Rise Time Accelerator

on the Low Voltage Bus. ENABLE2-4 Must Be Low Whenever ENABLE1 Is High

3.3V to 1.8V is illustrated in Figure 12, where a 3.3V input

voltage level is translated to a 1.8V output voltage level on

channel 1. Tying VCC to 3.3V satisﬁ es equation 5. Grounding

VCC2 disables the RTA on the low voltage channel. VMIN

defaults to VCC under these conditions, making the buf-

fer turn off voltage 0.99V. Channels 2-4 must be disabled

when channel 1 is enabled. A similar voltage translation

can also be performed going from a 3.3V bus supply on

the output side to a 1.8V bus supply on the input side if

ACC is tied high to disable the input RTA and if VCC and

VCC2 are tied to the output side bus supply.

LTC4314

GND

VCC VCC2

4314 F11

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLIN

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

ACC

DISCEN

FAULT

ENABLE1

ENABLE2

ENABLE3

ENABLE4

3.3V

FAULT

10k

0.01μF

3.3V 3.3V

10k

I2C

DEVICE

VOL = 0.6V I2C

DEVICE

IO CARD

CONNECTOR

I2C

DEVICE

IO CARD

CONNECTOR

ttt

LTC4314 I’DDDDDDDDDDI Tiwaaaaaaa i {DDDDDDDDJMEJ i We imagggggggg EXT L7LJCUEN2

LTC4314

4314f

PACKAGE DESCRIPTION

GN Package

20-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.337 – .344*

(8.560 – 8.738)

GN20 (SSOP) 0204

345678910

.229 – .244

(5.817 – 6.198)

.150 – .157**

(3.810 – 3.988)

1617181920 15 14 13 12 11

.016 – .050

(0.406 – 1.270)

.015 p .004

(0.38 p 0.10) s 45o

0o – 8o TYP

.0075 – .0098

(0.19 – 0.25)

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

.004 – .0098

(0.102 – 0.249)

.0250

(0.635)

BSC

.058

(1.473)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 – .165

.0250 BSC.0165 p.0015

.045 p.005

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

LTC43 1 4 PWVNUTCH 05 , R=uzn0Ru25 *7 , mum +/ x45"CHAMFER ‘ \ T ‘ w 20 ¢ \ 1 UAEIHHD ‘ 2 250nm 7 7 7‘ 7 , , J L7 LJUW

LTC4314

4314f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

UDC Package

20-Lead Plastic QFN (3mm × 4mm)

(Reference LTC DWG # 05-08-1742 Rev Ø)

3.00 p 0.10 1.50 REF

4.00 p 0.10

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 p 0.10

19 20

BOTTOM VIEW—EXPOSED PAD

2.50 REF

0.75 p 0.05

R = 0.115

TYP

PIN 1 NOTCH

R = 0.20 OR 0.25

s 45o CHAMFER

0.25 p 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UDC20) QFN 1106 REV Ø

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 p0.05

0.25 p0.05

2.50 REF

3.10 p 0.05

4.50 p 0.05

1.50 REF

2.10 p 0.05

3.50 p 0.05

PACKAGE OUTLINE

R = 0.05 TYP

1.65 p 0.10

2.65 p 0.10

1.65 p 0.05

2.65 p 0.05

0.50 BSC

LTC4314 II-II- II-II- ||||Iw 11 W |||| HF» :11 L7Hﬂ§N2

LTC4314

4314f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 1210 • PRINTED IN USA

RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

LTC4300A-1/

LTC4300A-2/

LTC4300A-3

Hot-Swappable 2-Wire Bus Buffers -1: Bus Buffer with READY and ENABLE

-2: Dual Supply Buffer with ACC

-3: Dual Supply Buffer with ENABLE

LTC4302-1/

LTC4302-2

Addressable 2-Wire Bus Buffer Address Expansion, GPIO, Software Controlled

LTC4303

LTC4304

Hot-Swappable 2-Wire Bus Buffer with Stuck Bus

Recovery

Provides Automatic Clocking to Free Stuck I2C Busses

LTC4305

LTC4306

2- or 4-Channel, 2-Wire Bus Multiplexers with

Capacitance Buffering

2 or 4 Software Selectable Downstream Busses, Stuck Bus Disconnect,

Rise Time Accelerators, Fault Reporting, ±5kV HBM ESD Tolerance

LTC4307 Low Offset Hot-Swappable 2-Wire Bus Buffer with

Stuck Bus Recovery

60mV Bus Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time

Accelerators, ±5kV HBM ESD Tolerance

LTC4307-1 High Deﬁ nition Multimedia Interface (HDMI) Level

Shifting 2-Wire Bus Buffer

60mV Buffer Offset, 3.3V to 5V Level Shifting, ±5kV HBM ESD Tolerance

LTC4308 Low Voltage, Level Shifting Hot-Swappable 2-Wire

Bus Buffer with Stuck Bus Recovery

Bus Buffer with 1V Pre-Charge, ENABLE and READY,

Level Translation to 1V Busses, Output Side Rise Time Accelerators

LTC4309 Low Offset Hot-Swappable 2-Wire Bus Buffer with

Stuck Bus Recovery

60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time

Accelerators, ±5kV HBM ESD Tolerance

LTC4311 Low Voltage I2C/SMBus Accelerator Rise Time Acceleration with ENABLE and ±8kV HBM ESD Tolerance

LTC4310-1/

LTC4310-2

Hot-Swappable I2C Isolators LTC4310-1: 100kHz Bus

LTC4310-2: 400kHz Bus

LTC4312 Pin-Selectable, 2-Channel, 2-Wire Multiplexer with

Bus Buffer

2 Pin-Selectable Downstream Busses, Stuck Bus Disconnect and Recovery,

Selectable Rise Time Accelerator Current and Activation Voltage,

±4kV HBM ESD Tolerance

1:8 Multiplexer with Level Translation and Operation with a Non-Compliant I2C Device

LTC4314

GND

VCC VCC2

4314 TA02

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLIN

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

ACC

DISCEN

FAULT

ENABLE1

ENABLE2

ENABLE3

ENABLE4

3.3V

10k

0.01μF

3.3V 3.3V

10k

3.3V

10k

I2C

DEVICE

LTC4314

GND

VCC VCC2

SCLOUT1

SDAOUT1

SCLOUT4

SDAOUT4

SCLOUT5

SDAOUT5

SCLOUT8

SDAOUT8

SCLIN

SDAIN

ENABLE1

ENABLE2

ENABLE3

ENABLE4

ACC

DISCEN

FAULT

ENABLE5

ENABLE6

ENABLE7

ENABLE8

0.01μF C4

0.01μF

3.3V 3.3V

R10

10k

R12

10k

R11

10k

ttt

NON-COMPLIANT

I2C DEVICE

VOL = 0.6V

Scheda tecnica LTC4314 di Analog Devices Inc.

INFORMAZIONI

GUIDA

CONTATTI

SEGUICI