Scheda tecnica LNK574,76 di Power Integrations

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www.power.com November 2015
Zero No-Load or Zero Standby Consumption
with up to 1 mW Output Load
This Product is Covered by Patents and/or Pending Patent Applications.
LNK574/576
LinkZero-LP
Output Power Table1
Product4
230 VAC ±15% 85-265 VAC
Adapter2Open
Frame3Adapter2Open
Frame3
LNK574DG 3 W 3 W 3 W 3 W
LNK576DG 6 W 9 W 5 W 8 W
Table 1. Output Power Table.
Notes:
1. IEC 62301 Clause 4.5 rounds standby power use below 5 mW to zero.
2. Typical continuous power in a non-ventilated enclosed adapter measured at
+50 °C ambient.
3. Maximum practical continuous power in an open frame design with adequate
heat sinking, measured at 50 °C ambient.
4. Packages: D: SO-8C.
Product Highlights
Lowest System Cost with Zero Standby
(1 mW Output Power)
• Automatically enters low consumption power-down mode when load
drops below ~0.2% of full load for LNK576 and ~0.6% for LNK574
• Detects load reconnection and automatically restarts regulation
• Simple upgrade to existing LinkSwitch-LP designs
• Very accurate IC parameter tolerances improve system manu-
facturing yield
• Suitable for low-cost clampless designs
• Frequency jittering greatly reduces EMI filter cost
• Extended package creepage improves system field reliability
Advanced Protection/Safety Features
• Accurate hysteretic thermal shutdown protection – automatic
recovery reduces field returns
• Universal input range allows worldwide operation
• Auto-restart reduces delivered power by >85% during short-circuit
and open-loop fault conditions
• Simple ON/OFF control, no loop compensation needed
• High bandwidth provides excellent transient load response with no
overshoot
EcoSmart™– Energy Efficient
• No-load or standby (1 mW output power) consumption as low as
<5 mW at 230 VAC input (Note 1)
• Easily meets all global energy efficiency regulations with no added
components
• ON/OFF control provides constant efficiency to very light loads
Applications
• Chargers for cell/cordless phones, PDAs, power tools, MP3/portable
audio devices, shavers, etc.
• Standby power supply for TV, video displays, and appliances
Description
The LinkZero™-LP controller incorporates new technology which
enables the device to automatically enter into and wake up from
no-load mode or with 1 mW load while taking less than 5 mW from the
AC power. IEC 62301 specifies measurements of standby power to a
minimum accuracy of 10 mW, and so LinkZero-LP’s consumption of
substantially less than 5 mW at 230 VAC rounds to zero based on the
IEC definition. This low power level is also immeasurable on most
power meters. The accurately specified FEEDBACK (FB) pin voltage
reference enables universal input primary-side regulated power
supplies with accurate constant voltage from 5% to full load. The
start-up and operating power are derived directly from the DRAIN pin
which eliminates start-up circuitry. The internal oscillator frequency is
jittered to significantly reduce both quasi-peak and average EMI,
minimizing filter cost.
Figure 1. Typical Applications – Zero No-Load Charger (a) and Zero Standby
Power Supply (b).
(a) Typical Application Schematic for LNK574DG.
(b) Typical Application Schematic for LNK576DG.
+
LNK574DG
PI-7230-052214
LNK576DG
DC
Output
OP1
PIN < 0.00 W
at 325 VDC in
Power-Down
Mode
OP1
Shunt
Regulator
D
S
FB
BP/M
++
$8 a "RSJZEES.
Rev. D 11/15
2
LNK574/576
www.power.com
Figure 2 Functional Block Diagram.
Figure 3. Pin Configuration.
Pin Functional Description
DRAIN (D) Pin:
The power MOSFET drain connection provides internal operating
current for both startup and steady-state operation.
BYPASS/MULTI-FUNCTIONAL PROGRAMMABLE (BP/M) Pin:
An external bypass capacitor for the internally generated 5.85 V
supply is connected to this pin. The value of capacitor establishes
the power-down period. The minimum value of capacitor is 0.1 mF.
An overvoltage protection disables the switching if the current into
the pin exceeds 6.5 mA (ISD).
FEEDBACK (FB) Pin:
During normal operation, switching of the power MOSFET is
controlled by this pin. MOSFET switching is disabled when a voltage
greater than an internal VFB reference voltage is applied to the
FEEDBACK pin.
The VFB reference voltage is internally adjusted from 1.70 V at full
load to 1.37 V at no-load in CV mode, and 1.70 V to 0.9 V in CC
mode. Below 0.9 V the part enters auto-restart operation.
SOURCE (S) Pin:
This pin is the power MOSFET source connection. It is also the
ground reference for the BYPASS and FEEDBACK pins.
PI-5507-060210
D Package (SO-8C)
BP/M
FB
D
1
2
4
8
7
6
5
S
S
S
S
PI-5509-032714
CLOCK
OSCILLATOR
5.85 V
4.85 V
6.5 V3 V
PU
OVERVOLTAGE
PROTECTION
RESET
0.9 V
FAULT
SOURCE
(S)
S
R
Q
DCMAX
ADJ
AUTO-RESTART
COUNTER
RESET JITTER
BYPASS/
MULTI FUNCTION
(BP/M)
+
-
VILIMIT
LEADING
EDGE
BLANKING
+
−
DRAIN
(D)
BYPASS PIN
UNDERVOLTAGE
CURRENT LIMIT
FEEDBACK
(FB)
OPEN LOOP
PULL UP
Q
+
+
+
+
REGULATOR
5.85 V
GENERATOR
FEEDBACK REF
1.70 V - 1.37 V
CC CUT BACK
1.70 V - 0.9 V
POWER-
DOWN
COUNTER EVENT
COUNTER
SYSTEM
POWER
DOWN/
RESTART
PU
160 or 416
fOSC
CYCLES
power \Megrcmons‘
Rev. D 11/15
3
LNK574/576
www.power.com
LinkZero-LP Functional Description
LinkZero-LP comprises a 700 V power MOSFET switch with a power
supply controller on the same die. Unlike conventional PWM (pulse
width modulation) controllers, it uses a simple ON/OFF control to
regulate the output voltage. The controller consists of an oscillator,
feedback (sense), 5.85 V regulator, BYPASS pin under/overvoltage
protection, over-temperature protection, frequency jittering, current
limit, leading edge blanking, BYPASS pin clamp during operation in
power-down and bypass modes. The controller includes a proprietary
power- down mode that automatically reduces standby consumption
to levels that are immeasurable on most power meters.
Power-Down Mode
The device enters into power-down mode (where MOSFET switching
is disabled) when the total load (power supply output plus bias
winding loads) has reduced to ~0.6% for LNK574 or ~0.2% for
LNK576 of full load. The internal controller detects this condition by
sensing when 160 or 416 cycles have been skipped twice with only
one active switching cycle in between the two sets of 160 for LNK574
or 416 for LNK576 skipped switching cycles. During the power-down
period the BYPASS pin capacitor will discharge from 5.85 V down to
about 3 V at which point the LinkZero-LP will wake up and charge the
BYPASS pin back up to 5.85 V. The wake up frequency is determined
by the user through the choice of the BYPASS pin capacitor value (see
Figure 22 for reference). Once the BYPASS pin has recharged to 5.85 V,
LinkZero-LP senses if the load condition has changed or not, if not
the LinkZero-LP will enter into a new power-down cycle or otherwise
resumes normal operation (See Applications Example section for
more details of power-down mode operation).
Oscillator
The typical oscillator frequency is internally set to an average of
100 kHz. An internal circuit senses the on-time of the MOSFET switch
and adjusts the oscillator frequency so that at large duty cycle (low-
line voltage) the frequency is about 100 kHz and at small duty cycle
(high-line voltage) the oscillator frequency is about 78 kHz. This
internal frequency adjustment is used to make the peak power point
constant over line voltage. Two signals are generated from the
oscillator: the maximum duty cycle signal (DCMAX) and the clock signal
that indicates the beginning of a switching cycle.
The oscillator incorporates circuitry that introduces a small amount of
frequency jitter, typically 6% of the switching frequency, to minimize
EMI. The modulation rate of the frequency jitter is set to 1 kHz to
optimize EMI reduction for both average and quasi-peak emissions.
The frequency jitter, which is proportional to the oscillator frequency,
should be measured with the oscilloscope triggered at the falling
edge of the drain voltage waveform. The oscillator frequency is
linearly reduced when the FEEDBACK pin voltage is lowered from
1.70 V down to 1.37 V.
Feedback Input Circuit CV Mode
The feedback input circuit reference is set at 1.70 V at full load and
gradually reduces down to 1.37 V at no-load. When the FEEDBACK
pin voltage reaches a VFB reference voltage (1.70 V to 1.37 V)
depending on the load, a low logic level (disable) is generated at the
output of the feedback circuit. This output is sampled at the
beginning of each cycle. If high, the power MOSFET is turned on for
that cycle (enabled), otherwise the power MOSFET remains off
(disabled). Since the sampling is done only at the beginning of each
cycle, subsequent changes in the FEEDBACK pin voltage during the
remainder of the cycle are ignored.
Feedback Input CC Mode
When the FEEDBACK pin voltage at full load falls below 1.70 V, the
oscillator frequency linearly reduces to typically 43% at the auto-
restart threshold voltage of 0.9 V. This function limits the power
supply output power at output voltages below the rated voltage
regulation threshold VR.
5.85 V Regulator
The BYPASS pin voltage is regulated by drawing a current from the
DRAIN whenever the MOSFET is off if needed to charge up the
BYPASS pin to a typical voltage of 5.85 V. When the MOSFET is on,
LinkZero-LP runs off of the energy stored in the bypass capacitor.
Extremely low power consumption of the internal circuitry allows
LinkZero-LP to operate continuously from the current drawn from the
DRAIN pin. A bypass capacitor value of 0.1 mF is sufficient for both
high frequency decoupling and energy storage.
6.5 V Shunt Regulator and 8.5 V Clamp
In addition, there is a shunt regulator that helps maintain the BYPASS
pin at 6.5 V when current is provided to the BYPASS pin externally.
This facilitates powering the device externally through a resistor from
the bias winding or power supply output in non-isolated designs, to
decrease device dissipation and increase power supply efficiency.
The 6.5 V shunt regulator is only active in normal operation, and
when in power-down mode a clamp at a higher voltage (typical 8.5 V)
will clamp the BYPASS pin.
BYPASS Pin Undervoltage Protection
The BYPASS pin undervoltage circuitry disables the power MOSFET
when the BYPASS pin voltage drops below 4.85 V. Once the BYPASS
pin voltage drops below 4.85 V, it must rise back to 5.85 V to enable
(turn on) the power MOSFET.
BYPASS Pin Overvoltage Protection
If the BYPASS pin gets pulled above 6.5 V (BPSHUNT)and the current
into the shunt exceeds 6.5 mA a latch will be set and the power
MOSFET will stop switching. To reset the latch the BYPASS pin has to
be pulled down to below 1.5 V.
Over-Temperature Protection
The thermal shutdown circuit senses the die temperature. The
threshold is set at 142 °C typical with a 70 °C hysteresis. When the
die temperature rises above this threshold (142 °C) the power
MOSFET is disabled and remains disabled until the die temperature
falls by 70 °C, at which point the MOSFET is re-enabled.
Current Limit
The current limit circuit senses the current in the power MOSFET.
When this current exceeds the internal threshold (ILIMIT), the power
MOSFET is turned off for the remaining of that cycle. The leading
edge blanking circuit inhibits the current limit comparator for a short
time (tLEB) after the power MOSFET is turned on. This leading edge
blanking time has been set so that current spikes caused by
capacitance and rectifier reverse recovery time will not cause
premature termination of the MOSFET conduction.
Auto-Restart
In the event of a fault condition such as output short-circuit,
LinkZero-LP enters into auto-restart operation. An internal counter
clocked by the oscillator gets reset every time the FEEDBACK pin
voltage exceeds the FEEDBACK pin auto-restart threshold voltage
(VFB(AR) typical 0.9 V). If the FEEDBACK pin voltage drops below VFB(AR)
for more than 145 ms to 170 ms depending on the line voltage, the
power MOSFET switching is disabled. The auto-restart alternately
enables and disables the switching of the power MOSFET at a duty
cycle of typically 12% until the fault condition is removed.
AHH MM "RSJZEES.
Rev. D 11/15
4
LNK574/576
www.power.com
A resistor lower than 50 kW in value should always be connected
from FEEDBACK pin to SOURCE pin. For resistor values >50 kW,
device operation is not guaranteed. If for any reason the FEEDBACK
pin is floated, the IC will stop switching.
Open-Loop Condition on the FEEDBACK Pin
When an open-loop condition on the FEEDBACK pin is detected, an
internal pull up current source pulls the FEEDBACK pin up to above
1.70 V and LinkZero-LP stops switching after 160 clock cycles for
LNK574 or 416 clock cycles for LNK576.
Applications Example
The circuit shown in Figure 4 is a typical isolated zero no-load 6 V,
350 mA, constant voltage, and constant current (CV/CC) output
power supply using LinkZero-LP.
AC input differential filtering is accomplished by the π filter formed by
C1, C2 and L1. The proprietary frequency jitter feature of the
LinkZero-LP eliminates the need for any Y capacitor or common-mode
inductor. Wire-wound resistor RF1 is a fusible, flame proof resistor
which is used as a fuse as well as to limit inrush current. Wire-wound
types are recommended for designs that operate ≥132 VAC to
withstand the instantaneous power when AC is first applied as C1 and
C2 charge.
The power supply utilizes simplified bias winding voltage feedback,
enabled by the LinkZero-LP ON/OFF control. The voltage across C5 is
determined by the FEEDBACK pin reference voltage and the resistor
divider formed by R3 and R4. Capacitor C4 provides high frequency
filtering on the FEEDBACK pin to avoid switching cycle pulse
bunching. The FEEDBACK pin reference voltage, which varies with
load, is set to 1.37 V at no-load and gradually increases to 1.70 V at
full load to provide cable drop compensation. In the constant voltage
(CV) region, the LinkZero-LP device enables/disables switching cycles
to maintain the FEEDBACK pin reference voltage. Diode D6 and low
cost ceramic capacitor C5 provide rectification and filtering of the
primary feedback winding waveform. At increased loads, beyond the
maximum power threshold, the IC transitions into the constant
current (CC) region. In this region, the FEEDBACK pin voltage begins
to reduce as the power supply output voltage falls. In order to
maintain a constant output current, the internal oscillator frequency is
reduced in this region until it reaches typically 48% of the starting
frequency. When the FEEDBACK pin voltage drops below the
auto-restart threshold (typically 0.9 V on the FEEDBACK pin), the
power supply enters the auto-restart mode. In this mode, the power
supply will turn off for 1.2 s and then turn back on for 170 ms. The
auto-restart function reduces the average output current during an
output short-circuit condition.
The LinkZero-LP device is self biased through the DRAIN pin.
However, to improve efficiency at high-line, an external bias may be
added using optional components diode D5 and resistor R2.
The power-down (PD) mode duty cycle and the no-load power
consumption is determined by the BYPASS pin capacitor C3. No-load
power consumption can be reduced by a capacitor with higher value.
Higher C3 capacitor values will tend to increase the output ripple in
PD mode – See LinkZero-LP Design Considerations section below.
A clampless primary circuit is achieved due to the very accurate
tolerance current limit trimming techniques used in manufacturing the
LinkZero-LP, plus the transformer construction techniques used. The
peak drain voltage is therefore limited to typically less than 550 V at
265 VAC, providing significant margin to the 700 V minimum drain
voltage specification (BVDSS).
Output rectification and filtering is achieved with output rectifier D7
and filter capacitor C7. Due to the auto-restart feature, the average
short-circuit output current is significantly less than 1 A, allowing low
current rating and low cost rectifier D7 to be used. Output circuitry is
designed to handle a continuous short-circuit on the power supply
output. Although not necessary in this design, a preload resistor may
be used at the output of the supply to reduce output voltage at
no-load.
Figure 4. Schematic of 2.1 W, 6 V, 350 mA, 0.00 W Adapter/Charger.
PI-6086-072110
D
S
FB
BP/M
R1
4.7 kΩ
R3
113 kΩ
1%
R2
82 kΩ
R5
5.1 Ω
R4
9.09 kΩ
1%
RF1
10 Ω
2 W
D7
SS15
D5
1N4148
D6
DL4003
D1
1N4007
D2
1N4007
D3
1N4007
D4
1N4007
T1
EF16
5
NC
9
8
2
1
4
C7
330 µF
16 V
C4
1 nF
50 V
C5
220 nF
50 V
C6
220 pF
100 V
C3
220 nF
50 V
L1
1.0 mH
6 V, 350 mA
RTN
U1
LNK574DG
LinkZero-LP
85 - 265
VAC
C1
3.3 µF
400 V
C2
3.3 µF
400 V
IO
IR
VR
VO
Rated Output Power = VR × IR
PI-5510-082310
power \Megrcmons‘
Rev. D 11/15
5
LNK574/576
www.power.com
LinkZero-LP Power-Down (PD) Mode
Design Considerations
The LinkZero-LP goes into PD mode when the output power supply
load is reduced enough that 160 for LNK574 or 416 for LNK576
consecutive switching cycles are skipped twice with only one active
switching cycle in between the two sets of 160 for LNK574 or 416 for
LNK576 skipped switching cycles. This corresponds to ~0.6% for
LNK574 or ~0.2% for LNK576 of the full load power capability of the
LinkZero-LP.
Even when the power supply output load is completely removed, any
preload resistor on the output and the components connected to the
bias winding still represent a load on the transformer. The feedback
circuitry connected to the bias winding should therefore be designed
to represent <0.6% for LNK574 or <0.2% for LNK576 of the power
supply full load. Otherwise LinkZero-LP will not be able to detect a
no-load condition on the output and will not enter PD mode thereby
disabling the benefit of zero no-load input power.
In the case of the design of Figure 4, the power supply full load
output power is 2.1 W (6 V, 350 mA). The bias winding load should
therefore be designed to be <<0.6% of this (<12.6 mW). In the
example of Figure 4, the average no-load voltage across bias winding
capacitor C5 is approximately 20 V. The loading of R3, R4 and R2 (if
used) should therefore be chosen to present <12.6 mW load with this
bias voltage. In the case shown, the R2 path consumes ~3.3 mW and
R3 and R4 also consumes ~3.3 mW. So the total consumption of
6.6 mW meets the criteria necessary to ensure the power supply will
enter PD mode when the power supply load is removed. Adjusting
the power consumption of the circuitry connected to the bias winding
can therefore be used to adjust the power supply output power
threshold at which the LinkZero-LP goes into PD mode.
It can be seen therefore that, if desired, PD mode can be avoided
altogether simply by adding a preload resistor on the output of the
power supply or increasing the load on the bias winding to >0.6%
(plus margin) of the power supply maximum power capability for
LNK574 or >0.2% for LNK576.
When the LinkZero-LP is in PD mode, the time taken for the BYPASS
pin voltage to discharge to VBPPDRESET (~3 V) determines the duration
of the PD off-time. The duration of the PD off-time also determines
the ripple on the output voltage.
If components D5 and R2 are not used in Figure 4, this time is
determined purely by the choice of C3. If however D5 and R2 are
used to provide an external BYPASS pin supply, then a combination of
the energy stored in C5 and C3 determine the PD off-time before the
BYPASS pin voltage reaches the VBP(PU) (~3 V).
In either case, C5 is completely discharged through R3 and R4 during
the PD off-time (D5 prevents the BYPASS capacitor C3 being
discharged through this path). C5 is therefore kept as small as
possible to reduce the power supply no-load input power consumption
associated with recharging this capacitor at the start of the next PD
on-time. The minimum value of C5 is determined by the time
constant set up with the feedback resistors R3 and R4 to avoid
excessive cycle by cycle ripple on C5 influencing the output voltage
regulation. The typical choice for C5 is between 100 nF and 330 nF.
When D5 and R2 are used, the minimum value of bias winding
capacitor C5 is again governed by voltage regulation performance so
the value of BYPASS pin capacitor C3 is typically reduced to reduce
PD off-time period if required. A minimum C3 value of
47 nF is recommended.
PCB Layout Considerations
LinkZero-LP Layout Considerations
Layout
See Figure 5 for a recommended circuit board layout for LinkZero-LP
(U1).
Single Point Grounding
Use a single point ground (Kelvin) connection from the input filter
capacitor to the area of copper connected to the SOURCE pins.
Bypass Capacitor (CBP), FEEDBACK Pin Noise Filter Capacitor
(CFB) and Feedback Resistors
To minimize loop area, these two capacitors should be physically
located as near as possible to the BYPASS and SOURCE pins, and
FEEDBACK pin and SOURCE pins respectively. Also note that to
minimize noise pickup, feedback resistors RFB1 and RFB2 are placed
close to the FEEDBACK pin.
Primary Loop Area
The area of the primary loop that connects the input filter capacitor,
transformer primary and LinkZero-LP should be kept as small as
possible.
Primary Clamp Circuit
An external clamp may be used to limit peak voltage on the DRAIN
pin at turn off. This can be achieved by using an RCD clamp or a
Zener (~200 V) and diode clamp across the primary winding. In all
cases, to minimize EMI, care should be taken to minimize the circuit
path from the clamp components to the transformer and LinkZero-LP
(U1).
Thermal Considerations
The copper area underneath the LinkZero-LP (U1) acts not only as a
single point ground, but also as a heat sink. As it is connected to the
quiet source node, this area should be maximized for good heat
sinking of U1. The same applies to the cathode of the output diode.
Y Capacitor
The placement of the Y-type capacitor (if used) should be directly
from the primary input filter capacitor positive terminal to the
common/return terminal of the transformer secondary. Such a
placement will route high magnitude common-mode surge currents
away from U1. Note: If an input π EMI filter is used, the inductor in
the π filter should be placed between the negative terminals on the
input filter capacitors.
Output Diode (DO)
For best performance, the area of the loop connecting the secondary
winding, the output diode (DO) and the output filter capacitor (CO)
should be minimized. In addition, sufficient copper area should be
provided at the anode and cathode terminals of the diode for heat
sinking. A larger area is preferred at the electrically “quiet” cathode
terminal. A large anode area can increase high frequency conducted
and radiated EMI. Resistor RS and CS represent the secondary side RC
snubber.
"RSJZEES.
Rev. D 11/15
6
LNK574/576
www.power.com
Quick Design Checklist
As with any power supply design, all LinkZero-LP designs should be
verified on the bench to make sure that component specifications are
not exceeded under worst-case conditions. The following minimum
set of tests is strongly recommended:
1. Maximum drain voltage – Verify that VDS does not exceed 660 V at
the highest input voltage and peak (overload) output power. This
margin to the 700 V BVDSS specification gives margin for design
variation, especially in clampless designs.
2. Maximum drain current – At maximum ambient temperature,
maximum input voltage and peak output (overload) power, verify
drain current waveforms for any signs of transformer saturation
and excessive leading-edge current spikes at startup. Repeat
under steady state conditions and verify that the leading-edge
current spike event is below ILIMIT(MIN) at the end of the tLEB(MIN).
Under all conditions, the maximum drain current should be below
the specified absolute maximum ratings.
Figure 5. PCB Layout of a 2.1 W, 6 V, 350 mA Charger.
+
–
HV DC
IN
+
–
LV DC
OUT
Transformer
CB
RFB1
T1
J3
R6
CO
DO
U1
CFB
RFB2
DBP
RBP
CBP
DBRSCS
PI-6098-092410
3. Thermal check – At specified maximum output power, minimum
input voltage and maximum ambient temperature, verify that the
temperature specifications are not exceeded for LinkZero-LP,
transformer, output diode and output capacitors. Enough thermal
margin should be allowed for part-to-part variation of the RDS(ON)
of LinkZero-LP as specified in the data sheet. Under low-line and
maximum power, maximum LinkZero-LP source pin temperature
of 100 °C is recommended to allow for these variations.
4. Negative drain voltages – Clampless designs may allow the drain
voltage to ring below source and cause reverse currents to flow
from source to drain. Verify that any such current remains within
the envelope shown in Figure 9.
power \Megrcmons‘
Rev. D 11/15
7
LNK574/576
www.power.com
Parameter Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
(Unless Otherwise Specified)
Min Typ Max Units
Control Functions
Output Frequency fOSC
TJ = 25 °C
VFB = 1.70 V, See Note C 93 100 107 kHz
Frequency Jitter Peak-Peak Jitter Compared to
Average Frequency, TJ = 25 °C ±3 %
Ratio of Output
Frequency at
Auto-Restart to fOSC
fOSC(AR)
fOSC
TJ = 25 °C
VFB = VFB(AR)
See Note B
43 %
Maximum Duty Cycle DCMAX 60 63 %
FEEDBACK Pin Voltage
at no Skipped Cycles VFB 1.63 1.70 1.77 V
FEEDBACK Pin
Voltage at 99.4%
Skipped Cycles
VFB(NL) 1.37 V
FEEDBACK Pin Voltage
at Auto-Restart VFB(AR) 0.8 0.9 1.05 V
Minimum Switch
ON-Time tON(MIN) 700 ns
Absolute Maximum Ratings(1,6)
DRAIN Voltage ........................................................-0.3 V to 700 V
Peak DRAIN Current LNK574 .................................... 200 (375) mA(2)
LNK576 .................................... 440 (825) mA(2)
Peak Negative Pulsed Drain Current ................................. -100 mA(3)
Feedback Voltage ........................................................ -0.3 V to 9 V
Feedback Current ...............................................................100 mA
BYPASS Pin Voltage ..................................................... -0.3 V to 9 V
BYPASS Pin Voltage in Power-Down Mode ....... -0.3 V to 11 V(7)
Storage Temperature ................................. -65 °C to 150 °C
Operating Junction Temperature ................-40 °C to 150 °C(4)
Lead Temperature .................................................. 260 °C(5)
Notes:
1. All voltages referenced to SOURCE, TA = 25 °C.
2. Higher peak DRAIN current allowed while DRAIN source voltage
does not exceed 400 V.
3. Duration not to exceed 2 ms.
4. Normally limited by internal circuitry.
5. 1/16 in. from case for 5 seconds.
6. Maximum ratings specified may be applied, one at a time without
causing permanent damage to the product. Exposure to
Absolute Maximum ratings for extended periods of time may
affect product reliability.
7. Maximum current into pin is 300 mA.
Thermal Resistance
Thermal Resistance: D Package:
(qJA) .................................. 100 °C/W(2); 80 °C/W(3)
(qJC) .....................................................30 °C/W(1)
Notes:
1. Measured on the SOURCE pin close to plastic interface.
2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. copper clad.
3. Soldered to 1 sq. in. (645 mm2), 2 oz. copper clad.
—,’.)ower \megvuuons'
Rev. D 11/15
8
LNK574/576
www.power.com
Parameter Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
(Unless Otherwise Specified)
Min Typ Max Units
Control Functions (cont.)
DRAIN Supply Current
IS1
Feedback Voltage > VFB
(MOSFET not Switching) 150 200 260
mA
IS2
0.9 V ≤ VFB ≤ 1.70 V
(MOSFET Switching)
LNK574 200 260 310
LNK576 230 285 340
BYPASS Pin
Charge Current
ICH1 VBP = 0 V, TJ = 25 °C
LNK574 -5.5 -3.8 -1.8
mA
LNK576 -7.0 -5.3 -3.3
ICH2 VBP = 4 V, TJ = 25 °C
LNK574 -3.8 -2.5 -1.0
LNK576 -4.8 -3.5 -2.0
BYPASS Pin Voltage VBP 5.60 5.85 6.10 V
BYPASS Pin
Voltage Hysteresis VBP(H) 0.8 1.0 1.2 V
BYPASS Pin
Shunt Voltage BPSHUNT 6.1 6.5 6.9 V
Circuit Protection
Current Limit ILIMIT
di/dt = 40 mA/ms
TJ = 25 °CLNK574 126 136 146
mA
di/dt = 100 mA/ms
TJ = 25 °CLNK576 325 350 375
Power Coefficient I2f
di/dt = 40 mA/ms
TJ = 25 °CLNK574 1665 1850 2091
A2Hz
di/dt = 100 mA/ms
TJ = 25 °CLNK576 10562 12250 14062
Leading Edge
Blanking Time tLEB TJ = 25 °C220 265 ns
BYPASS Pin Shutdown
Threshold Current ISD
VBP = BPSHUNT
See Note E 5.0 6.5 8.0 mA
Thermal Shutdown
Temperature TSD See Note B 135 142 150 °C
Thermal Shutdown
Hysteresis TSD(H) See Note B 70 °C
power \Megrcmons‘
Rev. D 11/15
9
LNK574/576
www.power.com
NOTES:
A. IDSS is the worse case off-state leakage specification at 80% of BVDSS and maximum operating junction temperature.
B. This parameter is derived from characterization.
C. Output frequency specification applies to low-line input voltage in the final application. The controller is designed to reduce output
frequency by approximately 20% at high-line input voltages to balance low-line and high-line maximum output power.
D. The auto-restart on-time/off-time is increased by 20% at high-line input 265 VAC.
E. LinkZero-LP shuts down if current into BYPASS pin reaches ISD at BPSHUNT voltage.
Parameter Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
(Unless Otherwise Specified)
Min Typ Max Units
Power-Down (PD) Mode
Off-State Drain Leakage
in Power-Down Mode IDSS(PD)
TJ = 25 °C
VDRAIN = 325 V
See Figure 25
6.5 9mA
BYPASS Pin Overvoltage
Protection in Power-
Down Mode
VBP(PDP)
IBP = 300 mA
TJ ≤ 100 °C7. 25 8.5 10.9 V
BYPASS Pin Power-Up
Reset Threshold (in
Power-Down Mode or at
Power Supply Start-Up)
VBP(PU) 1.5 3 4 V
Output
ON-State
Resistance RDS(ON)
LNK574
ID = 13 mA
TJ = 25 °C48 55
W
TJ = 100 °C76 88
LNK576
ID = 33 mA
TJ = 25 °C19 22
TJ = 100 °C30 35
Breakdown
Voltage BVDSS VBP = 6.2 V, TJ = 25 °C700 V
DRAIN Supply
Voltage 50 V
Auto-Restart
ON-Time tAR VIN = 85 VAC
TJ = 25 °C
See Note C
145 ms
Auto-Restart
Duty Cycle 1.0 s
Output Enable Delay tEN See Figure 8 14 ms
HV DRAIN VOLTAGE Pwrzowrossum DRAIN Current (mA) —power \megrcmons'
Rev. D 11/15
10
LNK574/576
www.power.com
Figure 7. Duty Cycle Measurement. Figure 8. Output Enable Timing.
Figure 6. General Test Circuit.
Figure 9. Peak Negative Pulsed DRAIN Current Waveform.
PI-3707-112503
FB
tP
tEN
DCMAX
tP = 1
fOSC
VDRAIN
(internal signal)
0
100
Time (∝s)
DRAIN Current (mA)
PI-4021-101305
-100
2 ∝s
S
S
S
S
BP/M
FB
D
PI-6067-072110
470 Ω
5 W
S1
50 V
0-2 V
0.1 µF
om~=o> :E xu Esouxmwhm mo“ / C/ 25 ‘C / 200 ES. 2250 z_(mn_ 9V ¢m3_o> =E mmm RSJZEL
Rev. D 11/15
11
LNK574/576
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Typical Performance Characteristics
1.1
1.0
0.9
-50 -25 0255075 100 125 150
Junction Temperature (°C)
Breakdown Voltage
(Normalized to 25
°C)
PI-2213-012301
1.2
1.0
0.8
0.6
0.4
0.2
0
-50 -25 0 25 50 75 100 125
Junction Temperature (°C)
PI-6065-071910
Output Frequency
(Normalized to 25
°C)
1.4
1.0
1.2
0.8
0.6
0.4
0.2
0
-50 0 50 100 150
Temperature (°C)
PI-6066-071910
Current Limit
(Normalized to 25
°C)
1.1
1.0
0.9
-50 -25 0255075 100 125 150
Temperature (
°
C)
FEEDBACK Pin Voltage
(Normalized to 25
°C)
PI-4057-071905
6
5
4
3
2
1
0
0 0.2 0.4 0.6 0.8 1.0
100
150
175
200
125
0
0 4286101214161820
DRAIN Voltage (V)
DRAIN Current (mA)
PI-3927-083104
25
75
50
Figure 10. Breakdown vs. Temperature.
Figure 12. Current Limit vs. Temperature.
Figure 14. BYPASS Pin Start-up Waveform (CBP
= 0.22 mF).
Figure 11. Frequency vs. Temperature.
Figure 13. FEEDBACK Pin Voltage vs. Temperature.
Figure 15. Output Characteristics for LNK574.
1000 25 “c , Ed; 100 c// 3 / 5 E % / u ,E E :1 Drain Voltage (V) // I / / / / // —power \megrcmons'
Rev. D 11/15
12
LNK574/576
www.power.com
Drain Voltage (V)
Drain Capacitance (pF)
PI-3928-083104
0 100 200 300 400 500
600
1
10
100
1000
Typical Performance Characteristics (cont.)
Figure 17. CDSS vs. Drain Voltage for LNK574.Figure 16. Output Characteristics for LNK576.
Figure 20. FEEDBACK Pin Regulation Voltage Threshold vs.
Output Load in CV Mode.
Figure 19. Frequency Reduction vs. Duty Cycle (Line Voltage).Figure 18. CDSS vs. Drain Voltage for LNK576.
Figure 21. FEEDBACK Pin Input Characteristics.
110
100
90
80
70
60
0 10 20 30 40 50 60 70
Duty Cycle (%)
PI-6068-071910
Frequency (kHz)
1.8
1.7
1.6
1.5
1.4
1.3
0 10 20 30 40 50 60 70 80 90 100
Output Load (%)
PI-6069-071910
FEEDBACK Pin Voltage
50
40
30
20
0
10
-10
-20
-30
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
FEEDBACK Pin Voltage
PI-6070-071910
FEEDBACK Pin Current
260
390
455
520
325
0
042 86 10 12 14 16 18 20
DRAIN Voltage (V)
DRAIN Current (mA)
PI-7093-072913
65
195
130
Drain Voltage (V)
Drain Capacitance (pF)
PI-7094-080713
0 100 200 300 400 500 600
2.6
26
260
2600
figflfifiy -
Rev. D 11/15
13
LNK574/576
www.power.com
Typical Performance Characteristics (cont.)
Figure 22. FEEDBACK Pin Input Characteristics in CC Mode
(1.7 V to 0.9 V).
Figure 24. Power-Down Off-Time vs. BYPASS Pin Capacitor.
VBP
Start at 5.85 V (Temperature = 25 °C)
Figure 23. Frequency Cut Back in CC Mode Normalized to 1.
Figure 25. Typical Drain Current vs. Temperature in
Power-Down Mode.
0
-4
-2
-6
-8
-10
-12
-14
-16
-18
-20
0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
FEEDBACK Pin Voltage
PI-6071-071910
FEEDBACK Pin Current
0
-3
-2
-1
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
FEEDBACK Pin Voltage
PI-6072-071910
FEEDBACK Pin Current
Auto-Restart
1
0.8
0.9
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 200 400 600 800 1000 1200 1400
Power Down Off-Time (ms)
PI-6110-112310
BYPASS Pin Capacitor (
µF)
10
9
8
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125
Temperature (°C)
PI-6111-081810
Drain Current (µA)
Q Q E - "RSQ’XEES.
Rev. D 11/15
14
LNK574/576
www.power.com
PI-4526-040207
D07C
SO-8C
3.90 (0.154) BSC
Notes:
1. JEDEC reference: MS-012.
2. Package outline exclusive of mold flash and metal burr.
3. Package outline inclusive of plating thickness.
4. Datums A and B to be determined at datum plane H.
5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.
0.20 (0.008) C
2X
1 4
5
8
26.00 (0.236) BSC
D
4
A
4.90 (0.193) BSC
2
0.10 (0.004) C
2X
D
0.10 (0.004) C 2X
A-B
1.27 (0.050) BSC
7X 0.31 - 0.51 (0.012 - 0.020)
0.25 (0.010) M C A-B D
0.25 (0.010)
0.10 (0.004)
(0.049 - 0.065)
1.25 - 1.65
1.75 (0.069)
1.35 (0.053)
0.10 (0.004) C
7X
C
H
o
1.27 (0.050)
0.40 (0.016)
GAUGE
PLANE
0 - 8
1.04 (0.041) REF 0.25 (0.010)
BSC
SEATING
PLANE
0.25 (0.010)
0.17 (0.007)
DETAIL A
DETAIL A
C
SEATING PLANE
Pin 1 ID
B
4
+
+ +
4.90 (0.193)
1.27 (0.050) 0.60 (0.024)
2.00 (0.079)
Reference
Solder Pad
Dimensions
+
power \Megrcmons‘
Rev. D 11/15
15
LNK574/576
www.power.com
PI-6583-060915
A. Power Integrations Registered Trademark
B. Assembly Date Code (last two digits of year followed by 2-digit work week)
C. Product Identification (Part #/Package Type)
D. Lot Identification Code
SO-8C PACKAGE MARKING
1530
LNK574DG
3D683G
A
B
C
D
—,’.)ower \megvuuons'
Rev. D 11/15
16
LNK574/576
www.power.com
Part Ordering Information
• LinkZero Product Family
• LinkZero-LP Series Number
• Package Identifier
D Plastic SO-8C
• Package Material
G GREEN: Halogen Free and RoHS Compliant
• Tape & Reel and Other Options
Blank Standard Configurations
TL Tape & Reel, 2.5 k pcs minimum for D Package. Not available for P Package.
LNK 574 D G - TL
MSL Table
Part Number MSL Rating
LNK574DG 1
LNK576DG 1
ESD and Latch-Up
Test Conditions Results
Latch-up at 125 °C EIA/JESD78 > ±100 mA or > 1.5 V (max) on all pins
Human Body Model ESD EIA/JESD22-A114-A Passes ±2000 V on all pins
Machine Model ESD EIA/JESD22-A115-A Passes ±200 V on all pins
power \Megrcmons‘
Rev. D 11/15
17
LNK574/576
www.power.com
Notes
Revision Notes Date
AInternal release. 10/12/10
BUpdated text and parameter tables. 12/07/10
BCorrected Figure 2. 11/14/12
C Added LNK576 parts. 05/15/14
D Updated with new Brand Style. Added Package Marking, ESD and MSL tables. 11/15
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at http://www.power.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, LYTSwitch, InnoSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS,
HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are trademarks of Power
Integrations, Inc. Other trademarks are property of their respective companies. ©2015, Power Integrations, Inc.
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