Scheda tecnica TPS2492,93 di Texas Instruments

Commenti/errori della scheda tecnica

I TEXAS INSTRUMENTS

VDS - Drain-to-Source Voltage - V

0.1

1000

ID- Drain-to-Source Current - A

DRAIN-TO-SOURCE CURRENT

DRAIN-TO-SOURCE VOLTAGE

1 10 100 1000

100

Programmed SOA 10 ms

10 ms

1 ms

100 ms

Operation in the gray area is limited by RDS(on)

1 UVEN

VCC

RSENSE

0.01 W

RGATE

10 W

12 11

3 2 7 4

41.2 kW

8.25 kW

0.068 mF

470 kW

SENSE GATE OUT

FLT

IMON

TIMERGNDVREFPROGOV

TPS2492/93

VLOGIC

VOUT

VIN

PLIM = 34 W

ILIM = 5 A

Timeout = 10 ms

TPS2492

TPS2493

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SLUSA65C –JULY 2010–REVISED JANUARY 2013

Positive High-Voltage Power-Limiting Hotswap Controller

With Analog Current Monitor Output

Check for Samples: TPS2492 ,TPS2493

1FEATURES DESCRIPTION

• 9-V to 80-V Operation The TPS2492 and TPS2493 are easy-to-use, positive

• High-Side Drive for External N-FET high voltage, 14-pin Hotswap Controllers that safely

• Programmable FET Power Limit drive an external N-channel FET to control load

current. The programmable power foldback protection

• Programmable Load Current Limit ensures that the external FET operates inside its safe

• Programmable Fault Timer operating area (SOA) during overload conditions by

• Load Current Monitor Output controlling of power dissipation. The programmable

current limit and fault timer ensure the supply,

• Power Good and Fault Outputs external FET, and load are not harmed by

• Enable/UV, OV Inputs overcurrent. Features include inrush current limiting,

• Latch or Auto Restart After Fault controlled load turn-on, interfacing to down-stream

• EVM Available SLUU425 DC-to-DC converters, and power feed protection.

• Calculation Tool Available SLVC033 The analog current monitor output provides a signal

ready for sampling with an external A/D converter.

APPLICATIONS Additional features include programmable overvoltage

• Server Backplanes and undervoltage shutdown, power-good for

coordinating loads with inrush, and a fault indicator to

• Storage Area Networks (SAN) indicate an over-current shutdown.

• Medical Systems

• Plug-in Modules

• Base Stations

Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

l TEXAS INSTRUMENTS

TPS2492

TPS2493

SLUSA65C –JULY 2010–REVISED JANUARY 2013

www.ti.com

PRODUCT INFORMATION(1)

TEMPERATURE FUNCTION PACKAGE PART NUMBER

Latched TPS2492PW

-40°C to 125°C PW14

Retry TPS2493PW

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder on www.ti.com.

ABSOLUTE MAXIMUM RATINGS(1)

over recommended TJand voltages with respect to GND (unless otherwise noted)

VALUE UNIT

VCC, SENSE, UVEN, OUT -0.3 to 100

Input voltage range

PROG, OV -0.3 to 6

VCC – SENSE Differential voltage -1.5 to 1.5 V

GATE, PG, FLT -0.3 to 100

Output voltage range

TIMER, VREF, IMON -0.3 to 6

PG, FLT 10

Sink current

PROG 2 mA

VREF Source current 2

HBM 2

ESD rating kV

CDM 0.5

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THERMAL INFORMATION

THERMAL METRIC(1) VALUE UNITS

θJA Junction-to-ambient thermal resistance(2) 116.4

θJB Junction-to-board thermal resistance(3) 53.8 °C/W

ψJT Junction-to-top characterization parameter(4) 1.4

ψJB Junction-to-board characterization parameter(5) 58.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).

RECOMMENDED OPERATING CONDITIONS

over recommended TJand voltages with respect to GND (unless otherwise noted)

MIN NOM MAX UNIT

VCC 9 80

Input voltage range V

PROG 0.4 4

Sourcing current 0 1 mA

VREF capacitive loading 0 1000 pF

IMON Sourcing current 1.9 mA

TJJunction operating temperature -40 125 °C

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l TEXAS INSTRUMENTS

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SLUSA65C –JULY 2010–REVISED JANUARY 2013

ELECTRICAL CHARACTERISTICS

9 V ≤VVCC ≤80 V, -40°C ≤TJ≤125°C, VTIMER = 0 V and all outputs unloaded. Typical specification are at TJ= 25°C, VVCC =

48 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Supply Current (VCC)

IVCC Enabled VUVEN = Hi, VSENSE = VOUT = VVCC 665 1000 µA

IVCC Disabled VUVEN = Lo, VSENSE = VVCC, VOUT = 0 120 250

Input Supply UVLO (VCC)

VVCC turn on Rising 8.4 8.8 V

Hysteresis 50 100 150 mV

Current Sense Input (SENSE)

ISENSE Input bias current VSENSE = VOUT = VVCC 7.5 20 µA

Reference Voltage Output (VREF)

VREF Reference voltage 0 ≤IVREF ≤1 mA 3.9 4 4.1 V

Power Limiting Input (PROG)

Input bias current; device

IPROG 0.4 ≤VPROG ≤4 V VUVEN = 48 V 5 µA

enabled; sourcing or sinking

Pull down resistance; device

RPROG IPROG = 200 µA; VUVEN = 0 V 375 600 Ω

disabled

Power Limiting and Current Limiting (SENSE)

VPROG = 2.4 V; VOUT = 0 V; VVCC = 48 V 17 25 33

Current limit threshold V(VCC-

SENSE) with power limiting trip VPROG = 0.9 V; VOUT = 30 V; VVCC = 48 V 17 25 33 mV

Current limit threshold V(VCC- VPROG = 4 V; VSENSE = VOUT 45 50 55

SENSE) without power limiting trip

VPROG = 4 V; VOUT = VSENSE; V(VCC-SENSE): 0

Large overload response time to

tF_TRIP rising to 200 mV; C(GATE-OUT) = 2 nF; V(GATE- 1.2 µs

GATE low OUT) = 1 V

TIMER Operation (TIMER)

VTIMER = 0 V 17 27 36

ISOURCE TIMER source current VTIMER = 0 V; TJ= 25°C 22 27 32 µA

VTIMER = 5 V 1.5 2.7 3.7

ISINK TIMER sink current VTIMER = 5 V; TJ= 25°C 2.1 2.7 3.1

TIMER upper threshold 3.9 4 0 4.1

VTIMER V

TIMER lower reset threshold TPS2492 only 0.96 1.00 1.04

DRETRY Fault retry duty cycle TPS2493 only 0.5 0.75 1 %

Fault Indicator Output (FLT)

IFLT = 2 mA 0.1 0.25

Low voltage (sinking) V

IFLT = 4 mA 0.25 0.5

ILEAKAGE Leakage current FLT high impedance 10 µA

Under-Voltage and Enable Input (UVEN)

VUVEN_H UVEN rising 1.31 1.35 1.39 V

Threshold voltage Hysteresis 80 100 120 mV

Leakage current VUVEN = 48 V 1 µA

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l TEXAS INSTRUMENTS

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SLUSA65C –JULY 2010–REVISED JANUARY 2013

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ELECTRICAL CHARACTERISTICS (continued)

9 V ≤VVCC ≤80 V, -40°C ≤TJ≤125°C, VTIMER = 0 V and all outputs unloaded. Typical specification are at TJ= 25°C, VVCC =

48 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Gate Drive Output (GATE)

GATE sourcing current VSENSE = VVCC; V(GATE-OUT) = 7 V; VUVEN = Hi 15 22 35 µA

VUVEN = Lo; VGATE = VVCC 1.8 2.4 2.8

IGATE GATE sinking current mA

VUVEN = Hi; VGATE = VVCC; VVCC- VSENSE =75 125 250

200 mV

VUVEN = Hi, VCC = SENSE = OUT, measure

VGATE GATE output 12 16 V

VGATE -VOUT

Propagation delay: UVEN going VUVEN = 0 →2.5 V, 50% of VUVEN to 50% of

tD_ON 25 40

high to GATE output high VGATE, VOUT = VVCC, R(GATE-OUT) = 1 MΩ

VUVEN = 2.5 V →0 V, 50% of VUVEN to 50%

Propagation delay: UVEN going

tD_OFF of VGATE, VOUT = VVCC, R(GATE-OUT) = 1 MΩ, 0.5 1

low to GATE output low µs

tFALL < 0.1 µs

VTIMER: 0 →5 V, tRISE < 0.1 µs. 50% of

Propagation delay: TIMER expires

tD_FAULT VTIMER to 50% of VGATE, VOUT = VCC , 0.8 1

to GATE output low R(GATE-OUT) = 1 MΩ,

Power Good Output (PG)

IPG = 2 mA 0.1 0.25

Low voltage (sinking) IPG = 4 mA 0.25 0.5

PG threshold voltage; VOUT rising; VSENSE = VVCC; measure V(VCC-OUT) 0.8 1.25 1.7

PG goes low V

PG threshold voltage; VOUT VSENSE = VVCC; measure V(VCC-OUT) 2.2 2.7 3.2

falling; PG goes open drain

PG threshold hysteresis voltage; VSENSE = VVCC 1.4

V(SENSE-OUT)

PG deglitch delay; detection to

tDPG VSENSE = VVCC 5 9 15 ms

output; rising and falling edges

ILEAKAGE Leakage current; PG false open drain 10 µA

Overvoltage Input (OV)

VOV_H OV rising 1.31 1.35 1.39 V

Threshold voltage Hysteresis 70 90 110 mV

ILEAKAGE Leakage current (sinking) VOV = 5 V 1 µA

tOFF Turn off time VOV = 0 →2.5 V to VGS < 1 V, CGATE = 2 nF 2

µs

Maximum duration of OV strong Gate pull down 40 100 220

pull down

Output Voltage Feedback (OUT)

VOUT = VVCC, VUVEN = Hi; sinking 8 20

IOUT Bias current µA

VOUT = GND; VUVEN = Lo; sourcing 18 40

Load Current Monitor (IMON) Output

Maximum output voltage VCC – VSENSE = 200 mV 2.6 2.8 3 V

ISOURCE Source current 1.9 mA

ISINK Sink current 60 µA

Gain (VIMON/V(VCC-SENSE)) 46 48 50 V/V

VOFFSET Offset voltage -50 -5 30 mV

Error relative to curve fit, 5 mV < (VCC –

Linearity(1) 0.3%

VSENSE )

Output Ripple(1) 8 mVPP

(1) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's

product warranty.

Product Folder Links: TPS2492 TPS2493

ENABLE

4 V REF 2

POR

ENABLE

Fault

Logic 4 V

1 V

9-ms Deglitch

2.7 V

1.25 V

Constant

Power

Engine

25 mA

2.5 mA

14 V

22 mA

2 mA

8.4 V

8.3 V

1.35 V

1.25 V

1.35 V

1.26 V

TIMER

FLT

IMON

OUT

GATE

VREF

VCC

PROG

SENSE

GND

UVEN

50 mV

Charge

Pump

UVLO

AV= 48

TPS2492

TPS2493

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SLUSA65C –JULY 2010–REVISED JANUARY 2013

DEVICE INFORMATION

Functional Block Diagram

Product Folder Links: TPS2492 TPS2493

‘5‘ TEXAS INSTRUMENTS i _ 33:33:: O _|__|_E_|_E_|__|_

UVEN 1

VREF

PROG

TIMER

IMON

GND

VCC

SENSE

GATE

OUT

FLT

PW PACKAGE

(top view)

TPS2492

TPS2493

SLUSA65C –JULY 2010–REVISED JANUARY 2013

www.ti.com

TERMINAL FUNCTIONS

TERMINAL I/O DESCRIPTION

NAME NO.

UVEN 1 I A low input inhibits GATE. A logic input can drive this pin as an enable.

VREF 2 O 4-V reference voltage used to set the power threshold on PROG pin.

PROG 3 I FET power-limit programming pin

TIMER 4 I/O A capacitor from TIMER to ground sets the fault timer period.

OV 5 I Overvoltage sensing input. A high input inhibits GATE.

IMON 6 O Current monitor output, nominally VIMON = 48 x (VVCC-SENSE).

GND 7 PWR Ground

PG 8 O Active low power good output. This is driven by VVCC-SENSE.

Active low fault indicator output. FLT indicates the fault timer has expired. FLT is

FLT 9 O reset by UVEN, UVLO, or automatic restart.

NC 10 No connect

FET source voltage (output) sensing pin. Gate is clamped to a diode drop below

OUT 11 I OUT.

GATE 12 O Gate driver output for external FET.

Current sensed as VVCC-SENSE and the FET VDS as VSENSE-OUT. For low FET VDS,

SENSE 13 I current limits at 50mV.

VCC 14 I Input supply and current sense positive input

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l TEXAS INSTRUMENTS

LIM

SENSE

50mV

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TPS2493

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SLUSA65C –JULY 2010–REVISED JANUARY 2013

DETAILED PIN DESCRIPTION

The following description relies on the Typical Application Diagram shown on page 1, and the Functional Block

Diagram.

VCC: This pin is associated with three functions:

1. Biasing power to the integrated circuit,

2. Input to power on reset (POR) and under-voltage lockout (UVLO) functions, and

3. Voltage sense at one terminal of RSENSE for M1 current measurement.

The voltage must exceed the POR (about 6 V for roughly 400 µs) and the internal UVLO (about 8 V) before

normal operation (driving the GATE) may begin. Connections to VCC should be designed to minimize RSENSE

voltage sensing errors and to maximize the effect of C1 and D1; place C1 at RSENSE rather than at the device pin

to eliminate transient sensing errors. GATE, PROG, and TIMER are held low when either UVLO or POR are

active. PG and FLT are open drain when either UVLO or POR are active.

SENSE: Monitors the voltage at the drain of M1, and the downstream side of RSENSE providing the constant

power limit engine with feedback of both M1 current (ID) and voltage (VDS). Voltage is determined by the

difference between SENSE and OUT, while the current analog is the voltage difference between VCC and

SENSE. The constant power engine uses VDS to compute the allowed IDand is clamped to 50 mV, acting like a

traditional current limit at low VDS. The current limit is set by the following equation:

(1)

Design the connections to SENSE to minimize RSENSE voltage sensing errors. Don't drive SENSE to a large

voltage difference from VCC because it is internally clamped to VCC. The current limit function can be disabled

by connecting SENSE to VCC.

GATE: Provides the high side (above VCC) gate drive for external N-channel FET. It is controlled by the internal

gate drive amplifier, which provides a pull-up of 22 µA from an internal charge pump and both strong (125 mA)

and weak (2 mA) pull-downs to ground. The strong pull down is triggered by an overvoltage on the OV pin or

large overcurrent to the load. The strong pull-down current is a non-linear function of the gate amplifier overdrive;

it provides small drive for small overloads, but large overdrive for fast reaction to an output short. There is a

separate pull-down of 2 mA to shut the MOSFET off when UVEN or UVLO cause this to happen. If an output

short causes the VCC to fall below the UVLO, the turnoff speed will be limited by the 2mA turnoff current. An

internal clamp protects the gate of the FET (to OUT).

OUT: This input pin is used by the constant power engine and the PG comparator to measure VDS of M1 as

V(SENSE-OUT). Internal protection circuits leak a small current from this pin when it is low. If the load circuit can

drive OUT below ground, connect a clamp (or freewheel) diode from OUT (cathode) to GND (anode). The diode

should clamp the output above -1 V during the transient.

UVEN: The positive threshold of UVEN must be exceeded before the GATE driver is enabled. If the UVEN pin

drops below the UVEN negative threshold while the GATE driver is enabled, the GATE driver will be pulled to

GND by the 2-mA pull down. UVEN can be used as a logic control input, an analog input voltage monitor as

illustrated by R1, R2 and R3 in the Typical Application Circuit, or it can be tied to VCC to always enable the

TPS2492/3. The hysteresis associated with the internal comparator makes this a stable method of detecting a

low input condition and shutting the downstream circuits off. A TPS2492 that has latched off can be reset by

cycling UVEN below its negative threshold and back high.

Product Folder Links: TPS2492 TPS2493

l TEXAS INSTRUMENTS

J(MAX) S(MAX)

LIM

JC(MAX)

T T

PRQ

LIM

PROG

LIM

10 I

TPS2492

TPS2493

SLUSA65C –JULY 2010–REVISED JANUARY 2013

www.ti.com

VREF: Provides a 4.0-V reference voltage for use in conjunction with R4/R5 of the Typical Application Circuit to

set the voltage on the PROG pin. The reference voltage is available once the internal POR and UVLO thresholds

have been met. It is not designed as a supply voltage for other circuitry, therefore ensure that no more than 1 mA

is drawn. Bypass capacitance is not required, but if a special application requires one, less than 1000 pF can be

placed on this pin. This limit maintains VREG regulator stability.

PROG: The voltage applied to this pin (0.4 V minimum) programs the power limit used by the constant power

engine. Normally, a resistor divider R4/R5 is connected from VREF to PROG to set the power limit according to

the following equation:

(2)

where PLIM is the desired power limit of M1 and ILIM is the current limit set point (see SENSE). PLIM is determined

by the desired thermal stress on M1:

(3)

where TJ(MAX) is the maximum desired transient junction temperature of M1 and TS(MAX) is the maximum case

temperature prior to a start or restart. VPROG is used in conjunction with VDS to compute the (scaled) current,

ID_ALLOWED, by the constant power engine. ID_ALLOWED is compared by the gate amplifier to the actual ID, and used

to generate a gate drive. If ID< ID_ALLOWED, the amplifier turns the gate of M1 full on because there is no overload

condition; otherwise GATE is regulated to maintain the ID= ID_ALLOWED relationship.

A capacitor may be tied from PROG to ground to alter the natural constant power inrush current shape. If

properly designed, the effect is to cause the leading step of current in Figure 13 to look like a ramp. It is not

recommended that this mechanism be used to achieve a long and low ramp inrush current because the power

limiting accuracy is lower at VPROG < 0.4 V. PROG is internally pulled to ground whenever UVEN, POR, or UVLO

are not satisfied or the TPS2492 is latched off. This feature serves to discharge any capacitance connected to

the pin. Do not apply voltages greater than 4 V to PROG. If the constant power limit is not used, PROG should

be tied to VREF through a 47-kΩresistor.

TIMER: An integrating capacitor, CT, connected to the TIMER pin sets the fault-time for both versions and the

restart interval for the TPS2493. The timer charges at 27 µA whenever the TPS2492/3 is in power limit or current

limit and discharges at 2.7 µA otherwise. The charge-to-discharge current ratio is constant with temperature even

though there is a positive temperature coefficient to both. If VTIMER reaches 4 V, the TPS2492/3 pulls GATE to

ground (with the strong pull down), and discharges CT. The TPS2492 latches off when the fault timer expires.

The TPS2493 holds GATE at ground when the timer expires before it attempts to restart (re-enable GATE) after

a timing sequence consisting of discharging TIMER down to 1 V followed by 15 more charge and discharge

cycles. Design for the TPS2393 TIMER period must assume a 3-V rise in VTIMER rather than a 4-V rise to

accommodate a restart.

The TPS2492 can be reset by either cycling the UVEN pin or the UVLO (e.g. power cycling). TIMER discharges

when UVEN is low or the internal UVLO or POR are active. The TIMER pin should be tied to ground if this

feature is not used.

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l TEXAS INSTRUMENTS

( )

IMON VCC SENSE

VCC SENSE

V Gain V Offset

Linearity(%) 100

Gain V Offset

é ù

- ´ +

ë û

= ´

é ù

´ +

ë û

TPS2492

TPS2493

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SLUSA65C –JULY 2010–REVISED JANUARY 2013

PG: The power good output is an active low, open-drain output intended to interface to downstream DC-to-DC

converters or monitoring circuits. PG goes low after VDS of M1 has fallen to about 1.25 V and a 9-ms deglitch

time period has elapsed. PG is open drain whenever UVEN is low, VDS of M1 is above 2.7 V, or UVLO is active.

PG can also be viewed as having an output voltage monitor function. The 9-ms deglitch circuit operates to filter

short events that could cause PG to go inactive (open drain) such as a momentary overload or input voltage

step. VPG can be greater than VVCC because it’s ESD protection is only with respect to ground. PG may be left

open or tied to GND if not used.

GND: This pin is connected to system ground.

IMON: This current monitor output has a voltage equal to 48 times the voltage across RSENSE (VVCC-SENSE). IMON

is clamped at 2.7 V to prevent damage to downstream A/D circuits. IMON is a voltage output and does not

require a pull up or pull down. IMON will have a small amount of superimposed ripple at 2.5 kHz that is an

artifact of the monitoring circuit. The error due to the ripple does not significantly effect accuracy for signals on

the order of 1 V, but better accuracy may be achieved for small signals with an external R-C filter. The IMON pull

up source is stronger than the pull down. A resistor pull down can be used to improve transient response in

designs with large filter capacitors. Leave IMON open if not used.

A curve of Linearity (%) versus VVCC-SENSE is provided in the Typical Characteristics, providing an indication of

error versus signal level. This curve is constructed by first performing a first order curve fit to VIMON versus VVCC-

SENSE, yielding Gain and Offset terms for the linear fit. The Linearity (%) plot is calculated as:

(4)

FLT: This active low, open drain output asserts (goes low) when the fault timer expires after a prolonged over

current or an OV is detected. FLT is open drain whenever UVEN, POR, or UVLO are not satisfied. FLT is latched

in the TPS2492, clearing when the latch is reset. FLT clears automatically in the TPS2493 when a power-up retry

occurs. VFLT can be greater than VVCC because it's ESD protection is only with respect to ground. FLT may be

left open or tied to GND when not used.

OV: The over-voltage monitoring pin is programed with a resistor divider such as R1 - R3 in the Typical

Application Circuit. This function forces GATE and FLT low while the OV condition exists. While VOV exceeds its

threshold, the strong GATE pull down (125 mA) is applied for up to 100 µs, followed by the 2 mA pull down. The

GATE pull down and FLT are released as soon as the OV condition is cleared. Tie OV to GND if not used.

Product Folder Links: TPS2492 TPS2493

l TEXAS INSTRUMENTS T,.:Izs° c n = 25%: /§/ / \\ \\ Vcc

9 19 29 39 49 59 69 79

TJ = −405C

TJ = 255C

TJ = 1255C

VCC − Supply Voltage − V

− Gate Pullup Current −

Gate mA

2.1

2.2

2.3

2.4

2.5

2.6

9 19 29 39 49 59 69 79

TJ = −405C

TJ = 255C

TJ = 1255C

− Gate Pullup Current (EN = OV) − mA

IGate

VCC − Supply Voltage − V

VCC - Supply Voltage - V

200

400

900

ICC - Supply Current - mA

9 79

800

593919

300

600

100

700

500

694929

TJ= 125°C

TJ= 25°C TJ= -40°C

9 19 29 39 49 59 69 79

TJ = −405C

TJ = 255C

TJ = 1255C

VCC − Supply Voltage − V

− Current Limit Trip − mV

V(VCC − Sense)

TPS2492

TPS2493

SLUSA65C –JULY 2010–REVISED JANUARY 2013

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TYPICAL CHARACTERISTICS

SUPPLY CURRENT CURRENT LIMIT TRIP

vs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE

Figure 1. Figure 2.

GATE PULL UP CURRENT GATE PULL DOWN CURRENT(UVEN = 0 V)

vs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE

Figure 3. Figure 4.

Product Folder Links: TPS2492 TPS2493

l TEXAS INSTRUMENTS \ \\ /\ \ \ \ \'\‘ \ \{ /\\\ cc Vcc

VCC - Supply Voltage - V

13.2

13.6

13.9

VGATE - Output Voltage - V

9 7919

13.4

13.8

39 59

13.3

13.5

13.7

694929

TJ= 125°C

TJ= 25°C

TJ= -40°C

9 19 29 39 49 59 69 79

− Timer Pullup Current −

TJ = −405C

TJ = 255C

TJ = 1255C

ITimer Aµ

VCC − Supply Voltage − V

115

135

155

175

195

215

9 19 29 39 49 59 69 79

TJ = −405C

TJ = 255C

TJ = 1255C

− Gate Pulldown Current − mA

IGate

VCC − Supply Voltage − V

200

400

600

800

1000

1200

9 14 19 24 29 34 39 44 49

T − Current Limit Response Time − nS

TJ = −405C

TJ = 255C

TJ = 1255C

VCC − Supply Voltage − V

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SLUSA65C –JULY 2010–REVISED JANUARY 2013

TYPICAL CHARACTERISTICS (continued)

GATE PULL DOWN CURRENT CURRENT LIMIT RESPONSE TIME

vs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE

(UVEN = 4 V, V(VCC – SENSE) = 200 mV) (UVEN = 4 V, V(VCC – SENSE) = 200 mV)

Figure 5. Figure 6.

GATE OUTPUT VOLTAGE TIMER PULL UP CURRENT

vs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE

Figure 7. Figure 8.

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l TEXAS INSTRUMENTS 'TImer — Charge/Discharge Ralio 5.3a 5.75 5.7a 5.65 TJ =125“C 5.6a Vcc 125m / cc cc ccrstMSE

VCC - Supply Voltage - V

1.345

1.349

1.351

9 7919

1.347

1.350

39 59

1.346

1.348

694929

TJ= 125°C

TJ= 25°C

TJ= -40°C

VUVEN - UVEN Threshold Voltage (Rising) - V

VCC-VSENSE - Supply Voltage - mV

-0.2

0.3

0.8

Linearity - %

0 30 40

0.7

6010

0.1

0.5

-0.1

0.6

0.4

5020

0.2

TJ= 125°C

TJ= 25°C

TJ= -40°C

VCC - Supply Voltage - V

1.245

1.251

1.255

VUVEN - UVEN Threshold Voltage (Falling) - V

9 7919

1.248

1.254

39 59

1.246

1.249

1.252

694929

TJ= 125°C

TJ= 25°C

TJ= -40°C

1.253

1.250

1.247

9.60

9.65

9.70

9.75

9.80

9 19 29 39 49 59 69 79

TJ = −405C

TJ = 1255C

TJ = 255C

− Charge/Discharge Ratio

ITimer

VCC − Supply Voltage − V

TPS2492

TPS2493

SLUSA65C –JULY 2010–REVISED JANUARY 2013

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TYPICAL CHARACTERISTICS (continued)

TIMER CHARGE/DISCHARGE RATIO UVEN AND OV THRESHOLD VOLTAGE (falling)

vs vs

SUPPLY VOLTAGE AND TEMPERATURE SUPPLY VOLTAGE

Figure 9. Figure 10.

UVEN AND OV THRESHOLD VOLTAGE (rising) LINEARITY

vs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE

Figure 11. Figure 12.

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APPLICATION INFORMATION

Basic Operation

The TPS2492/93 features include:

1. Adjustable under-voltage and over-voltage lockout;

2. Turn-on inrush limit;

3. High-side gate drive for an external N-channel FET;

4. FET protection (power limit and current limit);

5. Adjustable overload timeout;

6. Output current monitor;

7. Status output;

8. Charge-complete indicator for downstream converter sequencing; and

9. Optional automatic restart mode.

The TPS2492/93 features power-limiting FET protection that allows independent control of current limit (to set

maximum full-load current), power limit (to keep FET in its safe operating area), and overload time (to control

temperature rise). The power limiting feature controls the V and I across the FET to protect it, and does not

control load power. This protection is a specialized form of foldback output limiting. Given a constant power

dissipation, computation of peak junction temperature is straight forward. The TPS2393 provides a small

operating duty cycle into a short, reducing the average temperature rise of the FET to levels similar to normal

operation in many systems. This prevents overheating and failure with prolonged exposure to an output short.

The typical application circuit, and oscilloscope plots of Figure 13 and Figure 17 demonstrate many of the

functions described above.

Board Plug-In (Figure 13)

Only the bypass capacitor charge current and small bias currents are evident when a board is first plugged in as

seen in Figure 13. The TPS2492/93 is held inactive with GATE, PROG, and TIMER held low, and with PG and

FLT open drain, for less than 1 ms while internal voltages stabilize. Then GATE, PROG, TIMER, FLT and PG are

released and the part begins sourcing current to the GATE pin because UVEN is high and OV is low. The

external FET begins to turn on while the voltage across it, V(SENSE-OUT), and current through it, V(VCC-

SENSE)/RSENSE, are monitored. Current initially rises to the value which satisfies the power limit engine (PLIM/ VVCC)

since the output capacitor was discharged. The shape of the input current waveform shows the operation of the

FET power limit. In this case, the 5-A current limit is never reached as the output reaches full charge. This is

likely due to the limited gate slew rate.

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TIMER and PG Operation (Figure 13)

The TIMER pin charges CTas long as limiting action continues, and discharges at a 1/10 charge rate when

limiting stops. If the voltage on CTreaches 4 V before the output is charged, the external FET is turned off and

either a latch-off or restart cycle commences, depending on the part type. The open-drain PG output provides a

deglitched end-of-charge indication which is based on the voltage across the external FET. PG is useful for

preventing a downstream DC-to-DC converter from starting while COis still charging. PG goes active (low) about

9 ms after COis charged. This delay allows the external FET to fully turn on and any transients in the power

circuits to end before the converter starts up. The resistor pull-up shown on pin PG in the Typical Application

Circuit only demonstrates operation; the actual connection to the converter depends on the application. Timing

can appear to terminate early in some designs if operation transitions out of the power limit mode into a gate

charge-rate limited mode at low VDS values. This effect sometimes occurs because gate capacitances, CGD and

CGS, are nonlinear with applied voltage, getting larger at smaller voltage. This can be seen in Figure 13.

Figure 13. Basic Board Insertion

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l TEXAS INSTRUMENTS -m “Hum-wu- m-m mu 5-]...- n—umum. m... -mm. m 5...... n. m... ‘ -a"- m u... ... m... ..m mu- m mum. mm

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Action of the Constant Power Engine (Figure 14)

The calculated power dissipated in the external FET, VDS x ID, is computed under the same startup conditions as

Figure 13. The current of the external FET, labeled IIN, initially rises to the value that satisfies the constant power

engine; in this case it is 25 W / 48 V = 0.52 A. The 25-W value is programmed into the engine by setting the

PROG voltage using R4 and R5. VDS of the external FET, which is calculated as V(SENSE-OUT), falls as CO

charges, thus allowing the external FET drain current to increase. This is the result of the internal constant power

engine adjusting the current limit reference to the GATE amplifier as COcharges and VDS falls. The calculated

device power in Figure 14, labeled POWER, is seen to be reasonably constant within the limitations of circuit

tolerance and acquisition noise. A fixed current limit is implemented by clamping the constant power engine

output to 50 mV when VDS is low. This protection technique can be viewed as a specialized form of foldback

limiting; the benefit over linear foldback is that it yields the maximum output current from a device over the full

range of VDS while still protecting the device.

Figure 14. Computation of the External FET Stress During Startup

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Response to a Hard Output Short (Figure 15,Figure 16, and Figure 17)

Figure 15 shows the short circuit response over the full time-out period. An output short is applied, causing the

voltage to fall, limiter action begin, and the fault timer to start. The external FET current is actively controlled by

the power limiting engine and gate amplifier circuit while the TIMER pin charges CTto the 4-V threshold. Once

this threshold is reached, the TPS2492/93 turns off the external FET. The TPS2492 latches off until either the

input voltage drops below the UVLO threshold or UVEN cycles through the false (low) state. The TPS2493 will

attempt a restart after going through a timing cycle. Figure 16 demonstrates the operation of FLT during a short

circuit. FLT remains false (open drain) until the TIMER has expired.

Figure 15. Current Limit Overview

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Figure 16. FLT Operation

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The TPS2492/93 responds rapidly to a short circuit as seen in Figure 17. The falling OUT voltage is the result of

the external FET and COcurrents through the short circuit impedance. The internal GATE clamp causes the

GATE voltage to follow the output voltage down and subsequently limits the negative VGS. The IIN waveform

includes current into an input 47 µF capacitor. M1 drain current has a peak value in excess of the waveform, and

terminates when VGATE approaches VOUT. The rapidly rising fault current overdrives the GATE amplifier causing it

to overshoot and rapidly turn the external FET off by sinking current to ground. At a time beyond the extent of

Figure 17, but within the scope of Figure 15, the FET will be slowly turned back on as the GATE amplifier

recovers. The operating point will settle to the current or power limit, and finally the TIMER will expire and the

FET will turn off.

Limited input voltage overshoot appears in Figure 17 because a local 47-μF bypass capacitor and 1000 μF

distribution capacitor were used. The input voltage overshoots as the input current abruptly drops due to the

stored energy in the input wiring inductance. The exact waveforms seen in an application depend upon many

factors including parasitics of the voltage distribution, circuit layout, and the short itself.

Figure 17. Current Limit Onset

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Automatic Restart (Figure 18)

The TPS2493 automatically initiates a restart after a fault has caused it to turn off the external FET. Internal

control circuits use CTto count 16 cycles before re-enabling the external FET. This sequence repeats if the fault

persists. TIMER has a 1:10 charge-to-discharge current ratio, and uses a 1-V lower threshold. The fault-retry

duty cycle specification in the Electrical Characteristics Table quantifies this behavior. This small duty cycle often

reduces the average short-circuit power dissipation to levels associated with normal operation and reduces the

need for additional measures such as oversized heatsinking. Figure 18 demonstrates that the initial timing cycle

starts with VTIMER at zero V, subsequent cycles start with VTIMER at 1 V, and a succesful restart occurs after a 16

cycle delay.

Figure 18. TPS2492/93 Restart Cycle Timing

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UVEN

VREF

PROG

TIMER

IMON

GND

VCC

SENSE

GATE

OUT

FLT

TPS2492

VIN

RSENSE

RG D2

VOUT

IMON

RCG

Optional

Startup

Method

Optional IMON Filter

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Application Design Example

The following example illustrates the design and component selection process for a TPS2492/93 application.

Figure 19 shows the application circuit for this design example. The requirements of this design are:

• Nominal System Voltage: 12 V

• Maximum Operating System Voltage: 13.5 V

• Overvoltage Threshold: 14.5 V

• Undervoltage Threshold: 9.5 V

• Steady-state Load Current: 40 A

• Load Capacitance: 1000 µF

• Maximum Ambient Temperature: 50°C

• Maximum Static Junction Temperature 125°C

• Maximum Transient Junction Temperature: 150°C

Figure 19. TPS2492/93 Design Example Schematic

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l TEXAS INSTRUMENTS SENSE

J(MAX) A(MAX)

DSON(MAX) J

JA LIMIT(NOM)

T T 125°C 50°C

R 3mΩ at T = 125°C

R I 10 (50A)

= = =

´´

2 2

LIMIT(MAX)

I 55 1 3 025= ´ = ´ W =

RSENSE SENSE

P R A m . W

LIMIT(MAX)

SENSE

I 55

R 1mΩ

= = =

SENSE( MAX )

VmV A

SENSE

LIMIT

V50mV

R 1.042mΩ

1.2 I 1.2 40A

= = =

´ ´

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TPS2493

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SLUSA65C –JULY 2010–REVISED JANUARY 2013

1. Choose RSENSE

Calculate RSENSE using a multiplier factor of 1.2 (20%) for VSENSE and RSENSE tolerance along with some

additional margin.

(5)

Choose RSENSE =1mΩ, resulting in a nominal 50 A current limit.

(6)

(7)

Multiple sense resistors in parallel should be considered.

2. Choose M1

Select the M1 VDS rating allowing for maximum input voltage and transients. Then select an operating RDSON,

package, and cooling to control the operating temperature. Most manufacturers list RDSON(MAX) at 25°C and

provide a typical characteristics curve from which values at other temperatures can be derived. The next

equation can be used to estimate desired RDSON(MAX) at the maximum operating junction temperature of TJ(MAX).

(usually 125°C). TA(MAX) is the maximum expected ambient temperature. Assume that a thermal resistance, RθJA

of 10 °C/W can be achieved by reinforcing the typical 40°C/W for a 12inch copper pad with copper on multiple

layers and some airflow.

(8)

Assume that we are able to find a suitable FET with an RDSON of 0.74 mΩat 25°C and 1.18 mΩat 125°C. These

devices are in a package such as a D2PAK with a large copper base and very low RθJC.

The junction-to-ambient thermal resistance, RθJA, depends upon the package style chosen and the details of

heat-sinking and cooling including the PCB layout. Actual “in-system” temperature measurements will be required

to validate thermal performance.

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l TEXAS INSTRUMENTS FROG no

VOUT - Output Voltage - V

IOUT - Output Current - A

OUTPUT CURRENT

OUTPUT VOLTAGE (V VCC = 12 V)

12 8 4 0

2610

REF

4 5

PROG

R R ( 1) 140.6kΩ

= ´ - =

LIM

PROG

LIM

P249

V 0.498V

10 I 10 50

= = =

´ ´

( )

J(MAX2) CA LIMIT(NOM) DSON A(MAX)

LIM

0.7 T R I R T

P 249

é ù

´ - ´ ´ -

ë û

= =

TPS2492

TPS2493

SLUSA65C –JULY 2010–REVISED JANUARY 2013

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3. Choose the Power Limit PLIM and the PROG Resistors, R4and R5

M1 dissipates large amounts of power during power-up or output short circuit. Power limit, PLIM should be set to

prevent the M1 die temperature from exceeding a short term maximum temperature, TJ(MAX2). Short term TJ(MAX2)

may be set as high as 150°C (specified on FET datasheet) while still leaving ample margin for the typical

manufacturer's rating of 175°C. The R4 and R5 resistors set VPROG, programming the FET power dissipation.

Assume that RθJA is 10 °C/W, RθJC is 0.2 °C/W, and RθCA is 9.8 °C/W for the device we chose above. PLIM can

be estimated as follows:

(9)

Where RθCA is the M1 plus PCB case-to-ambient thermal resistance, RθJC is M1 junction-to-case thermal

resistance, RDSON is M1 channel resistance at the maximum operating temperature, and the factor of 0.7

accounts for the tolerance of the constant power engine. In this case we know that power limit is less than ILIMIT x

VIN and that power limit will control operation during a short circuit.

It is often advantageous to use a transient value of RθJC to get a usable solution, that is a VPROG within the

recommended range. If a current/power limited startup is used, transient RθJC should be based on the TIMER

period (see below). FET manufacturers typically provide transient thermal resistance in graphic format on their

datasheet. Additional information can be found in SLVA158.

The following equations calculate VPROG and R4 using an assumed R5= 20 kΩ.

(10)

(11)

Choose R4= 140 kΩ. The recommended minimum VPROG is 0.4 V. This is based on tolerance and accuracy of

the constant power engine making very low power-limited designs highly variable. Some suggestions to get

larger PLIM values are to start with a low static operating junction temperature, and to utilize the transient thermal

impedance (energy absorbing nature) of the package.

The output I vs. VOUT curve for this configuration is shown in Figure 20.

Figure 20. TPS2492/93 Power and Current Limit Curve

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C 416 1 0 2 0 1 4 75

4.1V

= ´ ´ + + =

As ( . . ) . nF

SOURCE(MAX)

T O-TOL T-TOL

TMR-TH(MAX)

C 1 C C

VON

t ( )= ´ ´ + +

VCC(MAX)

LIM

2 2

LIMIT(NOM) LIM

P1000 13 5

1000 249W 416

2 I 2 P 2 50 2 249W

´´

= + = + =

´ ´ ´ ´

CF . V

t s

( )

VCC(MAX)

LIM VCC(MAX) LIMIT(NOM)

LIMIT(NOM)

For P V I I

³ ´ = O

: t Current Limit Only

( )

LIM(ACT) VCC(MAX)

LIM VCC(MAX) LIMIT(NOM) 2

LIMIT(NOM) LIM(ACT)

P V

For P V I 2 I 2 P

´ ´

< ´ = +

´ ´

O O

C C

: t Power Limit

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SLUSA65C –JULY 2010–REVISED JANUARY 2013

4. Choose the TIMER Capacitor, CTand Turn-On Time

The turn on time tON, represents the time it takes the circuit to charge up the output capacitance COand load. CT

programs the fault time and should be chosen so that the fault timer does not terminate prior to completion of

start up. The turn on time is a function of the type of control; current limit, power limit, or dV/dt control. The

following equations calculates tON for the power limit and current limit cases, and assume that only COdraws

current during startup.

(12)

(13)

(14)

The next equation computes CTfor a TPS2492 application. TPS2492/93 TIMER current source and capacitor

tolerances are accounted for.

(15)

(16)

Choose CT= 6.8 nF assuming a 20% output capacitor tolerance and a 10% timing capacitor tolerance.

Equation 16 is written around startup for a TPS2492, however during a restart (after a fault) of a TPS2493, CT

charges from 1 V to 4.1 V, requiring a VTMR-TH(MAX) value of 3.1V.

The maximum TIMER period may be calculated using the minimum TIMER charge current and maximum value

of CT. Use this period to determine the transient RθJC in step 3. While this is beyond the scope of this example, it

may lead to some iteration.

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= -

GATE ON

G GD

VCC

I t

C C

=O VCC

CHARGE

C V

( )

R1= R1+R2 R2 9 7407 0 4133 9 3275- = W - W = W. k . k . k

( )

R2= R2+R3 R3 1 4133 1 0 4133- = W - W = W. k k . k

( )

UVEN_H

V 1 2 3 1 25 9 7407 1

R2+R3 1 4133

V 9 5

´ + + ´ W + W

= = = W

R R R . V . k k

. k

. V

( )

OV OV_H

UV_H

R3 V -V 1 14 5 1 35

R1+R2 9 7407

1 35

´W ´ -

= = = W

k . V . V

. k

. V

( )

R2+R3

R1+R2+R3

=UV

UVEN _ H

( )

R1+R2+R3

=OV

OV _ H

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5. Choose the Turn-On and Over-voltage Divider, R1- R3

Per our system design requirements above, both over-voltage shutdown and under-voltage shutdown are

desired. Equations for calculating the thresholds are:

(17)

(18)

Assume R3 is 1 kΩand use the following procedure to determine R1 and R2.

(19)

(20)

(21)

(22)

Selecting standard 1% values and scaling up by a factor of 10 to reduce power loss results in (R1 = 93.1 kΩ),

(R2 = 4.12 kΩ), and (R3 = 10 kΩ).

Alternative Inrush Designs

Gate Capacitor (dV/dt) Control

The TPS2492/93 can be used with applications that require constant turn-on currents. The current is controlled

by a single capacitor from the GATE terminal to ground with a series resistor. M1 appears to operate as a source

follower (following the gate voltage) in this implementation. Again assuming that the output capacitor charges

without additional loading, choose a time to charge, tON, based on the load capacitor, COinput voltage VI, and

desired charge current ICHARGE. When power limiting is used (VPROG < VREF) choose ICHARGE to be less than PLIM

/VVCC to prevent the fault timer from starting. The fault timer starts only if power or current limit is invoked.

(23)

Use the following equation to select the gate capacitance, CG. It has been assumed that the external added

(linear) capacitor is much larger than the FET capacitance. CGD is the gate capacitance of M1, and IGATE is the

TPS2492/93 nominal gate charge current. CGD is non-linear with applied VDG. An averaged estimate may be

made using the FET VGS vs QGcurve. Divide the charge accumulated during the plateau region by the plateau

VGS to get CGD. As shown in Figure 19, a series resistor of about 1 kΩshould be used in series with CGto avoid

slowing the turnoff.

(24)

If neither power nor current limit faults are invoked during turn on, CTcan be chosen for fast transient turnoff

response. Considerations are junction temperature rise (as above), anticipated system noise, and possible peak

overloads due to input voltage or load transients. Generally the period should be much less than the tON of step 4

above.

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Additional Design Considerations

Calculation Tool SLVC033

The calculation tool for the TPS2490/91, SLVC033, may be used with the TPS2492/93. For accurate results, the

timer current constants need to be updated. This may be accomplished using the Excel Tools / Protection

command along with the password provided in the tool (spreadsheet).

Use of PG to Control Downstream Converters

Use the PG pin to control and sequence a downstream DC/DC converter. If this is not done a long time delay

may be needed to allow COto fully charge before the converter starts. This practice will avoid having the

converter attempt to operate at a low input voltage, drawing large currents. This mode of converter operation has

the potential to form a stable operating point with the hotswap output I-V characteristic, preventing the system

from starting.

IMON Filtering

The internal monitoring circuits leave a small amount of residual noise at about 2.5 kHz on the IMON output.

While this does not contribute significant error at output voltages on the order of 1 V, better accuracy at low

outputs will benefit from an R-C filter. Figure 19 demonstrates this filtering with elements R6 and C2. An example

solution is a 1 kΩresistor and a 1.5 nF capacitor. A buffer (e.g. unity-gain opamp) may be required if the output

is used by a circuit that draws significant current.

Output Clamp Diode

Inductive loads or wiring inductance on the output may drive the OUT pin below GND when the circuit is

unplugged or during current limit. The OUT pin can be protected by D2 (see Figure 19) between the TPS2492/93

OUT to GND pins. The OUT pin can withstand a short transient to -1 V.

Input Clamp TVS

Energy stored in the inductance of input wiring has the capability to drive the input voltage up if the (load) current

is abruptly decreased. An example is a hard short on OUT rapidly raising the input current above the current limit

threshold, which is then abruptly driven to zero when the current limit gains control after several microseconds.

Combinations of input capacitance and transient voltage suppressor diodes (TVS - a type of Zener Diode) can

aid in controlling the voltage overshoot. This is demonstrated by D1 and C1 of Figure 19. While a small bypass

capacitor is recommended, the TVS is better able to control the voltage without the drawback of large input

capacitance.

Gate Clamp Diode

The TPS2492/93 has a relatively well-regulated gate voltage of 12 V to 16 V, even at low supply voltages. A

small clamp Zener from gate to source of M1, such as a BZX84C7V5, is recommended if VGS of M1 is rated

below this.

Input Bypass Capacitance

The input bypass capacitor, C1 per Figure 19 should be used to provide a low impedance local source of current

and control the supply dv/dt on the VCC pin.

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RETRY T

T =C 19 6 10´ ´.

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Adding External GATE-OUT Capacitance

Avoid directly placing ceramic capacitors directly across M1 gate to source when bypassing for ESD or noise is

desired. Add some small resistance in series with the capacitor if absolutely required. If the resistance is not

present, the added phase shift may encourage high frequency oscillation of the combined input and output L-C

circuits during startup conditions.

High Gate Capacitance Applications

If OUT falls very rapidly during a fault, the FET VGS can be driven high by the CGD - CGS voltage divider of

(VSENSE - VOUT). Given enough capacitance and dv/dt, the internal 14-V GATE to OUT clamp may not have the

capability to fully control the voltage. An external gate clamp Zener diode may be required to protect the FET if

this is the case.

When gate capacitor dV/dT control is used, a 1-kΩresistor in series with CGis recommended, as shown in

Figure 19.

Output Short Circuit Measurements

Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads,

circuit layout and component selection, output shorting method, relative location of the short, and instrumentation

all contribute to varying results. The actual short itself exhibits a certain degree of randomness as it

microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do

not expect to see waveforms exactly like those in the data sheet since every setup differs.

Applications Using the Retry Feature (TPS2493)

Applications using the retry feature may want to estimate fault retry time. The TPS2493 will retry (enable M1 to

attempt turn on) once for every 16 timer charge/discharge cycles (15 cycles between 1 V and 4 V, 1 cycle

between 0 V and 4 V).

(25)

M1 Selection

Use of a power FET in the linear region places large, long term stresses on the distributed junction. FETs whose

safe operating area (SOA) curves display multiple slopes on the same line (e.g. a line whose time parameter is a

constant) in the region of high voltage and low current generally are susceptible to secondary breakdown and are

not strong candidates for this application. An example of a good choice is found in the Typical Application Circuit

where the line at 10 ms shows no breaks in slope. The best device for the application is not always the lowest

RDSON device.

Layout Considerations

Good layout practice places the power devices D1, RSENSE, M1, and COso power flows in a sequential, linear

fashion. A ground plane under the power and the TPS2492/93 is desirable. The TPS2492/93 should be placed

close to the sense resistor and FET using a Kelvin type connection to achieve accurate current sensing across

RSENSE. A low-impedance GND connection is required because the TPS2492/93 can momentarily sink upwards

of 100 mA from the gate of M1. The GATE amplifier has high bandwidth while active, so keep the GATE trace

length short. The PROG, TIMER, OV, and UVEN pins have high input impedances, therefore keep their input

leads short. Oversize power traces and power device connections to assure low voltage drop and good thermal

performance.

Product Folder Links: TPS2492 TPS2493

l TEXAS INSTRUMENTS

TPS2492

TPS2493

www.ti.com

SLUSA65C –JULY 2010–REVISED JANUARY 2013

REVISION HISTORY

Changes from Original (July 2010) to Revision A Page

• Changed marketing status .................................................................................................................................................... 1

Changes from Revision A (#IMPLIED) to Revision B Page

• Changed temperature rating from 80°C to 125°C in the product Information section to match the rest of the

datasheet. ............................................................................................................................................................................. 2

Changes from Revision B (October 2011) to Revision C Page

• Added design calculator hyperlink. ....................................................................................................................................... 1

Product Folder Links: TPS2492 TPS2493

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TPS2492PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TPS2492

TPS2492PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TPS2492

TPS2493PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TPS2493

TPS2493PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TPS2493

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

I TEXAS INSTRUMENTS ‘3‘ V.'

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

Reel Width (W1)

REEL DIMENSIONS

Dimension designed to accommodate the component length

Dimension designed to accommodate the component thickness

Overall width of the carrier tape

Pitch between successive cavity centers

Dimension designed to accommodate the component width

TAPE DIMENSIONS

K0 P1

B0 W

Cavity

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Pocket Quadrants

Sprocket Holes

Q1 Q1Q2 Q2

Q3 Q3Q4 Q4 User Direction of Feed

Reel

Diameter

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS2492PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

TPS2493PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS2492PWR TSSOP PW 14 2000 356.0 356.0 35.0

TPS2493PWR TSSOP PW 14 2000 356.0 356.0 35.0

Pack Materials-Page 2

I TEXAS INSTRUMENTS __________________ ‘(I(I“""""""""

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

L - Tube length

T - Tube

height

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

TPS2492PW PW TSSOP 14 90 530 10.2 3600 3.5

TPS2493PW PW TSSOP 14 90 530 10.2 3600 3.5

Pack Materials-Page 3

MECHANICAL DATA "7’7 : 3‘ AST‘C SMAH CJ’ N7 HHHHHHH . . ‘7,4’ 44*, A f;—‘ NO'ES' A AH Hnec' dimensmrs c'e m m'\\me(ers Dwmens'amnq cnd tu‘erc'vcmg per ASME w 5M 1994, Tm drawer ‘5 subje», ,o "hangs wnrau: Home, Budy \evvgih ‘ues m W" Le mom Hush, pyuws‘m Ur guts Ms M exceed 0,15 each m & Rudy wde does NM Wands \Mer end ﬂair \Meﬁead 'Wclsh shaH um exceed 0‘75 each S‘de E Fa‘s WM" JEDEC M07153 MUM "\u>h, main: bus, 01 guie buns shuH {if TEXAS INSTRUMENTS www.ci.com

PW (RiPDsoicM) LAND PATTERN DATA PLASTHC SMALL OUTLINE Example Board Layout (Male 0) —>| ‘,——12x0 65 HHHHHHHi 5,60 HHHHHHHHi l“ l l l Example Non So‘dermask Deﬁned Pad 4 x 1,60 / H l <—0,07 y/="" ah="" around="" pad="" seamelry="" (see="" nale="" c)="" solder="" mask="" opening="" (see="" note="" e)="" stencil="" 0="" en'ln="" s="" (notepd)="" ‘3="" 14x0="" 30="" h="" '«,lzxo="" 65="" ~hhhhhh~="" 5,60="" hhhhhhh—="" example="" example="" 421128472/6="" 08/15="" notes:="" ah="" h‘lneor="" dimensions="" one="" in="" rnihll'rneters.="" tn‘ls="" dvowing="" is="" subject="" lp="" change="" wltnoul="" nallee.="" publl'cotlon="" hpcjssh="" is="" recommended="" lar="" allemale="" deslgns.="" laser="" cutllng="" apertures="" wch="" tropexoidm="" walls="" and="" also="" raund‘lna="" comers="" wlll="" we!="" better="" pasle="" release="" customers="" show="" contact="" their="" board="" assembly="" sl’te="" (ov="" stenci‘="" design="" recommendations.="" reler="" to="" ”50—7525="" lur="" other="" stencl‘="" recommendotluns="" customers="" shou‘d="" contact="" their="" board="" hoercot'lon="" shte="" (or="" solder="" musk="" tolerances="" between="" and="" around="" s'lgnol="" pods.="" *1?="" tums="" instruments="" www.ti.com="">

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

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Scheda tecnica TPS2492,93 di Texas Instruments

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