Scheda tecnica USB7216C

MICRQICHIP USB7216C
2021 Microchip Technology Inc. DS00003851A-page 1
USB7216C
Highlights
• 6-Port USB Smart Hub with:
- Native USB Gen 2 Type-C® support on
downstream port 1
- Three Standard USB 3.2 Gen 2 downstream ports
- Two Standard USB 2.0 downstream ports
- Internal Hub Feature Controller enables:
- USB to I2C/SPI/I2S/GPIO bridge endpointsupport
- USB to internal hub register write and read
• USB Link Power Management (LPM) support
• Programming of firmware image to external SPI
memory device from USB host
• USB-IF Battery Charger revision 1.2 support on
downstream ports (DCP, CDP, SDP)
• Enhanced OEM configuration options available
through either OTP or external SPI memory
• Available in 100-pin (12mm x 12mm) VQFN
RoHS compliant package
• Commercial and industrial grade temperature
support
Target Applications
• Standalone USB Hubs
• Laptop Docks
• PC Motherboards
• PC Monitor Docks
• Multi-function USB 3.2 Gen 2 Peripherals
Key Benefits
• USB 3.2 Gen 2 compliant 10 Gbps, 5 Gbps,
480 Mbps, 12 Mbps, and 1.5Mbps operation
- 5V tolerant USB 2.0 pins
- 1.21V tolerant USB 3.2 Gen 2 pins
- Integrated termination and pull-up/down resistors
• Native USB Type-C Support
- Type-C CC Pin with integrated Rp and Rd resistors
- Integrated multiplexer on USB Type-C enabled
ports. USB 3.2 Gen 2 PHYs are disabled until a
valid Type-C attach is detected, saving idle power.
Control for external VCONN supply
* USB Type-C® and USB-C® are registered trademarks of USB Implement-
ers Forum
• Supports battery charging of most popular battery
powered devices on all ports
- USB-IF Battery Charging rev. 1.2 support
(DCP, CDP, SDP)
- Apple® portable product charger emulation
- Chinese YD/T 1591-2006/2009 charger emulation
- European Union universal mobile charger support
- Supports additional portable devices
• On-chip Microcontroller
- manages I/Os, VBUS, and other signals
• 96kB RAM, 256kB ROM
• 8kB One-Time-Programmable (OTP) ROM
- Includes on-chip charge pump
• Configuration programming via OTP Memory, SPI
external memory, or SMBus
• FlexConnect
- The roles of the upstream and all downstream
ports are reversible on command
• Multi-Host Endpoint Reflector
- Integrated host-controller endpoint reflector via
CDC/NCM device class for automotive applications
• USB Bridging
- USB to I2C, SPI, I2S, and GPIO
• PortSwap
- Configurable USB 2.0 differential pair signal swap
• PHYBoost
- Programmable USB transceiver drive strength for
recovering signal integrity
• VariSense
- Programmable USB receive sensitivity
• USB Power Delivery Billboard Device Support
- Internal port can enumerate as a Power Delivery
Billboard device to communicate Power Delivery
Alternate Mode negotiation failure cases to host
• Compatible with Microsoft Windows 10, 8, 7, XP,
Apple OS X 10.4+, and Linux hub drivers
• Optimized for low-power operation and low ther-
mal dissipation
• 100-pin VQFN package (12mm x 12mm)
6-Port USB 3.2 Gen 2 Type-C® Controller Hub
USB7216C
DS00003851A-page 2 2021 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
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2021 Microchip Technology Inc. DS00003851A-page 3
USB7216C
1.0 PREFACE
1.1 General Terms
TABLE 1-1: GENERAL TERMS
Term Description
ADC Analog-to-Digital Converter
Byte 8 bits
CDC Communication Device Class
CSR Control and Status Registers
DFP Downstream Facing Port
DWORD 32 bits
EOP End of Packet
EP Endpoint
FIFO First In First Out buffer
FS Full-Speed
FSM Finite State Machine
GPIO General Purpose I/O
HS Hi-Speed
HSOS High Speed Over Sampling
Hub Feature Controller The Hub Feature Controller, sometimes called a Hub Controller for short is the internal
processor used to enable the unique features of the USB Controller Hub. This is not to
be confused with the USB Hub Controller that is used to communicate the hub status
back to the Host during a USB session.
I2CInter-Integrated Circuit
LS Low-Speed
lsb Least Significant Bit
LSB Least Significant Byte
msb Most Significant Bit
MSB Most Significant Byte
N/A Not Applicable
NC No Connect
OTP One Time Programmable
PCB Printed Circuit Board
PCS Physical Coding Sublayer
PHY Physical Layer
PLL Phase Lock Loop
RESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaran-
teed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
SDK Software Development Kit
SMBus System Management Bus
UFP Upstream Facing Port
UUID Universally Unique IDentifier
WORD 16 bits
USB7216C
DS00003851A-page 4 2021 Microchip Technology Inc.
1.2 Buffer Types
TABLE 1-2: BUFFER TYPES
Buffer Type Description
I Input.
IS Input with Schmitt trigger.
O12 Output buffer with 12 mA sink and 12 mA source.
OD12 Open-drain output with 12 mA sink
PU 50 μA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-
ups are always enabled.
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal
resistors to drive signals external to the device. When connected to a load that must be
pulled high, an external resistor must be added.
PD 50 μA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load that
must be pulled low, an external resistor must be added.
ICLK Crystal oscillator input pin
OCLK Crystal oscillator output pin
I/O-U Analog input/output defined in USB specification.
I-R RBIAS.
A Analog.
AIO Analog bidirectional.
P Power pin.
2021 Microchip Technology Inc. DS00003851A-page 5
USB7216C
1.3 Pin Reset States
The pin reset state definitions are detailed in Table 1-3. Refer to Section 3.1, Pin Assignments for details on individual
pin reset states.
1.4 Reference Documents
1. Universal Serial Bus Revision 3.2 Specification, http://www.usb.org
2. Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org
3. I2C-Bus Specification, Version 1.1, http://www.nxp.com/documents/user_manual/UM10204.pdf
4. I2S-Bus Specification, http://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf
5. System Management Bus Specification, Version 1.0, http://smbus.org/specs
TABLE 1-3: PIN RESET STATE LEGEND
Symbol Description
AI Analog input
AIO Analog input/output
AO Analog output
PD Hardware enables pull-down
PU Hardware enables pull-up
Y Hardware enables function
Z Hardware disables output driver (high impedance)
PU Hardware enables internal pull-up
PD Hardware enables internal pull-down
Note: Additional USB7216C resources can be found on the Microchip USB7216C product page at
www.microchip.com/USB7216C.
am am
USB7216C
DS00003851A-page 6 2021 Microchip Technology Inc.
2.0 INTRODUCTION
2.1 General Description
The Microchip USB7216C hub is a low-power, OEM configurable, USB 3.2 Gen 2 hub controller with 6 downstream
ports and advanced features for embedded USB applications. The USB7216C is fully compliant with the Universal Serial
Bus Revision 3.2 Specification and USB 2.0 Link Power Management Addendum. The USB7216C supports 10 Gbps
SuperSpeed+ (SS+), 5 Gbps SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-
Speed (LS) USB downstream devices on four standard USB 3.2 Gen 2 downstream ports and only legacy speeds (HS/
FS/LS) on two standard USB 2.0 downstream ports.
The USB7216C is a standard USB 3.2 Gen 2 hub that supports native basic Type-C with integrated CC logic on down-
stream port 1. The downstream Type-C port includes an internal USB 3.2 Gen 2 multiplexer; no external multiplexer is
required for Type-C support.
The USB7216C supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub controller that is the
culmination of seven generations of Microchip hub feature controller design and experience with proven reliability,
interoperability, and device compatibility. The SuperSpeed hub controller operates in parallel with the USB 2.0 controller,
decoupling the 10/5 Gbps SS+/SS data transfers from bottlenecks due to the slower USB 2.0 traffic.
The USB7216C enables OEMs to configure their system using “Configuration Straps.” These straps simplify the config-
uration process assigning default values to USB 3.2 Gen 2 ports and GPIOs. OEMs can disable ports, enable battery
charging and define GPIO functions as default assignments on power up removing the need for OTP or external SPI
ROM.
The USB7216C supports downstream battery charging. The USB7216C integrated battery charger detection circuitry
supports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB7216C provides the
battery charging handshake and supports the following USB-IF BC1.2 charging profiles:
• DCP: Dedicated Charging Port (Power brick with no data)
• CDP: Charging Downstream Port (1.5A with data)
• SDP: Standard Downstream Port (0.5A[USB 2.0]/0.9A[USB 3.2] with data)
Additionally, the USB7216C includes many powerful and unique features such as:
The Hub Feature Controller, an internal USB device dedicated for use as a USB to I2C/SPI/GPIO interface that allows
external circuits or devices to be monitored, controlled, or configured via the USB interface.
Multi-Host Endpoint Reflector, which provides unique USB functionality whereby USB data can be “mirrored” between
two USB hosts (Multi-Host) in order to perform a single USB transaction.This capability is fully covered by Microchip
intellectual property (U.S. Pat. Nos. 7,523,243 and 7,627,708) and is instrumental in enabling Apple CarPlay™, where
the Apple iPhone® becomes a USB Host.
FlexConnect, which provides flexible connectivity options. One of the USB7216C’s downstream ports can be reconfig-
ured to become the upstream port, allowing master capable devices to control other devices on the hub.
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength
in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity
in a compromised system environment. The graphic on the right shows an example of
Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in
a compromised system environment.
VariSense, which controls the Hi-Speed USB receiver sensitivity enabling programmable levels of USB signal receive
sensitivity. This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is
used.
Port Split, which allows for the USB 3.2 Gen 2 and USB 2.0 portions of downstream ports 2, 3, and 4 in Configuration
1 and downstream port 4 (only) in Configuration 2 to operate independently and enumerate two separate devices in
parallel in special applications.
USB Power Delivery Billboard Device, which allows an internal device to enumerate as a Billboard class device when
a Power Delivery Alternate Mode negotiation has failed. The Billboard device will enumerate temporarily to the host PC
when a failure occurs, as indicated by a digital signal from an external Power Delivery controller.
2021 Microchip Technology Inc. DS00003851A-page 7
USB7216C
The USB7216C can be configured for operation through internal default settings. Custom OEM configurations are sup-
ported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow
for maximum operational flexibility and are available as GPIOs for customer specific use.
The USB7216C is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature range. An inter-
nal block diagram of the USB7216C in an upstream Type-B application is shown in Figure 2-1.
FIGURE 2-1: USB7216C INTERNAL BLOCK DIAGRAM - UPSTREAM TYPE-B APPLICATION
Note: All port numbering in this document is LOGICAL port numbering with the device in the default configuration.
LOGICAL port numbering is the numbering as communicated to the USB host. It is the end result after any
port number remapping or port disabling. The PHYSICAL port number is the port number with respect to
the physical PHY on the chip. PHYSICAL port numbering is fixed and the settings are not impacted by
LOGICAL port renumbering/remapping. Certain port settings are made with respect to LOGICAL port num-
bering, and other port settings are made with respect to PHYSICAL port numbering. Refer to the “Config-
uration of USB7202/USB7206/USB725x” application note for details on the LOGICAL vs. PHYSICAL
mapping and additional configuration details.
Hub Controller Logic
I
2
C/SPI
25 Mhz
USB3 USB2
P5
‘A’
USB7216C
+3.3 V
VCORE
PHY2PHY1
PHY2
‘B’
PHY1
‘A’
P1
‘C’
CC
P2
‘A’
PHY3 PHY3
P3
‘A’
PHY4 PHY4
P4
‘A’
PHY5 PHY5
P6
‘A’
PHY6
Hub Feature Controller
GPIO SMB
OTP
SPI I
2
S
Mux
HFC
PHY
PHY0PHY0
P0
‘B’
7.1. 1.1.41.1 1.1 1 4 1 1.1.1 1 4 1 1 1 4 1 1.1.1 1 4 J1
USB7216C
DS00003851A-page 8 2021 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
3.1 Pin Assignments
FIGURE 3-1: USB7216C 100-VQFN PIN ASSIGNMENTS
Note: Configuration straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load.
Thermal slug connects to VSS
100
99
98
97
96
95
94
93
92
90
89
88
87
86
85
91
16
15
14
13
12
11
10
9
8
6
5
4
3
2
1
7
41
40
39
37
36
35
34
33
32
31
30
29
28
27
26
75
74
73
72
71
70
68
67
66
65
69
64
63
62
61
60
38
25
24
23
22
21
20
19
18
17
50
49
48
46
45
44
43
42
47
59
58
57
56
55
54
53
52
51
84
83
81
80
79
78
77
76
82
Microchip
USB7216C
(Top View 100-VQFN)
RESET_N
DP1_VBUS_MON
PF31
DP1_CC1
USB3DN_RXDM1A
USB3DN_RXDP1A
VCORE
USB3DN_TXDM1A
USB3DN_TXDP1A
USB2DN_DM1/PRT_DIS_M1
PF30
USB3DN_RXDM1B
USB2DN_DP1/PRT_DIS_P1
USB3DN_RXDP1B
VCORE
USB3DN_TXDM1B
USB3DN_TXDP1B
USB2DN_DM5/PRT_DIS_M5
USB2DN_DP5/PRT_DIS_P5
DP1_CC2
CFG_STRAP1
CFG_STRAP2
CFG_STRAP3
TESTEN
VCORE
USB2DN_DP2/PRT_DIS_P2
USB3DN_TXDP3
USB2DN_DM3/PRT_DIS_M3
VCORE
USB3DN_TXDM3
USB2DN_DM2/PRT_DIS_M2
USB2DN_DP3/PRT_DIS_P3
USB3DN_RXDM2
VCORE
USB3DN_TXDM2
USB3DN_TXDP2
VDD3 3
USB3DN_RXDP2
PF9
USB3DN_RXDP3
USB2DN_DM6/PRT_DIS_M6
USB3DN_RXDM3
PF3
VDD3 3
PF5
PF4
PF6
PF8
PF7
USB2DN_DP6/PRT_DIS_P6
PF17
SPI_D3/PF25
SPI_D0/CFG_BC_EN/PF22
SPI_CLK/PF21
VDD3 3
SPI_D1/PF23
PF19
PF26
TEST3
SPI_CE_N/CFG_NON_REM/PF20
TEST1
PF10
PF13
VDD3 3
TEST2
SPI_D2/PF24
PF18
PF15
PF16
VDD3 3
VCORE
PF12
PF29
PF11
PF14
PF27
PF28
VCORE
VCORE
USB3DN_TXDM4
USB3DN_TXDP4
USB2DN_DM4/PRT_DIS_M4
USB2DN_DP4/PRT_DIS_P4
VBUS_MON_UP
VDD33
USB3UP_TXDM
USB3UP_TXDP
USB2UP_DM
USB2UP_DP
VDD33
USB3DN_RXDM4
USB3DN_RXDP4
RBIAS
VDD33
XTALI/CLK_IN
XTALO
ATEST
USB3UP_RXDM
USB3UP_RXDP
VCORE
cu; Mum 0-1; a l RAP: mm mm m w «W mu m , mu mu mu m
2021 Microchip Technology Inc. DS00003851A-page 9
USB7216C
Pin Num Pin Name Reset Pin Num Pin Name Reset
1RESET_N Z 51 PF10 PD
2PF30 Z 52 PF11 PD
3PF31 Z 53 VDD33 Z
4DP1_VBUS_MON AI 54 PF12 PD
5USB2DN_DP1/PRT_DIS_P1 AIO PD 55 VCORE Z
6USB2DN_DM1/PRT_DIS_M1 AIO PD 56 PF13 PD
7USB3DN_TXDP1A AO PD 57 PF14 PD
8USB3DN_TXDM1A AO PD 58 PF15 PD
9VCORE Z 59 PF16 PD
10 USB3DN_RXDP1A AI PD 60 PF17 PD
11 USB3DN_RXDM1A AI PD 61 PF18 Z
12 DP1_CC1 AI 62 VDD33 Z
13 DP1_CC2 AI 63 TEST1 Z
14 USB2DN_DP5/PRT_DIS_P5 AIO PD 64 TEST2 Z
15 USB2DN_DM5/PRT_DIS_M5 AIO PD 65 TEST3 Z
16 USB3DN_TXDP1B AO PD 66 PF19 Z
17 USB3DN_TXDM1B AO PD 67 VDD33 Z
18 VCORE Z 68 SPI_CLK/PF21 Z
19 USB3DN_RXDP1B AI PD 69 SPI_CE_N/CFG_NON_REM/PF20 PU
20 USB3DN_RXDM1B AI PD 70 SPI_D0/CFG_BC_EN/PF22 Z
21 CFG_STRAP1 Z 71 SPI_D1/PF23 Z
22 CFG_STRAP2 Z 72 SPI_D2/PF24 Z
23 CFG_STRAP3 Z 73 SPI_D3/PF25 Z
24 TESTEN Z 74 PF29 Z
25 VCORE Z 75 PF26 Z
26 VDD33 Z 76 PF27 Z
27 USB2DN_DP2/PRT_DIS_P2 AIO PD 77 PF28 Z
28 USB2DN_DM2/PRT_DIS_M2 AIO PD 78 VCORE Z
29 USB3DN_TXDP2 AO PD 79 VDD33 Z
30 USB3DN_TXDM2 AO PD 80 VBUS_MON_UP AI
31 VCORE Z 81 USB2DN_DP4/PRT_DIS_P4 AIO PD
32 USB3DN_RXDP2 AI PD 82 USB2DN_DM4/PRT_DIS_M4 AIO PD
33 USB3DN_RXDM2 AI PD 83 USB3DN_TXDP4 AO PD
34 USB2DN_DP3/PRT_DIS_P3 AIO PD 84 USB3DN_TXDM4 AO PD
35 USB2DN_DM3/PRT_DIS_M3 AIO PD 85 VCORE Z
36 USB3DN_TXDP3 AO PD 86 USB3DN_RXDP4 AI PD
37 USB3DN_TXDM3 AO PD 87 USB3DN_RXDM4 AI PD
38 VCORE Z 88 VDD33 Z
39 USB3DN_RXDP3 AI PD 89 USB2UP_DP AIO Z
40 USB3DN_RXDM3 AI PD 90 USB2UP_DM AIO Z
41 USB2DN_DM6/PRT_DIS_M6 AIO PD 91 USB3UP_TXDP AO PD
42 USB2DN_DP6/PRT_DIS_P6 AIO PD 92 USB3UP_TXDM AO PD
43 VDD33 Z 93 VCORE Z
44 PF3 Z 94 USB3UP_RXDP AI PD
45 PF4 Z 95 USB3UP_RXDM AI PD
46 PF5 Z 96 ATEST AO
47 PF6 Z 97 XTALO AO
48 PF7 Z 98 XTALI/CLK_IN AI
49 PF8 Z 99 VDD33 Z
50 PF9 Z 100 RBIAS AI
Exposed Pad (VSS) must be connected to ground.
USB7216C
DS00003851A-page 10 2021 Microchip Technology Inc.
3.2 Pin Descriptions
This section contains descriptions of the various USB7216C pins. The “_N” symbol in the signal name indicates that the
active, or asserted, state occurs when the signal is at a low voltage level. For example, RESET_N indicates that the
reset signal is active low. When “_N” is not present after the signal name, the signal is asserted when at the high voltage
level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of
“active low” and “active high” signal. The term assert, or assertion, indicates that a signal is active, independent of
whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inac-
tive.
The “If Unused” column provides information on how to terminate pins if they are unused in a customer design.
Buffer type definitions are detailed in Section 1.2, Buffer Types.
TABLE 3-1: PIN DESCRIPTIONS
Name Symbol Buffer
Type Description If Unused
USB 3.2 Gen 2 Interfaces
Upstream USB
3.2 Gen 2 TX D+
USB3UP_TXDP I/O-U Upstream USB 3.2 Gen 2 Transmit Data
Plus.
Float
Upstream USB
3.2 Gen 2 TX D-
USB3UP_TXDM I/O-U Upstream USB 3.2 Gen 2 Transmit Data
Minus.
Float
Upstream USB
3.2 Gen 2 RX D+
USB3UP_RXDP I/O-U Upstream USB 3.2 Gen 2 Receive Data
Plus.
Weak pull-
down to
GND
Upstream USB
3.2 Gen 2 RX D-
USB3UP_RXDM I/O-U Upstream USB 3.2 Gen 2 Receive Data
Minus.
Weak pull-
down to
GND
Downstream
Port 1 USB 3.2
Gen 2 TX D+
Orientation A
USB3DN_TXDP1A I/O-U Downstream USB Type-C® “Orientation A”
SuperSpeed+ Transmit Data Plus, port 1.
Float
Downstream
Port 1 USB 3.2
Gen 2 TX D- Ori-
entation A
USB3DN_TXDM1A I/O-U Downstream USB Type-C “Orientation A”
SuperSpeed+ Transmit Data Minus, port 1.
Float
Downstream
Port 1 USB 3.2
Gen 2 RX D+
Orientation A
USB3DN_RXDP1A I/O-U Downstream USB Type-C “Orientation A”
SuperSpeed+ Receive Data Plus, port 1.
Weak pull-
down to
GND
Downstream
Port 1 USB 3.2
Gen 2 RX D-
Orientation A
USB3DN_RXDM1A I/O-U Downstream USB Type-C “Orientation A”
SuperSpeed+ Receive Data Minus, port 1.
Weak pull-
down to
GND
Downstream
Port 1 USB 3.2
Gen 2 TX D+
Orientation B
USB3DN_TXDP1B I/O-U Downstream USB Type-C “Orientation B”
SuperSpeed+ Transmit Data Plus, port 1.
Float
2021 Microchip Technology Inc. DS00003851A-page 11
USB7216C
Downstream
Port 1 USB 3.2
Gen 2 TX D-
Orientation B
USB3DN_TXDM1B I/O-U Downstream USB Type-C “Orientation B”
SuperSpeed+ Transmit Data Minus, port 1.
Float
Downstream
Port 1 USB 3.2
Gen 2 RX D+
Orientation B
USB3DN_RXDP1B I/O-U Downstream USB Type-C “Orientation B”
SuperSpeed+ Receive Data Plus, port 1.
Weak pull-
down to
GND
Downstream
Port 1 USB 3.2
Gen 2 RX D-
Orientation B
USB3DN_RXDM1B I/O-U Downstream USB Type-C “Orientation B”
SuperSpeed+ Receive Data Minus, port 1.
Weak pull-
down to
GND
Downstream
Ports 2-4 USB
3.2 Gen 2 TX D+
USB3DN_TXDP[2:4] I/O-U Downstream SuperSpeed+ Transmit Data
Plus, ports 2 through 4.
Float
Downstream
Ports 2-4 USB
3.2 Gen 2 TX D-
USB3DN_TXDM[2:4] I/O-U Downstream SuperSpeed+ Transmit Data
Minus, ports 2 through 4.
Float
Downstream
Ports 2-4 USB
3.2 Gen 2 RX D+
USB3DN_RXDP[2:4] I/O-U Downstream SuperSpeed+ Receive Data
Plus, ports 2 through 4.
Weak pull-
down to
GND
Downstream
Ports 2-4 USB
3.2 Gen 2 RX D-
USB3DN_RXDM[2:4] I/O-U Downstream SuperSpeed+ Receive Data
Minus, ports 2 through 4.
Weak pull-
down to
GND
USB 2.0 Interfaces
Upstream USB
2.0 D+
USB2UP_DP I/O-U Upstream USB 2.0 Data Plus (D+). Mandatory
Note 3-9
Upstream USB
2.0 D-
USB2UP_DM I/O-U Upstream USB 2.0 Data Minus (D-). Mandatory
Note 3-9
Downstream
Ports 1-6 USB
2.0 D+
USB2DN_DP[1:6] I/O-U Downstream USB 2.0 Ports 1-6 Data Plus
(D+).
Connect
directly to
3.3V
Downstream
Ports 1-6 USB
2.0 D-
USB2DN_DM[1:6] I/O-U Downstream USB 2.0 Ports 1-6 Data Minus
(D-)
Connect
directly to
3.3V
SPI Interface
SPI Clock SPI_CLK I/O-U SPI clock. If the SPI interface is enabled,
this pin must be driven low during reset.
Weak pull-
down to
GND
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Name Symbol Buffer
Type Description If Unused
swine operal cm BC EN Operates as CFC N0]\ REM
USB7216C
DS00003851A-page 12 2021 Microchip Technology Inc.
SPI Data 3-0 SPI_D[3:0] I/O-U SPI Data 3-0. If the SPI interface is enabled,
these signals function as Data 3 through 0.
Note 3-1 SPI_D0 operates as the
C F G _ B C _ E N s t r a p i f
external SPI memory is not
used. It must be terminated
with the selected strap
resistor to 3.3V or GND.
S P I _ D [ 1 : 3 ] sh o u l d b e
connected to GND through
a weak pull-down.
Note 3-1
SPI Chip
Enable
SPI_CE_N I/O12 Active low SPI chip enable input. If the SPI
interface is enabled, this pin must be driven
high in powerdown states.
Note 3-2 Operates as the
CFG_NON_REM strap if
external SPI memory is not
used. It must be terminated
with the selected strap
resistor to 3.3V or GND.
Note 3-2
USB Type-C Connector Control
Downstream
Port 1 Type-C
Voltage Monitor
DP1_VBUS_MON AIO Used to detect Type-C VBUS vSafe5V and
vSafe0V states on Port 1. A nominal voltage
of 2.7V (2.4V min -3.0V max) is required to
detect the presence of vSafe5V.
Externally, VBUS can be as high as 5.25 V,
which can be damaging to this pin. The
amplitude of VBUS must be reduced by a
voltage divider. The recommended voltage
divider is shown below. 1% tolerance resis-
tors are recommended.
For proper Type-C port operation, it is criti-
cal that this pin actually be connected to
VBUS of the port through the recommended
resistor divider. This pin should not be tied
permanently to a fixed voltage power rail.
Note 3-3 If unused: Weak pull-down
to GND. This pin may be
left unused if Port 1 is
disabled or reconfigured to
operate in legacy Type-A
m o d e t h r o u g h h u b
configuration.
Note 3-3
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Name Symbol Buffer
Type Description If Unused
VBUS_P1
43K
49.9K
DP1_VBUS_MON
2021 Microchip Technology Inc. DS00003851A-page 13
USB7216C
Downstream
Port 1 Type-C
CC1
DP1_CC1 I/O12 Used for Type-C attach and orientation
detection on Port 1. Includes configurable
Rp/Ra selection. Connect this pin directly to
the CC1 pin of the respective Type-C con-
nector.
Note 3-4 If unused: Weak pull-down
to GND. This pin may only
be left unused if Port 1 is
disabled or reconfigured to
operate in legacy Type-A
m o d e t h r o u g h h u b
configuration.
Note 3-4
Downstream
Port 1 Type-C
CC2
DP1_CC2 I/O12 Used for Type-C attach and orientation
detection on Port 1. Includes configurable
Rp/Ra selection. Connect this pin directly to
the CC2 pin of the respective Type-C con-
nector.
Note 3-5 If unused: Weak pull-down
to GND. This pin may only
be left unused if Port 1 is
disabled or reconfigured to
operate in legacy Type-A
m o d e t h r o u g h h u b
configuration.
Note 3-5
Upstream
Voltage Monitor
VBUS_MON_UP I/O12 Used to detect VBUS on the upstream port.
Externally, VBUS can be as high as 5.25 V,
which can be damaging to this pin. A nomi-
nal voltage of 2.7V (2.4V min -3.0V max) is
required to detect the presence of vSafe5V.
The amplitude of VBUS must be reduced by
a voltage divider. The recommended voltage
divider is shown below. 1% tolerance resis-
tors are recommended.
Note: For embedded host applications,
this pin should be controlled by
an I/O on the host processor to a
2.68V logic level.
Mandatory
Note 3-9
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Name Symbol Buffer
Type Description If Unused
VBUS_UP
43K
49.9K
VBUS_MON_UP
USB7216C
DS00003851A-page 14 2021 Microchip Technology Inc.
Miscellaneous
Programmable
Function Pins
PF[31:3] I/O12 Programmable function pins.
Note 3-6 If unused: depends on the
configured pin function.
Refe r to Se cti o n 3.3.4,
PF[31: 3] Con fi g ur ati o n
(CFG_STRAP[2:1])
Note 3-6
Test 1 TEST1 A Test 1 pin.
This signal is used for test purposes and
must always be pulled-up to 3.3V via a 10
k resistor.
Pull to 3.3V
through a
10 k
resistor
Test 2 TEST2 A Test 2 pin.
This signal is used for test purposes and
must always be pulled-up to 3.3V via a 10
k resistor.
Pull to 3.3V
through a
10 k
resistor
Test 3 TEST3 A Test 3 pin.
This signal is used for test purposes and
must always be pulled-up to 3.3V via a 10
k resistor.
Pull to 3.3V
through a
10 k
resistor
Reset Input RESET_N IS This active low signal is used by the system
to reset the device.
Mandatory
Note 3-9
Bias Resistor RBIAS I-R A 12.0 k 1.0% resistor is attached from
ground to this pin to set the transceiver’s
internal bias settings. Place the resistor as
close the device as possible with a dedi-
cated, low impedance connection to the
ground plane.
Mandatory
Note 3-9
Test TESTEN I/O12 Test pin.
This signal is used for test purposes and
must always be connected to ground.
Connect to
GND
Analog Test ATEST A Analog test pin.
This signal is used for test purposes and
must always be left unconnected.
Float
External 25 MHz
Crystal Input
XTALI ICLK External 25 MHz crystal input Mandatory
Note 3-9
External 25 MHz
Reference Clock
Input
CLK_IN ICLK External reference clock input.
The device may alternatively be driven by a
single-ended clock oscillator. When this
method is used, XTALO should be left
unconnected.
Mandatory
Note 3-9
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Name Symbol Buffer
Type Description If Unused
PRT DIS P 6:] These configuralio junclion wi‘h the c PRT DIS M 6:! PRT DIS M I These configural junclion wi‘h the PRT DIS P 6:1
2021 Microchip Technology Inc. DS00003851A-page 15
USB7216C
External 25 MHz
Crystal Output
XTALO OCLK External 25 MHz crystal output Float
(only if sin-
gle-ended
clock is
connected
to CLK_IN)
Configuration Straps
Port 6-1 D+
Disable
Configuration
Strap
PRT_DIS_P[6:1] I Port 6-1 D+ Disable Configuration Strap.
These configuration straps are used in con-
junction with the corresponding
PRT_DIS_M[6:1] straps to disable the
related port (6-1). See Note 3-10.
Both USB data pins for the corresponding
port must be tied to 3.3V to disable the
associated downstream port.
N/A
Port 6-1 D-
Disable
Configuration
Strap
PRT_DIS_M[6:1] I Port 6-1 D- Disable Configuration Strap.
These configuration straps are used in con-
junction with the corresponding
PRT_DIS_P[6:1] straps to disable the
related port (6-1). See Note 3-10.
Both USB data pins for the corresponding
port must be tied to 3.3V to disable the
associated downstream port.
Mandatory
Note 3-9
Non-Removable
Ports
Configuration
Strap
CFG_NON_REM I Non-Removable Ports Configuration Strap.
This configuration strap controls the number
of reported non-removable ports. See
Note 3-10 .
Note 3-7 Mandatory if external SPI
memory is not used for
f i r m w a r e e xe c u t i on . I f
external SPI memory is
us e d f o r fi r m w a r e
ex e c u t i o n, t h e n
configuration strap resistor
should be omitted.
Note 3-7
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Name Symbol Buffer
Type Description If Unused
CFG BC EN CFG STRAP 3
USB7216C
DS00003851A-page 16 2021 Microchip Technology Inc.
Note 3-9 Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N
(external chip reset). Configuration straps are identified by an underlined symbol name. Signals that
function as configuration straps must be augmented with an external resistor when connected to a
load. For additional information, refer to Section 3.3, Configuration Straps and Programmable
Functions.
Note 3-10 Pin use is mandatory. Cannot be left unused.
Battery Charging
Configuration
Strap
CFG_BC_EN I/O12 Battery Charging Configuration Strap.
This configuration strap controls the number
of BC 1.2 enabled downstream ports. See
Note 3-10.
Note 3-8 Mandatory if external SPI
memory is not used for
f i r m w a r e e xe c u t i on . I f
external SPI memory is
us e d f o r fi r m w a r e
ex e c u t i o n, t h e n
configuration strap resistor
should be omitted.
Mandatory
Note 3-9
Device Mode
Configuration
Straps 3-1
CFG_STRAP[3:1] I Device Mode Configuration Straps 3-1.
These configuration straps are used to
select the device’s mode of operation. See
Note 3-10.
Mandatory
Note 3-9
Power/Ground
+3.3V I/O Power
Supply Input
VDD33 P +3.3 V power and internal regulator input. Mandatory
Note 3-9
Digital Core
Power Supply
Input
VCORE P Digital core power supply input. Mandatory
Note 3-9
Ground VSS P Common ground.
This exposed pad must be connected to the
ground plane with a via array.
Mandatory
Note 3-9
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Name Symbol Buffer
Type Description If Unused
N (PRT DIS P 6:1 PRT DIS M 6:1 PRT DIS P6:l IPRT DIS M 6:! PRT DIS PX PRT DIS NIX PRT DIS PX PRT DIS Ile (cm REM ngs of me devxce CFC 1\ REM
2021 Microchip Technology Inc. DS00003851A-page 17
USB7216C
3.3 Configuration Straps and Programmable Functions
Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset
(RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following
deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the var-
ious device configuration straps and associated programmable pin functions.
3.3.1 PORT DISABLE CONFIGURATION (PRT_DIS_P[6:1] / PRT_DIS_M[6:1])
The PRT_DIS_P[6:1] / PRT_DIS_M[6:1] configuration straps are used in conjunction to disable the related port (6-1)
For PRT_DIS_Px (where x is the corresponding port 6-1):
0 = Port x D+ Enabled
1 = Port x D+ Disabled
For PRT_DIS_Mx (where x is the corresponding port 6-1):
0 = Port x D- Enabled
1 = Port x D- Disabled
3.3.2 NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM)
The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of
six settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The
resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down, and 10 Ω pull-
up, as shown in Table 3-2.
Note: The system designer must guarantee that configuration straps meet the timing requirements specified in
Section 9.6.2, Power-On and Configuration Strap Timing and Section 9.6.3, Reset and Configuration Strap
Timing. If configuration straps are not at the correct voltage level prior to being latched, the device may
capture incorrect strap values.
Note: Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable
the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.0
port.
N (cm BC EN CFG NON REM CFG NON REM CFG BC EN \ngs loe de CFC BC EN CFG BC EN CFG BC EN (cm STRAP 2:1 The USB72160 provxdes 29 programm figuraxion via the CFG STRAP 2:1 CFG STRAP 2:1 CFG STRAP} Q I CFG STRAPZ CFG STRAPI
USB7216C
DS00003851A-page 18 2021 Microchip Technology Inc.
3.3.3 BATTERY CHARGING CONFIGURATION (CFG_BC_EN)
The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of six
settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor
options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down, and 10 Ω pull-up, as
shown in Table 3-3.
3.3.4 PF[31:3] CONFIGURATION (CFG_STRAP[2:1])
The USB7216C provides 29 programmable function pins (PF[31:3]). These pins can be configured to 2 predefined con-
figuration via the CFG_STRAP[2:1] pins. These configurations are selected via external resistors on the
CFG_STRAP[2:1] pins, as detailed in Table 3-4. Resistor values and combinations not detailed in Table 3-4 are reserved
and should not be used.
A summary of the configuration pin assignments for each of the 2 configurations is provided in Table 3-5. For details on
behavior of each programmable function, refer to Table 3-6.
TABLE 3-2: CFG_NON_REM RESISTOR ENCODING
CFG_NON_REM Resistor Value Setting
200 kΩ Pull-Down All ports removable
200 kΩ Pull-Up Port 1 non-removable
10 kΩ Pull-Down Ports 1, 2 non-removable
10 kΩ Pull-Up Ports 1, 2, 3 non-removable
10 Ω Pull-Down Ports 1, 2, 3, 4 non-removable
10 Ω Pull-Up Ports 1, 2, 3, 4, 5, 6 non-removable
TABLE 3-3: CFG_BC_EN RESISTOR ENCODING
CFG_BC_EN Resistor Value Setting
200 kΩ Pull-Down Battery charging not enable on any port
200 kΩ Pull-Up BC1.2 DCP and CDP battery charging enabled on Port 1
10 kΩ Pull-Down BC1.2 DCP and CDP battery charging enabled on Ports 1, 2
10 kΩ Pull-Up BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3
10 Ω Pull-Down BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3, 4
10 Ω Pull-Up BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3, 4, 5, 6
Note: CFG_STRAP3 is not used and must be pulled-down to ground via a 200 k resistor.
TABLE 3-4: CFG_STRAP[2:1] RESISTOR ENCODING
Mode CFG_STRAP2
Resistor Value
CFG_STRAP1
Resistor Value
Configuration 1 200 kΩ Pull-Down 200 kΩ Pull-Down
Configuration 2 200 kΩ Pull-Down 200 kΩ Pull-Up
TABLE 3-5: PF[31:3] FUNCTION ASSIGNMENT
Pin Configuration 1
(SMBus/I2C)
Configuration 2
(I2S)
PF3 DP1_VCONN2 DP1_VCONN2
PF4 DP1_VCONN1 DP1_VCONN1
PF5 DP1_DISCHARGE DP1_DISCHARGE
PF6 GPIO70 GPIO70
2021 Microchip Technology Inc. DS00003851A-page 19
USB7216C
Note 3-1 The default function is not used in the USB7216C.
PF7 GPIO71 MIC_DET
PF8 GPIO72 GPIO72
PF9 GPIO73 GPIO73
PF10 PRT_CTL2_U3 I2S_SDI
PF11 PRT_CTL3_U3 I2S_MCLK
PF12 PRT_CTL4_U3 PRT_CTL4_U3
PF13 PRT_CTL4 PRT_CTL4
PF14 PRT_CTL3 PRT_CTL3
PF15 PRT_CTL2 PRT_CTL2
PF16 PRT_CTL5 PRT_CTL5
PF17 PRT_CTL1 PRT_CTL1
PF18 ALERT0 ALERT0
PF19 - I2S_SDO
PF20 SPI_CE_N SPI_CE_N
PF21 SPI_CLK SPI_CLK
PF22 SPI_D0 SPI_D0
PF23 SPI_D1 SPI_D1
PF24 SPI_D2 SPI_D2
PF25 SPI_D3 SPI_D3
PF26 SLV_I2C_CLK I2S_SCK
PF27 SLV_I2C_DATA PRT_CTL6
PF28 PRT_CTL6 I2S_LRCK
PF29 (Note 3-1) (Note 3-1)
PF30 MSTR_I2C_CLK MSTR_I2C_CLK
PF31 MSTR_I2C_DATA MSTR_I2C_DATA
Note: The default PFx pin functions can be overridden with additional configuration by modification of the pin mux
registers. These changes can be made during the SMBus configuration stage, by programming to OTP
memory, or during runtime (after hub has attached and enumerated) by register writes via the SMBus slave
interface or USB commands to the internal Hub Feature Controller Device.
TABLE 3-5: PF[31:3] FUNCTION ASSIGNMENT (CONTINUED)
Pin Configuration 1
(SMBus/I2C)
Configuration 2
(I2S)
USB7216C
DS00003851A-page 20 2021 Microchip Technology Inc.
TABLE 3-6: PROGRAMMABLE FUNCTIONS DESCRIPTIONS
Function Buffer
Type Description If Unused
Master SMBus/I2C Interface
MSTR_I2C_CLK I/O12 Bridging Master SMBus/I2C controller clock (SMBus/I2C controller
1). External 1k-10k pull-up resistors to 3.3V are required if the I2C
Master Interface is to be used.
Weak pull-
down to
GND
MSTR_I2C_DATA I/O12 Bridging Master SMBus/I2C controller data (SMBus/I2C controller
1). External 1k-10k pull-up resistors to 3.3V are required if the I2C
Master Interface is to be used.
Weak pull-
down to
GND
Slave SMBus/I2C Interface
SLV_I2C_CLK I/O12 Slave SMBus/I2C controller clock (SMBus/I2C controller 2). Exter-
nal 1k-10k pull-up resistors to 3.3V are required if the I2C Slave
Interface is to be used.
Weak pull-
down to
GND
SLV_I2C_DATA I/O12 Slave SMBus/I2C controller data (SMBus/I2C controller 2). External
1k-10k pull-up resistors to 3.3V are required if the I2C Slave Inter-
face is to be used.
Weak pull-
down to
GND
I2S Interface
I2S_SDI I I2S Serial Data In Weak pull-
down to
GND
I2S_SDO O12 I2S Serial Data Out Weak pull-
down to
GND
I2S_SCK O12 I2S Continuous Serial Clock Weak pull-
down to
GND
I2S_LRCK O12 I2S Word Select / Left-Right Clock Weak pull-
down to
GND
I2S_MCLK O12 I2S Master Clock Weak pull-
down to
GND
MIC_DET I I2S Microphone Plug Detect
0 = No microphone plugged into the audio jack
1 = Microphone plugged into the audio jack
Weak pull-
down to
GND
2021 Microchip Technology Inc. DS00003851A-page 21
USB7216C
Miscellaneous
ALERT0 I Alert 0
Interrupt input for connection to the local companion (UPD360/
UPD350) power delivery controller’s IRQ# signal.
DP1_VCONN1 I/O12 Port 1 VCONN1 enable. Active high signal.
0 = VCONN is turned off.
1 = VCONN is turned on. If DP1_VCONN1 is asserted and >3.0V is
not sensed on the CC1 line, a VCONN fault condition is detected.
Note 3-1 This pin can be left unused only if Port 1 is
disabled or reconfigured to operate as a legacy
Type-A port via OTP/SMBus/SPI configuration.
Weak pull-
down to
GND
(Note 3-1)
DP1_VCONN2 I/O12 Port 1 VCONN2 enable. Active high signal.
0 = VCONN is turned off.
1 = VCONN is turned on. If DP1_VCONN2 is asserted and >3.0V is
not sensed on the CC2 line, a VCONN fault condition is detected.
Note 3-2 This pin can be left unused only if Port 1 is
disabled or reconfigured to operate as a legacy
Type-A port via OTP/SMBus/SPI configuration.
Weak pull-
down to
GND
(Note 3-2)
DP1_DISCHARGE I/O12 Port 1 DISCHARGE enable. Active high signal.
0 = VBUS discharging is not active.
1 = VBUS is being discharged to GND. This pin only asserts for a
short duration when VBUS is being discharged from 5V (vSafe5V)
to 0V (vSafe0V).
Note 3-3 This pin can be left unused only if Port 1 is
disabled or reconfigured to operate as a legacy
Type-A port via OTP/SMBus/SPI configuration.
Weak pull-
down to
GND
(Note 3-3)
PRT_CTL6 I/O12
(PU)
Port 6 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 6.
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note: This signal controls both the USB 2.0 and USB 3.2 por-
tions of the port.
Note 3-4 This pin can be left unused only if Port 6 is
disabled via strap/OTP/SMBus/SPI configuration.
Float
(Note 3-4)
TABLE 3-6: PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)
Function Buffer
Type Description If Unused
USB7216C
DS00003851A-page 22 2021 Microchip Technology Inc.
PRT_CTL5 I/O12
(PU)
Port 5 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 5.
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note: This signal controls both the USB 2.0 and USB 3.2 por-
tions of the port.
Note 3-5 This pin can be left unused only if Port 5 is
disabled via strap/OTP/SMBus/SPI configuration.
Float
(Note 3-5)
PRT_CTL4 I/O12
(PU)
Port 4 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 4.
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note: When PortSplit is disabled, this signal controls both the
USB 2.0 and USB 3.2 portions of the port. When
PortSplit is enabled, this signal controls the USB 2.0
portion of the port only.
Note 3-6 This pin can be left unused only if Port 4 is
disabled via strap/OTP/SMBus/SPI configuration.
Float
(Note 3-6)
PRT_CTL3 I/O12
(PU)
Port 3 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 3.
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note: When PortSplit is disabled, this signal controls both the
USB 2.0 and USB 3.2 portions of the port. When
PortSplit is enabled, this signal controls the USB 2.0
portion of the port only.
Note 3-7 This pin can be left unused only if Port 3 is
disabled via strap/OTP/SMBus/SPI configuration.
Float
(Note 3-7)
TABLE 3-6: PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)
Function Buffer
Type Description If Unused
2021 Microchip Technology Inc. DS00003851A-page 23
USB7216C
PRT_CTL2 I/O12
(PU)
Port 2 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 2.
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note: When PortSplit is disabled, this signal controls both the
USB 2.0 and USB 3.2 portions of the port. When
PortSplit is enabled, this signal controls the USB 2.0
portion of the port only.
Note 3-8 This pin can be left unused only if Port 2 is
disabled via strap/OTP/SMBus/SPI configuration.
Float
(Note 3-4)
PRT_CTL1 I/O12
(PU)
Port 1 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 1.
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note: This signal controls both the USB 2.0 and USB 3.2 por-
tions of the port.
Note 3-9 This pin can be left unused only if Port 1 is
disabled via strap/OTP/SMBus/SPI configuration.
Float
(Note 3-4)
PRT_CTL4_U3 O12 Port 4 USB 3.2 PortSplit power enable
This signal is an active high control signal used to enable to the
USB 3.2 portion of the downstream port 4 when PortSplit is
enabled. When PortSplit is disabled, this pin is not used.
Note: This signal should only be used to control an embedded
USB 3.2 device.
Float
PRT_CTL3_U3 O12 Port 3 USB 3.2 PortSplit power enable
This signal is an active high control signal used to enable to the
USB 3.2 portion of the downstream port 3 when PortSplit is
enabled. When PortSplit is disabled, this pin is not used.
Note: This signal should only be used to control an embedded
USB 3.2 device.
Float
TABLE 3-6: PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)
Function Buffer
Type Description If Unused
USB7216C
DS00003851A-page 24 2021 Microchip Technology Inc.
3.4 Physical and Logical Port Mapping
The USB72xx family of devices are based upon a common architecture, but all have different modifications and/or pin
bond outs to achieve the various device configurations. The base chip is composed of a total of 6 USB3 PHYs and 7
USB2 PHYs. These PHYs are physically arranged on the chip in a certain way, which is referred to as the PHYSICAL
port mapping.
The actual port numbering is remapped by default in different ways on each device in the family. This changes the way
that the ports are numbered from the USB host’s perspective. This is referred to as LOGICAL mapping.
The various configuration options available for these devices may, at times, be with respect to PHYSICAL mapping or
LOGICAL mapping. Each individual configuration option which has a PHYSICAL or LOGICAL dependency is declared
as such within the register description.
The PHYSICAL vs. LOGICAL mapping is described for all port related pins in Table 3-7. A system design in schematics
and layout is generally performed using the pinout in Section 3.1, Pin Assignments, which is assigned by the default
LOGICAL mapping. Hence, it may be necessary to cross reference the PHYSICAL vs. LOGICAL look up tables when
determining the hub configuration.
PRT_CTL2_U3 O12 Port 2 USB 3.2 PortSplit power enable
This signal is an active high control signal used to enable to the
USB 3.2 portion of the downstream port 3 when PortSplit is
enabled. When PortSplit is disabled, this pin is not used.
Note: This signal should only be used to control an embedded
USB 3.2 device.
Float
GPIOxI/O12 General Purpose Input/Output
(x = 70-73)
Weak pull-
down to
GND
Note: The MPLAB Connect tool makes configuration simple; the settings can be selected by the user with respect
to the LOGICAL port numbering. The tool handles the necessary linking to the PHYSICAL port settings.
Refer to Section 6.0, Device Configuration for additional information.
TABLE 3-6: PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)
Function Buffer
Type Description If Unused
2021 Microchip Technology Inc. DS00003851A-page 25
USB7216C
TABLE 3-7: USB7216C PHYSICAL VS. LOGICAL PORT MAPPING
Device
Pin Pin Name (as in datasheet)
LOGICAL PORT NUMBER PHYSICAL PORT NUMBER
01234560123456
5 USB2DN_DP1 X X
6 USB2DN_DM1 X X
7 USB3DN_TXDP1A X X
8 USB3DN_TXDM1A X X
10 USB3DN_RXDP1A X X
11 USB3DN_RXDM1A X X
14 USB2DN_DP5 X X
15 USB2DN_DM5 X X
16 USB3DN_TXDP1B X X
17 USB3DN_TXDM1B X X
19 USB3DN_RXDP1B X X
20 USB3DN_RXDM1B X X
27 USB2DN_DP2 X X
28 USB2DN_DM2 X X
29 USB3DN_TXDP2 X X
30 USB3DN_TXDM2 X X
32 USB3DN_RXDP2 X X
33 USB3DN_RXDM2 X X
34 USB2DN_DP3 X X
35 USB2DN_DM3 X X
36 USB3DN_TXDP3 X X
37 USB3DN_TXDM3 X X
39 USB3DN_RXDP3 X X
40 USB3DN_RXDM3 X X
41 USB2DN_DM6 X X
42 USB2DN_DP6 X X
81 USB2DN_DP4 X X
82 USB2DN_DM4 X X
83 USB3DN_TXDP4 X X
84 USB3DN_TXDM4 X X
86 USB3DN_RXDP4 X X
87 USB3DN_RXDM4 X X
89 USB2UP_DP X X
90 USB2UP_DM X X
91 USB3UP_TXDP X X
92 USB3UP_TXDM X X
94 USB3UP_RXDP X X
95 USB3UP_RXDM X X
"Mm MM»; «H H %
USB7216C
DS00003851A-page 26 2021 Microchip Technology Inc.
4.0 DEVICE CONNECTIONS
4.1 Power Connections
Figure 4-1 illustrates the device power connections.
4.2 SPI Flash Connections
Figure 4-2 illustrates the Quad-SPI flash connections.
FIGURE 4-1: POWER CONNECTIONS
FIGURE 4-2: QUAD-SPI FLASH CONNECTIONS
+3.3V
Supply
USB7216C
3.3V Internal Logic
VDD33
(x8)
VSS
(exposed pad)
Digital Core
Internal Logic
VCORE
(x9)
VCORE
Supply
+3.3V
0.1uF
0.001uF
x8
+3.3V
4.7uF
VCORE
0.1uF
0.001uF
x9
VCORE
4.7uF
2021 Microchip Technology Inc. DS00003851A-page 27
USB7216C
4.3 SMBus/I2C Connections
Figure 4-3 illustrates the SMBus/I2C connections.
4.4 I2S Connections
Figure 4-4 illustrates the I2S connections.
FIGURE 4-3: SMBUS/I2C CONNECTIONS
FIGURE 4-4: I2S CONNECTIONS
Configuran'on 17 I®
USB7216C
DS00003851A-page 28 2021 Microchip Technology Inc.
5.0 MODES OF OPERATION
The device provides two main modes of operation: Standby Mode and Hub Mode. These modes are controlled via the
RESET_N pin, as shown in Table 5-1.
The flowchart in Figure 5-1 details the modes of operation and details how the device traverses through the Hub Mode
stages (shown in bold). The remaining sub-sections provide more detail on each stage of operation.
TABLE 5-1: MODES OF OPERATION
RESET_N Input Summary
0 Standby Mode: This is the lowest power mode of the device. No functions are active
other than monitoring the RESET_N input. All port interfaces are high impedance and
the PLL is halted. Refer to Section 8.11, Resets for additional information on RESET_N.
1 Hub (Normal) Mode: The device operates as a configurable USB hub. This mode has
various sub-modes of operation, as detailed in Figure 5-1. Power consumption is based
on the number of active ports, their speed, and amount of data received.
FIGURE 5-1: HUB MODE FLOWCHART
Combine OTP
Config Data
In SPI Mode
& Ext. SPI ROM
present?
YES
NO
Run From
External SPI ROM
(SPI_INIT)
SMBus Slave Pull-ups?
RESET_N deasserted
Modify Config
Based on Config
Straps
(CFG_ROM)
Load Config from
Internal ROM
YES
NO
(SMBUS_CHECK)
Perform SMBus/I2C
Initialization
SOC Done?
YES
NO
(CFG_SMBUS)
(CFG_OTP)
Hub Connect
(USB_ATTACH)
Normal Operation
(NORMAL_MODE)
(CFG_STRAP)
Configuration 1?
YES
NO
CFC STRAP 3:1 PRT DIS P 6:1 PRT DIS M 6:] CFC N0 RE I CFC BC EN CFC STRAP 3:]
2021 Microchip Technology Inc. DS00003851A-page 29
USB7216C
5.1 Boot Sequence
5.1.1 STANDBY MODE
If the RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maxi-
mum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream
ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no
states saved), all internal registers return to their default state, the PLL is halted, and core logic is powered down in order
to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode
and must be re-initialized after RESET_N is negated high.
5.1.2 SPI INITIALIZATION STAGE (SPI_INIT)
The first stage, the initialization stage, occurs on the deassertion of RESET_N. In this stage, the internal logic is reset,
the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal
firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid
signature of “2DFU” (device firmware upgrade) beginning at address 0x3FFFA. If a valid signature is found, then the
external SPI ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid
signature is not found, then execution continues from internal ROM (CFG_ROM stage).
The required SPI ROM must be a minimum of 1 Mbit, and 60 MHz or faster. Both 1, 2, and 4-bit SPI operation is sup-
ported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMs are also sup-
ported.
If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_ROM stage).
5.1.3 CONFIGURATION FROM INTERNAL ROM STAGE (CFG_ROM)
In this stage, the internal firmware loads the default values from the internal ROM. Most of the hub configuration regis-
ters, USB descriptors, electrical settings, etc. will be initialized in this state.
5.1.4 CONFIGURATION STRAP READ STAGE (CFG_STRAP)
In this stage, the firmware reads the following configuration straps to override the default values:
•CFG_STRAP[3:1]
•PRT_DIS_P[6:1]
•PRT_DIS_M[6:1]
•CFG_NON_REM
•CFG_BC_EN
If the CFG_STRAP[3:1] pins are set to Configuration 1, the device will move to the SMBUS_CHECK stage, otherwise
it will move to the CFG_OTP stage. Refer to Section 3.3, Configuration Straps and Programmable Functions for infor-
mation on usage of the various device configuration straps.
5.1.5 SMBUS CHECK STAGE (SMBUS_CHECK)
Based on the PF[31:3] configuration selected (refer to Section 3.3.4, PF[31:3] Configuration (CFG_STRAP[2:1])), the
firmware will check for the presence of external pull up resistors on the SMBus slave programmable function pins. If 10K
pull-ups are detected on both pins, the device will be configured as an SMBus slave, and the next state will be CFG_SM-
BUS. If a pull-up is not detected in either of the pins, the next state is CFG_OTP.
5.1.6 SMBUS CONFIGURATION STAGE (CFG_SMBUS)
In this stage, the external SMBus master can modify any of the default configuration settings specified in the integrated
ROM, such as USB device descriptors, port electrical settings, and control features such as downstream battery
charging.
There is no time limit on this mode. In this stage the firmware will wait indefinitely for the SMBus/I2C configuration. The
external SMBus master writes to register 0xFF to end the configuration in legacy mode. In non-legacy mode, the SMBus
command USB_ATTACH (opcode 0xAA55) or USB_ATTACH_WITH_SMBUS (opcode 0xAA56) will finish the configu-
ration.
USB7216C
DS00003851A-page 30 2021 Microchip Technology Inc.
5.1.7 OTP CONFIGURATION STAGE (CFG_OTP)
Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The
default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is pro-
grammed.
5.1.8 HUB CONNECT STAGE (USB_ATTACH)
Once the hub registers are updated through default values, SMBus master, and OTP, the device firmware will enable
attaching the USB host by setting the USB_ATTACH bit in the HUB_CMD_STAT register (for USB 2.0) and the
USB3_HUB_ENABLE bit (for USB 3.2). The device will remain in the Hub Connect stage indefinitely.
5.1.9 NORMAL MODE (NORMAL_MODE)
Lastly, the hub enters Normal Mode of operation. In this stage full USB operation is supported under control of the USB
Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the sys-
tem.
If RESET_N is asserted low, then Standby Mode is entered. The device may then be placed into any of the designated
hub stages. Asserting a soft disconnect on the upstream port will cause the hub to return to the Hub Connect stage until
the soft disconnect is negated.
Note: If the same register is modified in both CFG_SMBUS and CFG_OTP stages, the value from CFG_OTP will
overwrite any value written during CFG_SMBUS.
2021 Microchip Technology Inc. DS00003851A-page 31
USB7216C
6.0 DEVICE CONFIGURATION
The device supports a large number of features (some mutually exclusive), and must be configured in order to correctly
function when attached to a USB host controller. Microchip provides a comprehensive software programming tool,
MPLAB Connect Configurator (formerly ProTouch2), for OTP configuration of various USB7216C functions and regis-
ters. All configuration is to be performed via the MPLAB Connect Configurator programming tool. For additional infor-
mation on this tool, refer to the MPLAB Connect Configurator programming tool product page at http://
www.microchip.com/design-centers/usb/mplab-connect-configurator.
Additional information on configuring the USB7216C is also provided in the “Configuration of the USB720x/USB725x”
application note, which contains details on the hub operational mode, SOC configuration stage, OTP configuration, USB
configuration, and configuration register definitions. This application note, along with additional USB7216C resources,
can be found on the Microchip USB7216C product page at www.microchip.com/USB7216.
Note: The USB7216C requires external firmware to operate. Functions such as Power Delivery will not operate
without external firmware. Refer to the “Configuration of the USB7202/USB725x” application note for addi-
tional information.
Note: Device configuration straps and programmable pins are detailed in Section 3.3, Configuration Straps and
Programmable Functions.
Refer to Section 7.0, Device Interfaces for detailed information on each device interface.
USB7216C
DS00003851A-page 32 2021 Microchip Technology Inc.
7.0 DEVICE INTERFACES
The USB7216C provides multiple interfaces for configuration, external memory access, etc.. This section details the
various device interfaces:
•SPI/SQI Master Interface
•SMBus/I2C Master/Slave Interfaces
•I2S Interface
7.1 SPI/SQI Master Interface
The SPI/SQI controller has two basic modes of operation: execution of an external hub firmware image, or the USB to
SPI bridge. On power up, the firmware looks for an external SPI flash device that contains a valid signature of 2DFU
(device firmware upgrade) beginning at address 0x3FFFA. If a valid signature is found, then the external ROM mode is
enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found,
then execution continues from internal ROM and the SPI interface can be used as a USB to SPI bridge.
The entire firmware image is then executed in place entirely from the SPI interface. The SPI interface will remain con-
tinuously active while the hub is in the runtime state. The hub configuration options are also loaded entirely out of the
SPI memory device. Both the internal ROM firmware image and internal OTP memory are completely ignored while exe-
cuting the firmware and configuration from the external SPI memory.
The second mode of operation is the USB to SPI bridge operation. Additional details on this feature can be found in
Section 8.9, USB to SPI Bridging.
Table 7-1 details how the associated pins are mapped in SPI vs. SQI mode
Note: For details on how to enable each interface, refer to Section 3.3, Configuration Straps and Programmable
Functions.
For information on device connections, refer to Section 4.0, Device Connections. For information on device
configuration, refer to Section 6.0, Device Configuration.
Microchip provides a comprehensive software programming tool, MPLAB Connect Configurator (formerly
ProTouch2), for configuring the USB7216C functions, registers and OTP memory. All configuration is to be
performed via the MPLAB Connect Configurator programming tool. For additional information on this tool,
refer to th MPLAB Connect Configurator programming tool product page at http://www.microchip.com/
design-centers/usb/mplab-connect-configurator.
TABLE 7-1: SPI/SQI PIN USAGE
SPI Mode SQI Mode Description
SPI_CE_N SQI_CE_N SPI/SQI Chip Enable (Active Low)
SPI_CLK SQI_CLK SPI/SQI Clock
SPI_D0 SQI_D0 SPI Data Out; SQI Data I/O 0
SPI_D1 SQI_D1 SPI Data In; SQI Data I/O 1
-SQI_D2 SQI Data I/O 2
-SQI_D3 SQI Data I/O 3
Note: For SPI/SQI master timing information, refer to Section 9.6.10, SPI/SQI Master Timing.
n2
2021 Microchip Technology Inc. DS00003851A-page 33
USB7216C
7.2 SMBus/I2C Master/Slave Interfaces
The device provides three independent SMBus/I2C controllers (Slave, Master, and Power Delivery Master) which can
be used to access internal device run time registers or program the internal OTP memory. The device contains two 128
byte buffers to enable simultaneous master/slave operation and to minimize firmware overhead in processed I2C pack-
ets. The I2C interfaces support 100KHz Standard-mode (Sm) and 400KHz Fast Mode (Fm) operation.
The SMBus/I2C interfaces are assigned to programmable pins (PFx) and therefore the device must be programmed into
specific configurations to enable specific interfaces. Refer to Section 3.3.4, PF[31:3] Configuration (CFG_STRAP[2:1])
for additional information.
7.3 I2S Interface
The device provides an integrated I2S interface to facilitate the connection of digital audio devices. The I2S interface
conforms to the voltage, power, and timing characteristics/specifications as set forth in the I2S-Bus Specification, and
consists of the following signals:
•I2S_SDI: Serial Data Input
•I2S_SDO: Serial Data Output
•I2S_SCK: Serial Clock
•I2S_LRCK: Left/Right Clock (SS/FSYNC)
•I2S_MCLK: Master Clock
•MIC_DET: Microphone Plug Detect
Each audio connection is half-duplex, so I2S_SDO exists only on the transmit side and I2S_SDI exists only on the
receive side of the interface. Some codecs refer to the Serial Clock (I2S_SCK) as Baud/Bit Clock (BCLK). Also, the Left/
Right Clock is commonly referred to as LRC or LRCK. The I2S and other audio protocols refer to LRC as Word Select
(WS).
The following codec is supported by default:
• Analog Devices ADAU1961 (24-bit 96KHz)
The I2S interface is assigned to programmable pins (PFx) and therefore the device must be programmed into specific
configurations to enable the interface. Refer to Section 3.3.4, PF[31:3] Configuration (CFG_STRAP[2:1]) for additional
information.
7.3.1 MODES OF OPERATION
The USB audio class operates in three ways: Asynchronous, Synchronous and Adaptive. There are also multiple oper-
ating modes, such as hi-res, streaming, etc.. Typically for USB devices, inputs such as microphones are Asynchronous,
and output devices such as speakers are Adaptive. The hardware is set up to handle all three modes of operation. It is
recommended that the following configuration be used: Asynchronous IN; Adaptive OUT; 48Khz streaming mode; Two
channels: 16 bits per channel.
7.3.1.1 Asynchronous IN 48KHz Streaming
In this mode, the codec sampling clock is set to 48Khz based on the local oscillator. This clock is never changed. The
data from the codec is fed into the input FIFO. Since the sampling clock is asynchronous to the host clock, the amount
of data captured in every USB frame will vary. This issue is left for the host to handle. The input FIFO has two markers,
a low water mark (THRESHOLD_LOW_VAL), and a high water mark (THRESHOLD_HIGH_VAL). There are three reg-
isters to determine how much data to send back in each frame. If the amount of data in the FIFO exceeds the high water
mark, then HI_PKT_SIZE worth of data is sent. If the data is between the high and low water mark, the normal MID_P-
KT_SIZE amount of data is sent. If the data is below the low water mark, LO_PKT_SIZE worth of data is sent.
Note: For SMBus/I2C timing information, refer to Section 9.6.7, SMBus Timing and Section 9.6.8, I2C Timing.
Note: For I2S timing information, refer to Section 9.6.9, I2S Timing. For detailed information on utilizing the I2S
interface, including support for other codecs, refer to the application note “USB720x/USB725x I2S Opera-
tion”, which can be found on the Microchip USB7216C product page at www.microchip.com/USB7216C.
USB7216C
DS00003851A-page 34 2021 Microchip Technology Inc.
7.3.1.2 Adaptive OUT 48KHz Streaming
In this mode, the codec sampling clock is initially set to 48Khz based on the local oscillator. The host data is fed into the
OUT FIFO. The host will send the same amount of data on every frame, i.e. 48KHz of data based on the host clock. The
codec sampling clock is asynchronous to the host clock. This will cause the amount of data in the OUT FIFO to vary. If
the amount of data in the FIFO exceeds the high water mark, then the sampling clock is increased. If the data is between
the high and low water mark, the sampling clock does not change. If the data is below the low water mark, the sampling
clock is decreased.
7.3.1.3 Synchronous Operation
For synchronous operation, the internal clock must be synchronized with the host SOF. The Frame SOF is nominally
1mS. Since there is significant jitter in the SOFs, there is circuitry provided to measure the SOFs over a long period of
time to get a more accurate reading. The calculated host frequency is used to calculate the codec sampling clock.
PRT7CT L):
2021 Microchip Technology Inc. DS00003851A-page 35
USB7216C
8.0 FUNCTIONAL DESCRIPTIONS
This section details various USB7216C functions, including:
•Downstream Battery Charging
•Port Power Control
•CC Pin Orientation and Detection
•PortSplit
•FlexConnect
•Multi-Host Endpoint Reflector
•USB to GPIO Bridging
•USB to I2C Bridging
•USB to SPI Bridging
•Link Power Management (LPM)
•Resets
8.1 Downstream Battery Charging
The device can be configured by an OEM to have any of the downstream ports support battery charging. The hub’s role
in battery charging is to provide acknowledgment to a device’s query as to whether the hub system supports USB battery
charging. The hub silicon does not provide any current or power FETs or any additional circuitry to actually charge the
device. Those components must be provided externally by the OEM.
If the OEM provides an external supply capable of supplying current per the battery charging specification, the hub can
be configured to indicate the presence of such a supply from the device. This indication, via the PRT_CTLx pins, is on
a per port basis. For example, the OEM can configure two ports to support battery charging through high current power
FETs and leave the other two ports as standard USB ports.
The port control signals are assigned to programmable pins (PFx) and therefore the device must be programmed into
specific configurations to enable the signals. Refer to Section 3.3.4, PF[31:3] Configuration (CFG_STRAP[2:1]) for addi-
tional information.
For detailed information on utilizing the battery charging feature, refer to the application note “USB Battery Charging
with Microchip USB720x and USB725x Hubs”, which can be found on the Microchip USB7216C product page
www.microchip.com/USB7216C.
FIGURE 8-1: BATTERY CHARGING EXTERNAL POWER SUPPLY
SOC
VBUS[n]
INT
SCL
SDA
Microchip
Hub
DC Power
m I
USB7216C
DS00003851A-page 36 2021 Microchip Technology Inc.
8.2 Port Power Control
Port power and over-current sense share the same pin (PRT_CTLx) for each port. These functions can be controlled
directly from the USB hub, or via the processor.
8.2.1 PORT POWER CONTROL USING USB POWER SWITCH
When operating in combined mode, the device will have one port power control and over-current sense pin for each
downstream port. When disabling port power, the driver will actively drive a '0'. To avoid unnecessary power dissipation,
the pull-up resistor will be disabled at that time. When port power is enabled, it will disable the output driver and enable
the pull-up resistor, making it an open drain output. If there is an over-current situation, the USB Power Switch will assert
the open drain OCS signal. The Schmidt trigger input will recognize that as a low. The open drain output does not inter-
fere. The over-current sense filter handles the transient conditions such as low voltage while the device is powering up.
Note: The PRT_CTLx function is assigned to programmable function pins (PFx) via configuration straps. Refer
to Section 3.3.4, PF[31:3] Configuration (CFG_STRAP[2:1]) for additional information.
Note: The port power control for the USB 2.0 and USB 3.2 portions of a specific port can also be individually con-
trolled via the PortSplit function. Refer to Section 8.4, PortSplit for additional information.
Note: An external power switch is the required implementation for Type-C ports due to the requirement that VBUS
on Type-C ports must be discharged to 0V when no device is attached to the port.
FIGURE 8-2: PORT POWER CONTROL WITH USB POWER SWITCH
USB Power
Switch
50k
PRTPWR
EN
OCS
OCS
Pull‐UpEnable
5V
USB
Device
FILTER
PRT_CTLx
EA
2021 Microchip Technology Inc. DS00003851A-page 37
USB7216C
8.2.2 PORT POWER CONTROL USING POLY FUSE
When using the device with a poly fuse, there is no need for an output power control. A single port power control and
over-current sense for each downstream port is still used from the Hub's perspective. When disabling port power, the
driver will actively drive a '0'. This will have no effect as the external diode will isolate pin from the load. When port power
is enabled, it will disable the output driver and enable the pull-up resistor. This means that the pull-up resistor is providing
3.3 volts to the anode of the diode. If there is an over-current situation, the poly fuse will open. This will cause the cath-
ode of the diode to go to 0 volts. The anode of the diode will be at 0.7 volts, and the Schmidt trigger input will register
this as a low resulting in an over-current detection. The open drain output does not interfere.
8.3 CC Pin Orientation and Detection
The device provides CC1 and CC2 pins on all Type-C ports for cable plug orientation and detection of a USB Type-C
receptacle. The device also integrates a comparator and DAC circuit to implement Type-C attach and detach functions,
which supports up to eight programmable thresholds for attach detection between a UFP and DFP. When operating as
a UFP, the device supports detecting changes in the DFP’s advertised thresholds.
When operating as a DFP, the device implements current sources to advertise current charging capabilities on both CC
pins. By default, the CC pins advertise a 3A VBUS sourcing capability when operating in DFP mode. This may be recon-
figured to 1.5A or Default USB (500mA for USB2 DFP or 900mA for a USB3 DFP) via OTP, SMBus, or SPI configuration.
When a UFP connection is established, the current driven across the CC pins creates a voltage across the UFP’s Rd
pull-down that can be detected by the integrated CC comparator. When connected to an active cable, an alternative
pull-down, Ra, appears on the CC pin.
When operating as a UFP, the device applies an Rd pull-down on both CC lines and waits for a DFP connection from
the assertion of VBUS. The CC comparator is used to determine the advertised current charger capabilities supported
by the DFP.
VCONN is a 3V-5V supply used to power circuitry in the USB Type-C plug that is required to implement Electronically
Marked Cables and other VCONN Powered accessories. By default the DFP always sources VCONN when connected
to an active cable. The USB7216C requires the use of two external VCONN FETs. The device provides the enables for
these FETs, and can detect an over-current event (OCS) by monitoring the output voltage of the FET via the CC pins.
Note: Type-C ports may not utilize a Poly-Fuse port power implementation due to the requirements that VBUS
on Type-C ports must be discharged to 0V when no device is attached to the port.
FIGURE 8-3: PORT POWER CONTROL USING A POLY FUSE
PRT_CTLx
50k
PRTPWR
OCS
USB
Device
Pull-Up Enable
5V
Poly Fuse
FILTER
USB7216C
DS00003851A-page 38 2021 Microchip Technology Inc.
If the voltage on the VCONN line is sensed as <3.0V by the CC comparator of the either CC1 or CC2 (whichever pin is
operating as VCONN at the time) then an over-current event is detected and the VCONN supply is shut off. VCONN is
only sourced on either the CC1 or the CC2 pin, never both. The pin which is to become the VCONN supply is determined
only when a device is attached to the Type-C port. The VCONN supply is controlled from the hub DP1_VCONN1/
DP1_VCONN2/DP2_VCONN2/DP2_VCONN2.
The device also implements a comparator for determining when a VBUS is within a programmed range, vSafe5V or
vSafe0V. VBUS is divided down externally to provide a nominal 2.68V at the VBUS_MON pin. For a DFP, the VBUS
comparator is useful to detect when VBUS is within the required range per power delivery negotiations. For a UFP, the
VBUS comparator is utilized to determine when a DFP is attached or detached. It may also use the comparator to deter-
mine when VBUS is within a new voltage range per power delivery negotiations.
8.4 PortSplit
The PortSplit feature allows the USB 2.0 and USB 3.2 PHYs associated with a downstream port to be operationally sep-
arated. The intention of this feature is to allow a system designer to connect an embedded USB 3.x device to the USB
3.2 PHY, while allowing the USB 2.0 PHY to be used as either a standard USB 2.0 port or with a separate embedded
USB 2.0 device. PortSplit can be configured via OTP/SMBus. By default, all ports are configured to non-split mode.
PortSplit is supported for ports 2, 3, and 4 in configuration 1 and only for port 4 in configuration 2 (refer to Table 3-5).
When PortSplit is disabled on a specific port, the corresponding PRT_CTLx pin controls both the USB 2.0 and USB 3.2
portions of the port (port power and overcurrent condition). When PortSplit is enabled on a specific port, the corre-
sponding PRT_CTLx pin controls the USB 2.0 portion of the port, and the corresponding PRT_CTLx_U3 pin controls
the USB 3.2 portion of the port.
8.5 FlexConnect
The device allows the upstream port to be swapped with any downstream port, enabling any USB port to assume the
role of USB host at any time during hub operation. This host role exchange feature is called FlexConnect. Additionally,
the USB 2.0 ports can be flexed independently of the USB 3.2 ports.
This functionality can be used in two primary ways:
1. Host Swapping: This functionality can be achieved through a hub wherein a host and device can agree to swap
the host/device relationship; The host becomes a device, and the device becomes a host.
2. Host Sharing: A USB ecosystem can be shared between multiple hosts. Note that only 1 host may access to
the USB tree at a time.
FlexConnect can be enabled through any of the following three methods:
•I2C Control: The embedded I2C slave can be used to control the state of the FlexConnect feature through basic
write/read operations.
•USB Command: FlexConnect can be initiated via a special USB command directed to the hub’s internal Hub
Feature Controller device.
•Direct Pin Control: Any available GPIO pin on the hub can be assigned the role of a FlexConnect control pin.
For detailed information on utilizing the FlexConnect feature, refer to the application note “USB720x/USB725x FlexCon-
nect Operation”, which can be found on the Microchip USB7216C product page at www.microchip.com/USB7216C.
Note: The native USB Type-C functionality (including CC pin orientation and detection features) is managed
autonomously by the USB7216C.
Note: Direct Pin Control is only available in certain configurations. Refer to Section 3.3.4, PF[31:3] Configuration
(CFG_STRAP[2:1]) for additional information.
2021 Microchip Technology Inc. DS00003851A-page 39
USB7216C
8.6 Multi-Host Endpoint Reflector
The internal Multi-Host Endpoint Reflector allows for smart-phone automotive mode sessions to be entered on the
downstream ports. The device supports the Multi-Host Endpoint Reflector on downstream ports.
The Multi-Host Endpoint Reflector uses standard Network Control Model (NCM v1.0) device protocol, which is a sub-
class of Communication Device Class (CDC) group of protocols. Standard NCM USB drivers may be utilized; No custom
drivers are required.
A Multi-Host Endpoint Reflector session may be entered on only 1 downstream port at a time. Entry into Multi-Host mode
is initiated via a no data Control USB transfer addressed to the internal Hub Feature Controller device in the hub.
The USB7216C has two internal USB devices. The Multi-Host Endpoint Reflector is a Composite iAP and NCM device.
The Hub Feature Controller is a Generic USB Device Class device which enables the USB bridging functions.
The hub ports which are connected to both the Multi-Host Endpoint Reflector and Hub Feature Controller are both con-
figured as non-removable.
For detailed information on utilizing the multi-host endpoint reflector feature, refer to the application note “USB7202/
USB725x Multi-Host Endpoint Reflector Operation”, which can be found on the Microchip USB7216C product page at
www.microchip.com/USB7216C.
8.7 USB to GPIO Bridging
The USB to GPIO bridging feature provides system designers expanded system control and potential BOM reduction.
General Purpose Input/Outputs (GPIOs) may be used for any general 3.3V level digital control and input functions.
Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-
form the following functions:
• Set the direction of the GPIO (input or output)
• Enable a pull-up resistor
• Enable a pull-down resistor
• Read the state
• Set the state
For detailed information on utilizing the USB to GPIO bridging feature, refer to the application note “USB to GPIO Bridg-
ing with Microchip USB720x and USB725x Hubs”, which can be found on the Microchip USB7216C product page at
www.microchip.com/USB7216C.
8.8 USB to I2C Bridging
The USB to I2C bridging feature provides system designers expanded system control and potential BOM reduction. The
use of a separate USB to I2C device is no longer required and a downstream USB port is not lost, as occurs when a
standalone USB to I2C device is implemented.
Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-
form the following functions:
• Configure I2C Pass-Through Interface
• I2C Write
• I2C Read
For detailed information on utilizing the USB to I2C bridging feature, refer to the application note “USB to I2C Bridging
with Microchip USB720x and USB725x Hubs”, which can be found on the Microchip USB7216C product page at
www.microchip.com/USB7216C.
8.9 USB to SPI Bridging
The USB to SPI bridging feature provides system designers expanded system control and potential BOM reduction. The
use of a separate USB to SPI device is no longer required and a downstream USB port is not lost, as occurs when a
standalone USB to SPI device is implemented.
Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-
form the following functions:
• Enable SPI Pass-Through Interface
• SPI Write/Read
USB7216C
DS00003851A-page 40 2021 Microchip Technology Inc.
• Disable SPI Pass-Through Interface
For detailed information on utilizing the USB to SPI bridging feature, refer to the application note “USB to SPI Bridging
with Microchip USB720x and USB725x Hubs”, which can be found on the Microchip USB7216C product page at
www.microchip.com/USB7216C.
8.10 Link Power Management (LPM)
The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM
states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB
suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8-1.
8.11 Resets
The device includes the following chip-level reset sources:
•Power-On Reset (POR)
•External Chip Reset (RESET_N)
•USB Bus Reset
8.11.1 POWER-ON RESET (POR)
A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the
device. A timer within the device will assert the internal reset per the specifications listed in Section 9.6.2, Power-On
and Configuration Strap Timing.
8.11.2 EXTERNAL CHIP RESET (RESET_N)
A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within operating range, per the
specifications in Section 9.6.3, Reset and Configuration Strap Timing. While reset is asserted, the device (and its asso-
ciated external circuitry) enters Standby Mode and consumes minimal current.
Assertion of RESET_N causes the following:
1. The PHY is disabled and the differential pairs will be in a high-impedance state.
2. All transactions immediately terminate; no states are saved.
3. All internal registers return to the default state.
4. The external crystal oscillator is halted.
5. The PLL is halted.
TABLE 8-1: LPM STATE DEFINITIONS
State Description Entry/Exit Time to L0
L2 Suspend Entry: ~3 ms
Exit: ~2 ms (from start of RESUME)
L1 Sleep Entry: <10 us
Exit: <50 us
L0 Fully Enabled (On) -
Note: All power supplies must have reached the operating levels mandated in Section 9.2, Operating Condi-
tions**, prior to (or coincident with) the assertion of RESET_N.
2021 Microchip Technology Inc. DS00003851A-page 41
USB7216C
8.11.3 USB BUS RESET
In response to the upstream port signaling a reset to the device, the device performs the following:
1. Sets default address to 0.
2. Sets configuration to Unconfigured.
3. Moves device from suspended to active (if suspended).
4. Complies with the USB Specification for behavior after completion of a reset sequence.
The host then configures the device in accordance with the USB Specification.
Note: The device does not propagate the upstream USB reset to downstream devices.
USB7216C
DS00003851A-page 42 2021 Microchip Technology Inc.
9.0 OPERATIONAL CHARACTERISTICS
9.1 Absolute Maximum Ratings*
Digital Core Supply Voltage (VCORE) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +1.21 V
+3.3 V Supply Voltage (VDD33) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.6 V
Positive voltage on input signal pins, with respect to ground (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.6 V
Negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V
Positive voltage on XTALI/CLK_IN, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.63 V
Positive voltage on USB DP/DM signal pins, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0 V
Positive voltage on USB 3.2 Gen 2 USB3UP_xxxx and USB3DN_xxxx signal pins, with respect to ground. . . . . 1.21 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +150oC
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125oC
Lead Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020
HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +/-3.5 kV
Note 1: When powering this device from laboratory or system power supplies, it is important that the absolute max-
imum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on
their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may
appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
Note 2: This rating does not apply to the following pins: All USB DM/DP pins, XTAL1/CLK_IN, XTALO and
VBUS_MON_UP.
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating
only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional
operation of the device at any condition exceeding those indicated in Section 9.2, Operating Conditions**, Section 9.5,
DC Specifications, or any other applicable section of this specification is not implied.
9.2 Operating Conditions**
Digital Core Supply Voltage (VCORE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.09 V to +1.21 V
+3.3 V Supply Voltage (VDD33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to +3.6 V
Input Signal Pins Voltage (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V
XTALI/CLK_IN Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V
USB 2.0 DP/DM Signal Pins Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +5.5 V
USB 3.2 Gen 2 USB3UP_xxxx and USB3DN_xxxx Signal Pins Voltage . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +1.21 V
Ambient Operating Temperature in Still Air (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 3
Digital Core Supply Voltage Rise Time (TRT in Figure 9-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ms
+3.3 V Supply Voltage Rise Time (TRT in Figure 9-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ms
Note 3: 0oC to +70oC for commercial version, -40oC to +85oC for industrial version. **Proper operation of the device
is guaranteed only within the ranges specified in this section. Do not drive input signals without power sup-
plied to the device.
2021 Microchip Technology Inc. DS00003851A-page 43
USB7216C
9.3 Package Thermal Specifications
FIGURE 9-1: SUPPLY RISE TIME MODEL
Note: The Power Supply Rise time requirement does not apply if the RESET_N signal is held low during power
on and released after power levels rise and stabilize above the power on thresholds, or if the RESET_N
signal is toggled after power supplies become stable.
TABLE 9-1: PACKAGE THERMAL PARAMETERS
Symbol °C/W Velocity (Meters/s)
JA
19 0
16 1
14 2.5
JT
0.1 0
0.1 1
JB 9 0
JC
1.3 0
1.3 1
JB 10 -
Note: Thermal parameters are measured or estimated for devices in a multi-layer 2S2P PCB per JESDN51.
t10%
10%
90%
Voltage TRT
t90% Time
100%
3.3 V
VSS
VDD33
90%
100%
VCORE
USB7216C
DS00003851A-page 44 2021 Microchip Technology Inc.
9.4 Power Consumption
This section details the power consumption of the device as measured during various modes of operation. Power dis-
sipation is determined by temperature, supply voltage, and external source/sink requirements.
TABLE 9-2: DEVICE POWER CONSUMPTION
Typical (mA) @ 25°C Typical Power
VCORE (1.15V) VDD33 (3.3V) (mW)
Global Suspend 9.6 14.5 59
VBUS Off 9.4 13.8 56
Reset 4.2 0.2 5
Data for Calculating Active Transfer Current
Upstream Port Link Speed Base Currents
SS+ Current 410 30.8
SS Current 370 27.3
HS Current 58 19.7
Additional Current Per Enabled Port
SS+ Current 179 11.1
SS Current 143 9.1
HS Current 1 10.8
Example Active Data Transfer Current Calculation: 1 SS+ Port and 2 HS Ports
Active Data Transfer Current (mA @ 3.3V) {30.8} + {1 * 11.1} + {2 * 10.8} = 63.5
Active Data Transfer Current (mA @ 1.15V) {410} + {1 * 179} + {2 * 1} = 591
Note: In the Active Idle and Active Data Transfer sections of Table 9-2, the various port configurations are indi-
cated via the following acronyms:
SS+ = USB 3.2 SuperSpeed+ (Gen 2)
SS = USB 3.2 SuperSpeed (Gen 1)
HS = USB 2.0 High Speed
VIH (I T IHT VILT VOH ‘OH VOL 0L VIH
2021 Microchip Technology Inc. DS00003851A-page 45
USB7216C
9.5 DC Specifications
Note 4: XTALI can optionally be driven from a 25 MHz singled-ended clock oscillator.
Note 5: Refer to the USB 3.2 Gen 2 Specification for USB DC electrical characteristics.
TABLE 9-3: I/O DC ELECTRICAL CHARACTERISTICS
Parameter Symbol Min Typical Max Units Notes
I Type Input Buffer
Low Input Level
High Input Level
VIL
VIH 2.1
0.9 V
V
IS Type Input Buffer
Low Input Level
High Input Level
Schmitt Trigger Hysteresis
(VIHT - VILT)
VIL
VIH
VHYS
2.1
100 160
0.9
240
V
V
mV
O12 Type Output Buffer
Low Output Level
High Output Level
VOL
VOH VDD33-0.4
0.4 V
V
IOL = 12 mA
IOH = -12 mA
OD12 Type Output Buffer
Low Output Level VOL 0.4 V IOL = 12 mA
ICLK Type Input Buffer
(XTALI Input)
Low Input Level
High Input Level
VIL
VIH 1.1
0.35 V
V
Note 4
IO-U Type Buffer
(See Note 5)
Note 5
Ptvnoaafl VDD33
USB7216C
DS00003851A-page 46 2021 Microchip Technology Inc.
9.6 AC Specifications
This section details the various AC timing specifications of the device.
9.6.1 POWER SUPPLY AND RESET_N SEQUENCE TIMING
There is no specific requirement for power sequencing of VDD33 and VCORE for device operation. Figure 9-2 illustrates
the recommended power supply sequencing for ensuring long term reliability of the device. VCORE should rise after or
at the same time as VDD33. Similarly, RESET_N should rise after or at the same time as VDD33. RESET_N does not
have any other timing dependencies. The rise times for VCORE and VDD33 are provided in Section 9.2, Operating Con-
ditions** and Figure 9-1.
9.6.2 POWER-ON AND CONFIGURATION STRAP TIMING
Figure 9-3 illustrates the configuration strap valid timing requirements in relation to power-on, for applications where
RESET_N is not used at power-on. In order for valid configuration strap values to be read at power-on, the following
timing requirements must be met. The operational levels (Vopp) for the external power supplies are detailed in
Section 9.2, Operating Conditions**.
Device configuration straps are also latched as a result of RESET_N assertion. Refer to Section 9.6.3, Reset and Con-
figuration Strap Timing for additional details.
FIGURE 9-2: POWER SUPPLY AND RESET_N SEQUENCE TIMING
TABLE 9-4: POWER SUPPLY AND RESET_N SEQUENCE TIMING
Symbol Description Min Typ Max Units
tVDD33 VDD33 to VCORE rise delay 0 ms
treset VDD33 to RESET_N rise delay 0 ms
FIGURE 9-3: POWER-ON CONFIGURATION STRAP VALID TIMING
TABLE 9-5: POWER-ON CONFIGURATION STRAP LATCHING TIMING
Symbol Description Min Typ Max Units
tcsh Configuration strap hold after external power supplies at opera-
tional levels
1 ms
VDD33
VCORE
RESET_N
All External
Power Supplies
Vopp
Configuration
Straps
tcsh
rsua ‘csn TsMEust SMEUSiRDV
2021 Microchip Technology Inc. DS00003851A-page 47
USB7216C
9.6.3 RESET AND CONFIGURATION STRAP TIMING
Figure 9-4 illustrates the RESET_N pin timing requirements and its relation to the configuration strap pins. Assertion of
RESET_N is not a requirement. However, if used, it must be asserted for the minimum period specified. Refer to
Section 8.11, Resets for additional information on resets. Refer to Section 3.3, Configuration Straps and Programmable
Functions for additional information on configuration straps.
9.6.4 POWER-ON OR RESET TO SMBUS SLAVE READY TIMING
Figure 9-5 illustrates the SMBus Slave interface readiness in relation to power-on or de-assertion of RESET_N. In order
to ensure reliable SMBus slave operation, the SMBus master must allow the bus to remain idle until tSMBUS_RDY timing
has been met. The operational levels (Vopp) for the external power supplies are detailed in Section 9.2, Operating Con-
ditions**.
FIGURE 9-4: RESET_N CONFIGURATION STRAP TIMING
TABLE 9-6: RESET_N CONFIGURATION STRAP TIMING
Symbol Description Min Typ Max Units
trstia RESET_N input assertion time 5 s
tcsh Configuration strap pins hold after RESET_N deassertion 1 ms
Note: The clock input must be stable prior to RESET_N deassertion.
Configuration strap latching and output drive timings shown assume that the Power-On reset has finished
first otherwise the timings in Section 9.6.2, Power-On and Configuration Strap Timing apply.
FIGURE 9-5: POWER-ON OR RESET TO SMBUS SLAVE READY TIMING
TABLE 9-7: POWER-ON OR RESET TO SMBUS SLAVE READY TIMING
Symbol Description Min Typ Max Units
tSMBUS_RDY Power-on or RESET_N deassertion to SMBus ready 40 ms
RESET_N
Configuration
Straps
trstia
tcsh
All External
Power Supplies
& Reset
V
opp
SMBus
SMBus commands accepted
(if SMBus slave interface is enabled)
SMBus interface not available
(slave interface will stretch clock if addressed)
Power-on-Reset
SOC_CFG STAGE
TATTACHjuv— X )6»: ATTACH RDV
USB7216C
DS00003851A-page 48 2021 Microchip Technology Inc.
9.6.5 USB ATTACH COMMAND TO SMBUS SLAVE READY TIMING
Figure 9-6 illustrates the SMBus Slave interface readiness in relation to ACK of the Slave interface to the “USB Attach
with SMBus Runtime Access” (AA56h) from the SMBus Master. In order to ensure reliable SMBus slave operation, the
SMBus master must allow the bus to remain idle after issuing the “USB Attach with SMBus Runtime Access” until tAT-
TACH_RDY timing has been met.
Note 6: The tATTACH_RDY values are preliminary and subject to change.
9.6.6 USB TIMING
All device USB signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Uni-
versal Serial Bus Specification. Please refer to the Universal Serial Bus Revision 3.2 Specification, available at http://
www.usb.org/developers/docs.
9.6.7 SMBUS TIMING
All device SMBus signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Sys-
tem Management Bus Specification. Please refer to the System Management Bus Specification, Version 1.0, available
at http://smbus.org/specs.
9.6.8 I2C TIMING
All device I2C signals conform to the 100KHz Standard-mode (Sm) and 400KHz Fast Mode (Fm) voltage, power, and
timing characteristics/specifications as set forth in the I2C-Bus Specification. Please refer to the I2C-Bus Specification,
available at http://www.nxp.com/documents/user_manual/UM10204.pdf.
9.6.9 I2S TIMING
All device I2S signals conform to the voltage, power, and timing characteristics/specifications as set forth in the I2S-Bus
Specification. Please refer to the I2S-Bus Specification, available at www.sparkfun.com/datasheets/BreakoutBoards/
I2SBUS.pdf
Note: When accessing SMBus during runtime, it is critical to force some clocks to stay on. If this step is not taken,
the SMBus slave interface will not be accessible while the hub is placed into a Suspend state by the host.
FIGURE 9-6: USB ATTACH COMMAND TO SMBUS SLAVE READY TIMING
TABLE 9-8: USB ATTACH COMMAND TO SMBUS SLAVE READY TIMING
Symbol Description Min Typ Max Units
tATTACH_RDY USB Attach command to SMBus ready (Note 6) 11.5 ms
SMBus
SMBus commands accepted
(if ‘Attach with I2C slave enabled during
runtime’ command is used)
SMBus interface not available
(slave interface will stretch clock if address ed)
SOC_CFG Stage
Attach
Command ACK
Runtime StageSOC_CFG S tage
At tach
Command
2021 Microchip Technology Inc. DS00003851A-page 49
USB7216C
9.6.10 SPI/SQI MASTER TIMING
This section specifies the SPI/SQI master timing requirements for the device.
FIGURE 9-7: SPI/SQI MASTER TIMING
TABLE 9-9: SPI/SQI MASTER TIMING (30 MHZ OPERATION)
Symbol Description Min Typ Max Units
tfc Clock frequency 30 MHz
tceh Chip enable (SPI_CE_N) high time 100 ns
tclq Clock to input data 13 ns
tdh Input data hold time 0 ns
tos Output setup time 5 ns
toh Output hold time 5 ns
tov Clock to output valid 4 ns
tcel Chip enable (SPI_CE_N) low to first clock 12 ns
tceh Last clock to chip enable (SPI_CE_N) high 12 ns
TABLE 9-10: SPI/SQI MASTER TIMING (60 MHZ OPERATION)
Symbol Description Min Typ Max Units
tfc Clock frequency 60 MHz
tceh Chip enable (SPI_CE_N) high time 50 ns
tclq Clock to input data 9 ns
tdh Input data hold time 0 ns
tos Output setup time 5 ns
toh Output hold time 5 ns
tov Clock to output valid 4 ns
tcel Chip enable (SPI_CE_N) low to first clock 12 ns
tceh Last clock to chip enable (SPI_CE_N) high 12 ns
SPI_CLK
SPI_D[3:0] (in)
SPI_D[3:0] (out)
SPI_CE_N
tcel tfc
Output
data valid
tclq
tceh
tdh
toh
tos tov toh
Output
data valid
Input
data valid
tceh
l:| Crystal Cut AT. typ Crystal Oscillation Mode Fundamental Mode Crystal Calibration Mode Parallel Resonant Mode Frequency F » 25.000 - MHZ Frequency Tolerance @ 25°C F » - :50 PPM Frequency Stability Over Temp F » - :50 PPM Frequency Deviation Over Time F » 13 to 5 - PPM Note 7 Total Allowable PPM Budget » - 1100 PPM Shunt Capacitance C » 7 typ - pF Load Capacitance C » 20 typ - pF Drive Level P 100 - - uW Equivalent Series Resistance R » - 60 0 Operating Temperature Range Note 8 - Note 9 °C XTALI/CLKJN Pin Capacitance » 3 typ - pF Note 10 XTALD Pin Capacitance » 3 typ - pF Note 10
USB7216C
DS00003851A-page 50 2021 Microchip Technology Inc.
9.7 Clock Specifications
The device can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator input. If the single-ended clock
oscillator method is implemented, XTALO should be left unconnected and XTALI/CLK_IN should be driven with a
nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals
(XTALI/XTALO). The following circuit design (Figure 9-8) and specifications (Table 9-11) are required to ensure proper
operation.
9.7.1 CRYSTAL SPECIFICATIONS
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals
(XTALI/XTALO). Refer to Table 9-11 for the recommended crystal specifications.
FIGURE 9-8: 25MHZ CRYSTAL CIRCUIT
TABLE 9-11: CRYSTAL SPECIFICATIONS
Parameter Symbol Min Nom Max Units Notes
Crystal Cut AT, typ
Crystal Oscillation Mode Fundamental Mode
Crystal Calibration Mode Parallel Resonant Mode
Frequency Ffund - 25.000 - MHz
Frequency Tolerance @ 25oC Ftol - - ±50 PPM
Frequency Stability Over Temp Ftemp - - ±50 PPM
Frequency Deviation Over Time Fage - ±3 to 5 - PPM Note 7
Total Allowable PPM Budget - - ±100 PPM
Shunt Capacitance CO- 7 typ - pF
Load Capacitance CL- 20 typ - pF
Drive Level PW100 - - uW
Equivalent Series Resistance R1- - 60 Ω
Operating Temperature Range Note 8 -Note 9 oC
XTALI/CLK_IN Pin Capacitance - 3 typ - pF Note 10
XTALO Pin Capacitance - 3 typ - pF Note 10
USB7216C
XTALO
XTALI
Y1
C
1
C
2
2021 Microchip Technology Inc. DS00003851A-page 51
USB7216C
Note 7: Frequency Deviation Over Time is also referred to as Aging.
Note 8: 0 °C for commercial version, -40 °C for industrial version.
Note 9: +70 °C for commercial version, +85 °C for industrial version.
Note 10: This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included in this
value. The XTALI/CLK_IN pin, XTALO pin and PCB capacitance values are required to accurately calcu-
late the value of the two external load capacitors. These two external load capacitors determine the accu-
racy of the 25.000 MHz frequency.
9.7.2 EXTERNAL REFERENCE CLOCK (CLK_IN)
When using an external reference clock, the following clock characteristics are required:
• 25 MHz
• 50% duty cycle ±10%, ±100 ppm
• Jitter < 100 ps RMS
,/,,,, ‘3‘ USB7216Ci RnnnO YYWWNNN | V k | I’ | J
USB7216C
DS00003851A-page 52 2021 Microchip Technology Inc.
10.0 PACKAGE OUTLINE
10.1 Package Marking Information
*Standard device marking consists of Microchip part number, year code, week code and traceability code.
For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
Legend: iTemperature range designator (Blank = commercial, i = industrial)
R Product revision
nnn Internal code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
YY Year code (last two digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
100-VQFN (12x12 mm)
PIN 1
e3
Q i EC: TOP VIEW D2 $-na 1 SIDE VIEW TUUUUUUUUULIUUUUUUUUU UU g I E 69 o.1o® c A B I +i7i7 7%» E2 E E K BOTTOM VIEW C C AIBI Mmrochlp Technmogy Drawmg comm Rev B
2021 Microchip Technology Inc. DS00003851A-page 53
USB7216C
10.2 Package Drawings
Note: For the most current package drawings, see the Microchip Packaging Specification at:
http://www.microchip.com/packaging.
FIGURE 10-1: 100-VQFN PACKAGE (DRAWING)
%
$
 &
 &
 & $ %
 &
'$780%
'$780$
127(
1
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%277209,(:
127(
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 & $ %
 & $ %
0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY%6KHHWRI
'
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6((
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FIGURE 10-2: 100-VQFN PACKAGE (DIMENSIONS) $55ng Termmal Le m Notes 1, Fm 2, Pa 3, Dwm
USB7216C
DS00003851A-page 54 2021 Microchip Technology Inc.
FIGURE 10-2: 100-VQFN PACKAGE (DIMENSIONS)
0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY%6KHHWRI
1XPEHURI7HUPLQDOV
2YHUDOO+HLJKW
7HUPLQDO:LGWK
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7HUPLQDO/HQJWK
([SRVHG3DG:LGWK
7HUPLQDO7KLFNQHVV
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8QLWV
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$
E
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0,//,0(7(56
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0$;
. 
5()5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
%6&%DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
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Notes:
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
3DFNDJHLVVDZVLQJXODWHG
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
7HUPLQDOWR([SRVHG3DG
2YHUDOO/HQJWK
([SRVHG3DG/HQJWK
'
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%6&
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&
6($7,1*
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FIGURE 10-3: 100-VQFN PACKAGE (LAND-PATTERN) 7 . 1:Hflflflflflflflflflflflflflflfl‘flflfl'flfl[mi—I ‘ g 22322:? g i¢_§__ZZZZZZ E
2021 Microchip Technology Inc. DS00003851A-page 55
USB7216C
FIGURE 10-3: 100-VQFN PACKAGE (LAND-PATTERN)
RECOMMENDED LAND PATTERN
Dimension Limits
Units
C2
Optional Center Pad Width
Contact Pad Spacing
Optional Center Pad Length
Contact Pitch
Y2
X2
8.10
8.10
MILLIMETERS
0.40 BSC
MIN
E
MAX
11.70
Contact Pad Length (X100)
Contact Pad Width (X100)
Y1
X1
1.05
0.20
Microchip Technology Drawing C04-2407A
NOM
SILK SCREEN
12
100
C1
C2
E
X1
Y1
G1
Y2
X2
C1Contact Pad Spacing 11.70
Contact Pad to Center Pad (X100) G1 0.20
Thermal Via Diameter V
Thermal Via Pitch EV
0.33
1.20
ØV
EV
EV
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M
For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
1.
2.
USB7216C
DS00003851A-page 56 2021 Microchip Technology Inc.
APPENDIX A: REVISION HISTORY
TABLE A-1: REVISION HISTORY
Revision Level & Date Section/Figure/Entry Correction
00003851A (02-16-21) initial release
PART NO. [X] XXX I? T Dev a pa ck —> DIRECTION OF UNREELING rt
2021 Microchip Technology Inc. DS00003851A-page 57
USB7216C
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X] XXX
PackageTemperature
Range
Device
Device: USB7216C
Tape and Reel
Option:
Blank = Standard packaging (tray)
T = Tape and Reel (Note 1)
Temperature
Range:
Blank = 0C to +70C (Commercial)
I = -40C to +85C (Industrial)
Package: KDX = 100-pin VQFN
Examples:
a) USB7216C/KDX
Tray, 0C to +70C, 100-pin VQFN
b) USB7216CT/KDX
Tape & reel, 0C to +70C, 100-pin VQFN
c) USB7216C-I/KDX
Tray, -40C to +85C, 100-pin VQFN
d) USB7216CT-I/KDX
Tape & reel, -40C to +85C, 100-pin VQFN
Note 1: Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
[X](1)
Tape and Reel
Option
-
/
USB7216C
DS00003851A-page 58 2021 Microchip Technology Inc.
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-
tains the following information:
•Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
•General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
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•Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-
nars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-
cation” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-
ment.
Technical support is available through the web site at: http://microchip.com/support
IN NO EVENT WILL MICROCHIP BE LIABLE FORANY INDIRECT: SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS‘ DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE‘ HOWEVER
2021 Microchip Technology Inc. DS00003851A-page 59
USB7216C
Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Information
regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsi-
bility to ensure that your application meets with your specifications.
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF
ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMA-
TION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FIT-
NESS FOR A PARTICULAR PURPOSE OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS,
DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER
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FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFOR-
MATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR
THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees
to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No
licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch,
MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo,
PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other
countries.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion,
SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom,
CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip
Connectivity, JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK,
NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker,
RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II,
Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and
ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in
other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2021, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 9781522476764
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specifications contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip
devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications
contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished
without violating Microchip's intellectual property rights.
• Microchip is willing to work with any customer who is concerned about the integrity of its code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not
mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are
committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection
feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or
other copyrighted work, you may have a right to sue for relief under that Act.
For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.
6‘ MICRDCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
2021 Microchip Technology Inc. DS00003851A-page 60
AMERICAS
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02/28/20