Another important application for the PLL frequency synthesizer is generating a conversion clock for high speed data converters. In an IF sampling radio receiver architecture the high-speed ADC must have excellent aperture jitter to acquire signals at high intermediate frequencies. Jitter is the time domain expression of phase noise. At a given input frequency the ADC signal-to-noise ratio is influenced by aperture jitter and conversion clock jitter.
 
                 
                 
                 
 
 
 
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