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Sampling clock jitter and aperture jitter produce a degradation in the ADC SNR as shown in this diagram. The horizontal axis is the full-scale sinewave input frequency. The vertical axis is the SNR due only to jitter (assuming an otherwise perfect ADC). The SNR is expressed in ENOB on the right-hand vertical axis. An example of the stringent requirements on the sampling clock can be seen by assuming a 100MHz full-scale IF input signal. Assume that an SNR equivalent to 14-bits is desired, the total jitter must be between 50fs and 100fs. This is difficult to accomplish. It is a real limiting factor in IF sampling applications and cannot be overlooked.
PTM Published on: 2009-08-24
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